Brother HL-720 - B/W Laser Printer Service Manual page 27

<HL-730/730Plus>
The ASIC is composed of Cell Based IC and has the following function blocks.
(1) Oscillator circuit
Generates the main clock for the CPU by dividing the source clock frequency into
two.
(2) Address decoder
Generates the CS for each device.
(3) DRAM control
Generates the RAS, CAS, WE, OE and MA signals for the DRAM and controls
refresh recessing (CAS before RAS self-refreshing method).
(4) Interrupt control
Interrupt levels:
Priority High 7
6
5
4
3
2
Low 1
(5) Timers
The following timers are incorporated:
Timer 1 16-bit timer
Timer 2 10-bit timer
Timer 3 Watch-dog timer
(6) FIFO
A 5,120-bit FIFO is incorporated. Data for one raster is transferred from the RAM
to the FIFO by DMA transmission and is output as serial video data. The data cycle
is 6.13 MHz.
NMI
FIFO
EXINT(Option Serial I/O)
BD / Timer 1
SCANINT
CDCC / BOISE / DATA EXTENTION
Timer 2
II-10