S4 Post Codes - JETWAY 939GT4SLIR311 User Manual

Code(hex) Name
77 Display POST error
78 CMOS and Option
ROM Init
79 Reserved
7A Reserved
7B Reserved
7C Reserved
7D Boot Medium
detection
7E Final Init
7F Special KBC patch
80 Boot Attempt
FF Boot

S4 POST Codes

Code(hex) Name
5A Early Chipset Init
5B Cmos Check
5C Chipset default
Prog
5D Identify the CPU
5E Setup Interrupt
Vector Table
5F Test CMOS
Interface and
Battery status
60 KBC final Init
Description
Check POST error and display them
and ask for user intervention
Ask password security (optional).
Write all CMOS values back to RAM and
clear screen.
Enable parity checker
Enable NMI, Enable cache before boot.
Initialize any option ROMs present
from C8000h to EFFFFh.
NOTE: When FSCAN option is enabled,
ROMs initialize from C8000h to
F7FFFh.
Read and store boot partition head and
cylinders values in RAM
Final init for last micro details
before boot
Set system speed for boot
Setup NumLock status according to
Setup
Set low stack
Boot via INT 19h.
Description
Early Initialized the super IO
Reset Video controller
Keyboard controller init
Test the Keyboard
Initilized the mouse
Check Cmos Circuitry and reset CMOS
Program the chipset registers with
CMOS values. Init onboard clock
generator
Check the CPU ID and init L1/L2 cache
Initialize first 120 interrupt
vectors with SPURIOUS_INT_HDLR and
INT 00h-1Fh according to INT_TBL
First step initialize if single CPU
Onboard. Re-init KB
If support HPM, HPM get initialized
Here.
Verifies CMOS is working correctly,
detects bad battery. If failed, load
CMOS defaults and load into chipset
Final Initial KBC and setup BIOS data
area
i7