TYAN TIGER K8SSA Manual page 74

Feature
NorthBridge Chipset Configuration
Min Active RAS (Tras)
Row Precharge Time
(Trp)
RAS/RAS Delay (Trrd)
Row Cycle (Trc)
Row Refresh Cycle
(Trfc)
Read Write Delay
(Trwt)
Read Preamble
Asynchronous Latency
Option
This setting allows you to select the
number of clock cycles allotted for the
RAS pulse width, according to DRAM
Read only
specifications. The less the clock
cycles, the faster the DRAM
performance.
This item controls the number of cycles
for Row Address Strobe (RAS) to be
allowed to precharge. If insufficient
time is allowed for the RAS to
Read only
accumulate its chage before DRAM
refresh, refresh may be incomplete and
DRAM may fail to retain data. This
item applies only when synchronous
DRAM is installed in the system.
Auto uses hardware compensation
values. Other values add to or subtract
Read only
from hardware generated value.
Recommended setting is Auto.
Bits 7-4. RAS#-active to RAS#-active
Read only
or auto refresh of the same bank.
Bits 11-8. Auto-refresh-active to
Read only
RAS#-active or RAS# auto-refresh.
Bits 6-4. Specifies the read-to-write
delay. This is not a DRAM-specified
timing parameter, but must be
considered due to routing latencies on
Read only
the clock forwarded bus. It is counted
from the first address bus slot that was
not associated with part of the read
burst.
Bits 11-8. The time prior to the max-
read DQS-return when the DQS
receiver should be turned on. This is
specified in units of 0.5ns. The
controller needs to know when to
Read only enable its DQS receiver in anticipation
of the DRAM DQS driver turning on for
a read. The controller will disable its
DQS receiver until the read preamble
time and then enable its DQS receiver
while the DRAM asserts DQS.
Bits 3-0. This filed should be loaded
with a 4-bit value equal to the
Read only
maximum asynchronous latency in the
DRAM read round-trip loop.
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Description