Management Processor Overview - HP AB500A - Integrated Lights-Out Advanced Technology Brief

Management processor overview

As indicated in Figure 1, the iLO 2 management processor includes the following chip architecture:
• 66-MHz RISC processor core with separate instruction set and integrated data cache
• Memory controller
• 4 megabytes (MB) of flash ROM
• 16 megabytes of memory (SDRAM)
• 24-MHz digital video redirection engine
• Dedicated 10/100 or at host NIC speed
Like the first-generation iLO processor, iLO 2 is a 32-bit, PCI-based processor. iLO 2 improvements
include more memory and a new digital video redirection (DVR) engine. The aspects discussed in the
following paragraphs apply to both first-generation iLO and the iLO 2 device.
The NIC and associated RJ-45 management (Mgmt) port are independent of the 10/100/1000
Ethernet interface(s) provided by the host server.
Figure 1. This block diagram shows the configuration of the HP iLO 2 management processor. It is based on thel
iLO processor, and adds enhancements including more memory and an updated digital video redirection.
RJ-45
Ethernet
Management
Port
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