Related Manuals for IBM 160
Summarization of Contents
Notices
Electronic Emission Notices
Information regarding electronic emission notices, including FCC statements.
Trademarks and Service Marks
List of trademarks and service marks used in this publication.
Product Safety Information
General Safety
General safety guidelines and compliance with IBM safety standards.
Safety Notices
Safety notices and warnings related to maintenance information procedures.
Service Inspection Procedures
Procedures for service personnel to check 3745 safety criteria.
About This Book
Who Should Use This Book
Identifies the intended audience for this manual, including required knowledge.
Service Personnel Definitions
Defines terms relevant to service personnel.
How to Use the Maintenance Library
Explains the process of performing maintenance and interacting with the HCS.
Where to Find More Information
Directs users to additional resources for problem analysis and techniques.
Chapter 1. General Information
3745 in a Network
Describes how the 3745 Communication Controller connects to a network.
Identification and Capacity
Details the identification and connection capabilities of various 3745 models.
Controller Structure
Outlines the four functional areas of the 3745 controller.
Communication Subsystem
Describes the communication subsystem and its four types of line connections.
Low-/Medium-Speed Transmission Subsystem (TSS)
Details the TSS subsystem, including LSS and LIB components.
High-Performance Transmission Subsystem (HPTSS)
Describes the HPTSS, consisting of high-speed scanners (HSS).
Ethernet Subsystem (ESS)
Details the ESS, which attaches up to two Ethernet LAN adapters (ELA).
Token-Ring Subsystem (TRSS)
Describes the TRSS, consisting of token-ring multiplexer and interface couplers.
Maintenance and Operator Subsystem (MOSS)
Explains the MOSS functions, including initialization and problem determination.
Programming Support and Network Management
Covers host-resident programs, operating systems, access methods, and network management.
Controller-Resident Programs
Describes the programs that run within the 3745 controller.
Generating and Loading the Control Program
Details the process of generating and loading the control program.
Preventive Maintenance
Explains preventive maintenance procedures, including battery replacement.
Maintenance Aids
Lists tools and test equipment used for maintenance.
Chapter 2. Central Control Unit (CCU)
The CCU in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the CCU data flow for specific 3745 models.
The CCU in 3745 Model 17A Data Flow
Diagram illustrating the CCU data flow for the 3745 Model 17A.
General Description
Provides a general overview of the 3745's Central Control Unit (CCU).
Data Flow
Details the data flow within the CCU's Control Subsystem (CSS).
Packaging
Describes the packaging of the communication subsystem (CSS) components.
Functional Description
Explains the functions of the central control unit (CCU) as an interrupt-driven processor.
Program Levels
Details the five operational program levels within the controller hardware.
Interrupts
Explains the priority system used for handling interrupt requests.
Instruction Set
Lists the 53 executable instructions available for the 3745.
CCU Environment
Illustrates the interconnections to the CCU, including buses and control logic.
CCU Subsystem Power-ON Reset (POR)
Describes the Power-ON Reset (POR) activation and storage control sequence.
Main Storage
Details the main storage, which contains the control program.
Storage Environment
Explains how main storage communicates with the CCU and high-speed adapters.
Direct Memory Access and Storage Control (SCTL)
Details the functions of the SCTL card for DMA and storage control.
CCU-to-Storage Interconnection
Explains the interconnection between the CCU and storage, including cache.
Cache Storage
Describes the cache storage, providing instructions and data at cycle rate.
Storage Protection
Explains storage protection and address exception (SP/AE) mechanisms.
Main Storage Protection State
Details the states a main storage position can be in regarding protection.
CCU Timers
Describes the two available timers: 100 ms interval timer and high/low resolution timer.
CCU to and from Adapters
Explains CCU interconnections with adapters via the IOC bus.
IOC Control Logic
Describes how IOC logic operates depending on program or adapter initiation.
IOC Data Flow
Details the I/O bus data flow and registers.
Level 2 and Level 3 Interrupt Reporting
Explains how level 2 and level 3 interrupt requests are reported.
Level 1 Interrupt Reporting
Explains how level 1 interrupt requests are reported.
Registers
Describes the two types of registers: general and external.
General Registers
Details the forty general registers available for program use.
Instruction Address Register (IAR)
Describes the instruction address register (IAR).
External Registers
Explains external registers not directly accessible by the control program.
Hardware Registers
Lists hardware registers used to store and pass essential controller operation information.
Chapter 3. Buses
The Buses in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram showing bus data flow for 3745 models 130, 150, 160, and 170.
The Buses in 3745 Model 17A Data Flow
Diagram showing bus data flow for the 3745 Model 17A.
Generalities
Describes the two types of buses connecting adapters to CCU/SCTL.
IOC Bus
Details the IOC bus, including data, address, and control exchanges.
IOC Bus Protocol
Explains the protocol for the IOC bus, with examples like read PIO.
CCU-Bus Layout (Maximum Configuration)
Diagram illustrating the CCU-bus layout for maximum configuration.
CCU/Adapters Interconnection
Explains the interconnection between CCU and adapters via buses.
DMA Bus
Describes the DMA bus used for data transfer between CCU storage and high-speed adapters.
PIO Operation
Details the PIO operation sequence, including steps and initiated by CCU or MOSS.
AIO Operation
Explains the AIO operation, also known as cycle stealing.
Bus Propagation Cards (BPC1/BPC2)
Details the bus propagation cards (BPC1/BPC2) and their configuration rules.
3746-900/3745 Attachment
Describes the attachment of the 3746-900 to the 3745.
Adapter Addressing
Explains logical and physical adapter addressing.
Logical Adapter Address
Describes the composition of a logical adapter address.
Physical Address Wiring
Details the physical address wiring for adapters.
CA Addressing
Explains the CA addressing scheme in PIO mode.
Line Adapter Addressing (LSS, HSS, and ELA)
Details line adapter addressing for LSS, HSS, and ELA.
3746 Model 900 Adapter Addressing (CBC, PRC)
Explains adapter addressing for the 3746 Model 900 (CBC, PRC).
LIC Board Addressing
Describes LIC board addressing using a seven-position switch.
Line Addressing
Explains line numbering based on LIC board type and configuration.
LIC1 LIC3 LIC4A and LIC4B Addressing
Details the addressing for LIC1, LIC3, LIC4A, and LIC4B.
TSS Line Addressing for LICs 1-4
Provides TSS line addressing for LIC types 1-4.
LIC5 and LIC6 Addressing
Details LIC5 and LIC6 addressing.
Port Position for LIC Type 5 and LIC Type 6 at 9.6 and 19.2 kbps
Describes port positions for LIC types 5 and 6 at specific speeds.
Port Position for LIC Type 6 at 56 kbps
Describes port positions for LIC type 6 at 56 kbps.
TSS Line Addressing for LICs 5-6
Provides TSS line addressing for LIC types 5-6.
HPTSS Line Addressing
Details HPTSS line addressing.
ESS Line Addressing
Details ESS line addressing.
Token-Ring Adapter (TRA) Addressing
Explains the addressing for Token-Ring Adapters (TRA).
Token-Ring Line Addressing
Describes token-ring line addressing.
Adapter Bypass Mechanism
Explains the bypass mechanism for adapters.
BPC Card Installation Rules (Model 170)
Provides rules for installing BPC cards on Model 170.
Cycle Steal Grant (CSG) and Autoselection Mechanism for Model 170
Details CSG and autoselection mechanisms for Model 170.
IOC Bus Scoping Routine
Explains the PIO scoping routine for PIO tags and data bus.
How to Start the Routine
Provides instructions on how to start the IOC bus scoping routine.
Adapter Selection
Explains how to select an adapter for MIOH operation.
Parameter Description
Describes the parameters used in MIOH operations.
RACs Generated
Lists RACs generated when the scoping routine does not run.
Error Bit (ERR)
Details the error bit patterns displayed with RACs.
Chapter 4. Transmission Subsystem (TSS)
The TSS in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the TSS data flow for specific 3745 models.
The TSS in 3745 Model 17A Data Flow
Diagram illustrating the TSS data flow for the 3745 Model 17A.
Definitions
Defines low-speed scanners (LSSs) associated with LIC boards.
Low-Speed Scanner (LSS)
Details the LSS, consisting of CSP and FESL.
Communication Scanner Processor (CSP)
Describes the CSP, its functions, and components.
Front-End Scanner Low-Speed (FESL)
Explains the FESL's role in connecting CSP and LIC units.
LIC Board
Describes the LIC board, consisting of multiplexer and interface coupler cards.
Multiplexer Card (MUX)
Details Multiplexer Cards (MUXs), including DMUX functions.
Single Multiplexer Card (SMUX)
Describes SMUXA/B cards and their functions.
Line Interface Coupler (LIC)
Explains the LIC's function and its attachment to FDX/HDX lines.
LIC Types 1 to 4 Characteristics
Details characteristics of LIC types 1 to 4.
LIC Types 5/6 Characteristics
Details characteristics of LIC types 5 and 6.
Line Weights
Explains line weights and their calculation for scanner occupation.
Chapter 5. High Performance Transmission Subsystem (HPTSS)
The HPTSS in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the HPTSS data flow for specific 3745 models.
The HPTSS in 3745 Model 17A Data Flow
Diagram illustrating the HPTSS data flow for the 3745 Model 17A.
Introduction
Introduces the HPTSS, its capabilities, and system environment.
System Environment
Describes the system environment for HPTSS, including network standards.
ELA Packaging
Details the ELA packaging, consisting of CSP and EAC cards.
Line Addressing
Explains line addressing for HSS and the TD1 field of the IOH.
HSS Commands
Lists NCP commands supported by the HSS.
Interface Types
Describes the two types of line interface available at the FESH card exit.
HPTSS Data Flow
Diagram illustrating the HPTSS data flow.
CSP Microcode Summary
Lists the main microcode functions supported by the HSS.
Internal Interconnections
Explains how each HSS interconnects with CSS and MOSS.
CSP-to-IOC Bus
Details the CSP-to-IOC bus connection and its uses.
NCP-HSS Microcode
Explains how CCU exchanges data with HSS CSP.
CLDP-HSS Microcode
Describes the controller load/dump program used for remote 3745 interconnection.
FESH to CSP
Explains the physical interconnection between FESH and CSP.
Microcode to FESH
Describes how microcode is loaded from CSP into FESH RAM.
Data Transmission
Explains data transmission commands issued by CSP microcode to FESH.
Chapter 6. The Token-Ring Subsystem
The TRSS in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the TRSS data flow for specific 3745 models.
The TRSS in 3745 Model 17A Data Flow
Diagram illustrating the TRSS data flow for the 3745 Model 17A.
Token-Ring Network
Describes token-ring networks and their design approach.
IBM Token-Ring Network
Explains IBM Token-Ring as an information transport system.
Cabling System (Ring)
Details the transmission media used for token-ring networks.
Token-Ring Adapter
Describes the functions of the token-ring adapter in the 3745.
The Token-Ring Adapter in the 3745
Introduces the token-ring adapter (TRA) and its components.
Introduction
Introduces the token-ring subsystem (TRSS) and its protocol.
Packaging
Details the packaging of the token-ring adapter (TRA).
Token-Ring Interface Coupler (TIC) Card
Describes the TIC card and its functional areas.
TIC Data Flow
Explains the data flow through the TIC card on the ring.
The Front End
Describes the front end as the interface to the ring transmission line.
The Protocol Handler
Explains the protocol handler's role as a logical interconnection.
The Message Processor
Describes the message processor as the master control element.
TIC Bus Interconnection Control
Explains the mechanism for data transfer between TIC storage and CCU storage.
Receive Operation
Describes the receive operation for data from the ring.
Transmit Operation
Explains the transmit operation, reversing the receive flow.
Token-Ring Multiplexor (TRM) Card
Describes the TRM card functions and its interconnections.
IOC Bus Interconnection
Explains the IOC bus interconnection for communication.
Summary of the IOC Bus Interface Signal Lines
Lists and describes the IOC bus interface signal lines.
TIC Bus Interconnection
Explains the TIC bus interconnection.
Summary of the TIC Bus Signal Lines
Lists and describes the TIC bus signal lines.
TRM Arbitration Mechanism
Explains the arbitration logic for TRM, involving scan wheels.
TRA Resets
Details the three functions implemented to reset the TRA.
Power ON Reset and Tag Reset
Explains how Power ON reset and Tag reset are activated.
Programmed Reset
Describes how the program initiates a programmed reset.
TIC Reset
Explains how the program performs a selective reset of the TIC.
Diagnostic Section TA0A
Provides diagnostic procedures for TRM disconnection.
Error Detection and Reporting
Details error detection and reporting for TRM Level 1.
TRM Level 1 Error Status Register
Describes the TD field of the TRM Level 1 Error Status Register.
TRM Level 2 Error Status Registers
Details the two level 2 status registers provided by the TRM.
Chapter 7. Channel Adapter (CA)
The CA in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the CA data flow for specific 3745 models.
The CA in 3745 Model 17A Data Flow
Diagram illustrating the CA data flow for the 3745 Model 17A.
Introduction
Introduces the microcoded CA, its attachment, and capabilities.
Buffer Chaining Channel Adapter (BCCA)
Describes the BCCA, a new channel adapter improving performance.
Packaging
Details the packaging of CADS or BCCA on a channel adapter logic card.
Supported Features
Lists features supported by CADS and BCCA.
Non-Supported Features
Lists features not supported by CADS and BCCA.
Configuration
Explains CA configuration availability via IOC BUS.
CA Operating Environment
Describes how the CA operates with control programs and interfaces.
Modes of Operation
Details the NSC and ESC modes of operation for the CA.
Host Unit Control Word (UCW)/Host I/O Configuration Data Set (IOCDS)
Explains UCW/IOCDS requirements for the controller.
Overall Operation
Describes how the CA connects to the 370 channel and IOC bus.
Data Transfer Methods (PIO and AIO)
Explains the two methods used for data transfer between CA and CCU.
CA Instructions
Details the instructions used to control the CA.
CA States
Describes the possible states of the CA: Ready, Initial Selection, Data Transfer, Disabled.
CA Interrupt Requests
Explains the interrupt requests the CA can raise to the CCU and MOSS.
Accessing CA Registers
Describes how CA registers are accessed by the control program or MOSS.
Channel Interface Tag Signals Used by the CA
Lists the channel interface tag signals used by the CA.
Autoselection
Explains how to work with a CA through autoselection.
Autoselection Mechanism
Details the autoselection mechanism.
Autoselection (AS) Chain
Describes the AS chain for CA installation.
Autoselection Error
Explains errors detected on the 'sample' chain during autoselection.
Cycle Steal
Describes cycle steal operations and information known to the IOC.
Cycle Steal (CS) Chain
Explains the CS chain depending on CA installation order.
Removing a CA from the Cycle Steal Chain
Details how to remove a CA from the cycle steal chain safely.
CA/MOSS Connection
Explains the 16-line link connecting the MCC card to the channel adapters.
Interrupt Requests
Describes the two major classes of interrupt: CA level 1 and CA level 3.
Level 1 Interrupt Request
Details level 1 interrupt requests caused by hardware errors.
Level 3 Interrupt Request
Details level 3 interrupt requests caused by initial selection or data/status transfers.
Level 4 Interrupt
Describes level 4 interrupt requests raised to MOSS in diagnostic mode.
Accessing CA Registers
Explains how CA registers are accessed by control program or MOSS.
Channel Interface Tag Signals Used by the CA
Lists channel interface tag signals used by the CA.
Autoselection
Explains how to work with a CA through autoselection.
Autoselection Mechanism
Details the autoselection mechanism.
Autoselection (AS) Chain
Describes the AS chain for CA installation.
Autoselection Error
Explains errors detected on the 'sample' chain during autoselection.
Cycle Steal
Describes cycle steal operations and information known to the IOC.
Cycle Steal (CS) Chain
Explains the CS chain depending on CA installation order.
Removing a CA from the Cycle Steal Chain
Details how to remove a CA from the cycle steal chain safely.
Chapter 4. Transmission Subsystem (TSS)
The TSS in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the TSS data flow for specific 3745 models.
The TSS in 3745 Model 17A Data Flow
Diagram illustrating the TSS data flow for the 3745 Model 17A.
Definitions
Defines low-speed scanners (LSSs) associated with LIC boards.
Low-Speed Scanner (LSS)
Details the LSS, consisting of CSP and FESL.
Communication Scanner Processor (CSP)
Describes the CSP, its functions, and components.
Front-End Scanner Low-Speed (FESL)
Explains the FESL's role in connecting CSP and LIC units.
LIC Board
Describes the LIC board, consisting of multiplexer and interface coupler cards.
Multiplexer Card (MUX)
Details Multiplexer Cards (MUXs), including DMUX functions.
Single Multiplexer Card (SMUX)
Describes SMUXA/B cards and their functions.
Line Interface Coupler (LIC)
Explains the LIC's function and its attachment to FDX/HDX lines.
LIC Types 1 to 4 Characteristics
Details characteristics of LIC types 1 to 4.
LIC Types 5/6 Characteristics
Details characteristics of LIC types 5 and 6.
Line Weights
Explains line weights and their calculation for scanner occupation.
Chapter 5. High Performance Transmission Subsystem (HPTSS)
The HPTSS in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the HPTSS data flow for specific 3745 models.
The HPTSS in 3745 Model 17A Data Flow
Diagram illustrating the HPTSS data flow for the 3745 Model 17A.
Introduction
Introduces the HPTSS, its capabilities, and system environment.
System Environment
Describes the system environment for HPTSS, including network standards.
ELA Packaging
Details the ELA packaging, consisting of CSP and EAC cards.
Line Addressing
Explains line addressing for HSS and the TD1 field of the IOH.
HSS Commands
Lists NCP commands supported by the HSS.
Interface Types
Describes the two types of line interface available at the FESH card exit.
HPTSS Data Flow
Diagram illustrating the HPTSS data flow.
CSP Microcode Summary
Lists the main microcode functions supported by the HSS.
Internal Interconnections
Explains how each HSS interconnects with CSS and MOSS.
CSP-to-IOC Bus
Details the CSP-to-IOC bus connection and its uses.
NCP-HSS Microcode
Explains how CCU exchanges data with HSS CSP.
CLDP-HSS Microcode
Describes the controller load/dump program used for remote 3745 interconnection.
FESH to CSP
Explains the physical interconnection between FESH and CSP.
Microcode to FESH
Describes how microcode is loaded from CSP into FESH RAM.
Data Transmission
Explains data transmission commands issued by CSP microcode to FESH.
Chapter 6. The Token-Ring Subsystem
The TRSS in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the TRSS data flow for specific 3745 models.
The TRSS in 3745 Model 17A Data Flow
Diagram illustrating the TRSS data flow for the 3745 Model 17A.
Token-Ring Network
Describes token-ring networks and their design approach.
IBM Token-Ring Network
Explains IBM Token-Ring as an information transport system.
Cabling System (Ring)
Details the transmission media used for token-ring networks.
Token-Ring Adapter
Describes the functions of the token-ring adapter in the 3745.
The Token-Ring Adapter in the 3745
Introduces the token-ring adapter (TRA) and its components.
Introduction
Introduces the token-ring subsystem (TRSS) and its protocol.
Packaging
Details the packaging of the token-ring adapter (TRA).
Token-Ring Interface Coupler (TIC) Card
Describes the TIC card and its functional areas.
TIC Data Flow
Explains the data flow through the TIC card on the ring.
The Front End
Describes the front end as the interface to the ring transmission line.
The Protocol Handler
Explains the protocol handler's role as a logical interconnection.
The Message Processor
Describes the message processor as the master control element.
TIC Bus Interconnection Control
Explains the mechanism for data transfer between TIC storage and CCU storage.
Receive Operation
Describes the receive operation for data from the ring.
Transmit Operation
Explains the transmit operation, reversing the receive flow.
Token-Ring Multiplexor (TRM) Card
Describes the TRM card functions and its interconnections.
IOC Bus Interconnection
Explains the IOC bus interconnection for communication.
Summary of the IOC Bus Interface Signal Lines
Lists and describes the IOC bus interface signal lines.
TIC Bus Interconnection
Explains the TIC bus interconnection.
Summary of the TIC Bus Signal Lines
Lists and describes the TIC bus signal lines.
TRM Arbitration Mechanism
Explains the arbitration logic for TRM, involving scan wheels.
TRA Resets
Details the three functions implemented to reset the TRA.
Power ON Reset and Tag Reset
Explains how Power ON reset and Tag reset are activated.
Programmed Reset
Describes how the program initiates a programmed reset.
TIC Reset
Explains how the program performs a selective reset of the TIC.
Diagnostic Section TA0A
Provides diagnostic procedures for TRM disconnection.
Error Detection and Reporting
Details error detection and reporting for TRM Level 1.
TRM Level 1 Error Status Register
Describes the TD field of the TRM Level 1 Error Status Register.
TRM Level 2 Error Status Registers
Details the two level 2 status registers provided by the TRM.
Chapter 7. Channel Adapter (CA)
The CA in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the CA data flow for specific 3745 models.
The CA in 3745 Model 17A Data Flow
Diagram illustrating the CA data flow for the 3745 Model 17A.
Introduction
Introduces the microcoded CA, its attachment, and capabilities.
Buffer Chaining Channel Adapter (BCCA)
Describes the BCCA, a new channel adapter improving performance.
Packaging
Details the packaging of CADS or BCCA on a channel adapter logic card.
Supported Features
Lists features supported by CADS and BCCA.
Non-Supported Features
Lists features not supported by CADS and BCCA.
Configuration
Explains CA configuration availability via IOC BUS.
CA Operating Environment
Describes how the CA operates with control programs and interfaces.
Modes of Operation
Details the NSC and ESC modes of operation for the CA.
Host Unit Control Word (UCW)/Host I/O Configuration Data Set (IOCDS)
Explains UCW/IOCDS requirements for the controller.
Overall Operation
Describes how the CA connects to the 370 channel and IOC bus.
Data Transfer Methods (PIO and AIO)
Explains the two methods used for data transfer between CA and CCU.
CA Instructions
Details the instructions used to control the CA.
CA States
Describes the possible states of the CA: Ready, Initial Selection, Data Transfer, Disabled.
CA Interrupt Requests
Explains the interrupt requests the CA can raise to the CCU and MOSS.
Accessing CA Registers
Describes how CA registers are accessed by the control program or MOSS.
Channel Interface Tag Signals Used by the CA
Lists the channel interface tag signals used by the CA.
Autoselection
Explains how to work with a CA through autoselection.
Autoselection Mechanism
Details the autoselection mechanism.
Autoselection (AS) Chain
Describes the AS chain for CA installation.
Autoselection Error
Explains errors detected on the 'sample' chain during autoselection.
Cycle Steal
Describes cycle steal operations and information known to the IOC.
Cycle Steal (CS) Chain
Explains the CS chain depending on CA installation order.
Removing a CA from the Cycle Steal Chain
Details how to remove a CA from the cycle steal chain safely.
Chapter 4. Transmission Subsystem (TSS)
The TSS in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the TSS data flow for specific 3745 models.
The TSS in 3745 Model 17A Data Flow
Diagram illustrating the TSS data flow for the 3745 Model 17A.
Definitions
Defines low-speed scanners (LSSs) associated with LIC boards.
Low-Speed Scanner (LSS)
Details the LSS, consisting of CSP and FESL.
Communication Scanner Processor (CSP)
Describes the CSP, its functions, and components.
Front-End Scanner Low-Speed (FESL)
Explains the FESL's role in connecting CSP and LIC units.
LIC Board
Describes the LIC board, consisting of multiplexer and interface coupler cards.
Multiplexer Card (MUX)
Details Multiplexer Cards (MUXs), including DMUX functions.
Single Multiplexer Card (SMUX)
Describes SMUXA/B cards and their functions.
Line Interface Coupler (LIC)
Explains the LIC's function and its attachment to FDX/HDX lines.
LIC Types 1 to 4 Characteristics
Details characteristics of LIC types 1 to 4.
LIC Types 5/6 Characteristics
Details characteristics of LIC types 5 and 6.
Line Weights
Explains line weights and their calculation for scanner occupation.
Chapter 5. High Performance Transmission Subsystem (HPTSS)
The HPTSS in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the HPTSS data flow for specific 3745 models.
The HPTSS in 3745 Model 17A Data Flow
Diagram illustrating the HPTSS data flow for the 3745 Model 17A.
Introduction
Introduces the HPTSS, its capabilities, and system environment.
System Environment
Describes the system environment for HPTSS, including network standards.
ELA Packaging
Details the ELA packaging, consisting of CSP and EAC cards.
Line Addressing
Explains line addressing for HSS and the TD1 field of the IOH.
HSS Commands
Lists NCP commands supported by the HSS.
Interface Types
Describes the two types of line interface available at the FESH card exit.
HPTSS Data Flow
Diagram illustrating the HPTSS data flow.
CSP Microcode Summary
Lists the main microcode functions supported by the HSS.
Internal Interconnections
Explains how each HSS interconnects with CSS and MOSS.
CSP-to-IOC Bus
Details the CSP-to-IOC bus connection and its uses.
NCP-HSS Microcode
Explains how CCU exchanges data with HSS CSP.
CLDP-HSS Microcode
Describes the controller load/dump program used for remote 3745 interconnection.
FESH to CSP
Explains the physical interconnection between FESH and CSP.
Microcode to FESH
Describes how microcode is loaded from CSP into FESH RAM.
Data Transmission
Explains data transmission commands issued by CSP microcode to FESH.
Chapter 6. The Token-Ring Subsystem
The TRSS in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the TRSS data flow for specific 3745 models.
The TRSS in 3745 Model 17A Data Flow
Diagram illustrating the TRSS data flow for the 3745 Model 17A.
Token-Ring Network
Describes token-ring networks and their design approach.
IBM Token-Ring Network
Explains IBM Token-Ring as an information transport system.
Cabling System (Ring)
Details the transmission media used for token-ring networks.
Token-Ring Adapter
Describes the functions of the token-ring adapter in the 3745.
The Token-Ring Adapter in the 3745
Introduces the token-ring adapter (TRA) and its components.
Introduction
Introduces the token-ring subsystem (TRSS) and its protocol.
Packaging
Details the packaging of the token-ring adapter (TRA).
Token-Ring Interface Coupler (TIC) Card
Describes the TIC card and its functional areas.
TIC Data Flow
Explains the data flow through the TIC card on the ring.
The Front End
Describes the front end as the interface to the ring transmission line.
The Protocol Handler
Explains the protocol handler's role as a logical interconnection.
The Message Processor
Describes the message processor as the master control element.
TIC Bus Interconnection Control
Explains the mechanism for data transfer between TIC storage and CCU storage.
Receive Operation
Describes the receive operation for data from the ring.
Transmit Operation
Explains the transmit operation, reversing the receive flow.
Token-Ring Multiplexor (TRM) Card
Describes the TRM card functions and its interconnections.
IOC Bus Interconnection
Explains the IOC bus interconnection for communication.
Summary of the IOC Bus Interface Signal Lines
Lists and describes the IOC bus interface signal lines.
TIC Bus Interconnection
Explains the TIC bus interconnection.
Summary of the TIC Bus Signal Lines
Lists and describes the TIC bus signal lines.
TRM Arbitration Mechanism
Explains the arbitration logic for TRM, involving scan wheels.
TRA Resets
Details the three functions implemented to reset the TRA.
Power ON Reset and Tag Reset
Explains how Power ON reset and Tag reset are activated.
Programmed Reset
Describes how the program initiates a programmed reset.
TIC Reset
Explains how the program performs a selective reset of the TIC.
Diagnostic Section TA0A
Provides diagnostic procedures for TRM disconnection.
Error Detection and Reporting
Details error detection and reporting for TRM Level 1.
TRM Level 1 Error Status Register
Describes the TD field of the TRM Level 1 Error Status Register.
TRM Level 2 Error Status Registers
Details the two level 2 status registers provided by the TRM.
Chapter 7. Channel Adapter (CA)
The CA in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the CA data flow for specific 3745 models.
The CA in 3745 Model 17A Data Flow
Diagram illustrating the CA data flow for the 3745 Model 17A.
Introduction
Introduces the microcoded CA, its attachment, and capabilities.
Buffer Chaining Channel Adapter (BCCA)
Describes the BCCA, a new channel adapter improving performance.
Packaging
Details the packaging of CADS or BCCA on a channel adapter logic card.
Supported Features
Lists features supported by CADS and BCCA.
Non-Supported Features
Lists features not supported by CADS and BCCA.
Configuration
Explains CA configuration availability via IOC BUS.
CA Operating Environment
Describes how the CA operates with control programs and interfaces.
Modes of Operation
Details the NSC and ESC modes of operation for the CA.
Host Unit Control Word (UCW)/Host I/O Configuration Data Set (IOCDS)
Explains UCW/IOCDS requirements for the controller.
Overall Operation
Describes how the CA connects to the 370 channel and IOC bus.
Data Transfer Methods (PIO and AIO)
Explains the two methods used for data transfer between CA and CCU.
CA Instructions
Details the instructions used to control the CA.
CA States
Describes the possible states of the CA: Ready, Initial Selection, Data Transfer, Disabled.
CA Interrupt Requests
Explains the interrupt requests the CA can raise to the CCU and MOSS.
Accessing CA Registers
Describes how CA registers are accessed by the control program or MOSS.
Channel Interface Tag Signals Used by the CA
Lists the channel interface tag signals used by the CA.
Autoselection
Explains how to work with a CA through autoselection.
Autoselection Mechanism
Details the autoselection mechanism.
Autoselection (AS) Chain
Describes the AS chain for CA installation.
Autoselection Error
Explains errors detected on the 'sample' chain during autoselection.
Cycle Steal
Describes cycle steal operations and information known to the IOC.
Cycle Steal (CS) Chain
Explains the CS chain depending on CA installation order.
Removing a CA from the Cycle Steal Chain
Details how to remove a CA from the cycle steal chain safely.
Chapter 8. Maintenance and Operator Subsystem (MOSS)
The MOSS in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the MOSS data flow for specific 3745 models.
The MOSS in 3745 Model 17A Data Flow
Diagram illustrating the MOSS data flow for the 3745 Model 17A.
Introduction
Introduces MOSS, its functions, and components.
MOSS Processor
Describes the MOSS processor and its activities.
Packaging
Details the MOSS board components.
MOSS Reset
Explains the MOSS reset process, including POR flowchart.
MOSS Functions
Lists the functions provided by MOSS for maintaining the 3745.
MOSS States
Describes the possible states of a scanner as viewed by NCP/PEP or MOSS.
MOSS Changes of State
Explains the events and actions causing MOSS state changes.
Branch Trace
Describes the branch trace facility for recording non-sequential operations.
Branch Trace Buffer
Explains the branch trace buffer allocation and storage.
Conditional Branch Trace
Describes how to start and stop a branch trace without MOSS intervention.
Mailbox Description
Explains mailbox areas used for NCP/PEP and MOSS communication.
Exchange Time Outs
Describes the requester filling mailbox and posting an interrupt.
CCU to MOSS Communication (Out Mailbox)
Explains passing requests from NCP/PEP to MOSS and MOSS posting status response.
MOSS-to-CCU Communication (In Mailbox)
Explains passing MOSS requests to NCP/PEP and NCP/PEP posting status response.
Mailbox Commands
Lists commands sent by MOSS to CCU control program (IN mailboxes).
Request Unit List
Defines request units sent by SSCP and processed by MOSS.
Chapter 9. Control Panel, Operator Consoles, Disk/Diskette Drives
Control Panel
Provides an overview of the control panel functions and components.
Operator Consoles for Models 1x0
Highlights the three console interfaces used by customers and service personnel.
Console Sharing Via IBM 7427
Explains how the IBM 7427 Console Switching Unit can be used.
Remote Support Facility (RSF)
Describes the RSF attachment via modem and its operating characteristics.
Consoles Tail Gate on Models 1X0
Details console tail gate connectors for Models 1X0.
For 3745 Model 17A
Provides information on J1 connector for service processor connection via LAN.
Customer Power Control
Describes the customer power control connector and its function.
Hard Disk Drive (HDD)
Details the characteristics of the 3745 hard disk drive.
Flexible Disk Drive (FDD)
Describes the characteristics of the 3745 diskette drive.
Chapter 10. Power System
Power System in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the power system data flow for specific 3745 models.
The Power System in 3745 Model 17A Data Flow
Diagram illustrating the power system data flow for the 3745 Model 17A.
Introduction
Details the components of the power system.
AC Voltages Input
Describes the power subsystem's AC voltage input characteristics.
AC Voltages Limits
Specifies the AC voltage limits for the 3745.
Frequency
Lists the operating frequencies for the 3745.
Safety Statement
Provides safety statements for input/output cables.
Primary Power Box
Details the primary power box component locations.
Power Supply 1 (PS1)
Describes Power Supply 1 (PS1) and its connection layout.
Power Supply 2 (PS2)
Describes Power Supply 2 (PS2) and its connection layout.
Disk and Diskette Drive ON/OFF Control
Explains the ON/OFF control for disk drives via MOSS or manually.
Power Control Subsystem
Details the functions of the power control subsystem.
Power Control Data Flow
Diagram illustrating the power control data flow.
Power Control
Describes the power control card (PCC) and control panel.
Power Mode of Operation
Explains the different power modes: Local, Host, and Network.
Switching From One Mode to Another
Describes how to switch between power modes (host, network, local).
Power ON/OFF Sequence
Details the normal power ON and OFF sequences.
Scheduled Power ON Function
Explains the function of the clock for scheduled power ON actions.
Automatic Restart Function
Describes the automatic restart function available in host and network modes.
Power ON Retry Function
Explains the automatic repower function after a power OFF.
Power Status Monitoring
Describes how power status is cyclically scanned to determine faults.
Individual Reset Function
Allows MOSS to perform selective resets for diagnostic purposes.
Chapter 11. Error Logging
Introduction
Introduces hexadecimal codes and Box Event Records (BERs).
Hexadecimal Codes
Explains the hexadecimal codes displayed on the operator's panel.
Box Event Records (BERs)
Describes the event logging procedure of MOSS reporting errors.
BER Formatting
Explains how MOSS identifies and formats BERs.
Automatic BER Analysis
Describes the automatic BER analysis process.
General Process Flow
Details the automatic BER analysis functions.
CE Field Updating
Explains the 40-byte field available to CE for personal notes.
BER Reference Code
Explains reference codes for intermittent failures.
Manual FRU Correlation
Describes correlation of FRUs based on BER reference codes.
Automatic FRU Correlation
Explains the automatic FRU correlation process.
Reference Codes
Provides structure for reference codes related to hardware and software problems.
Chapter 12. Ethernet Subsystem (ESS)
The ESS in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the ESS data flow for specific 3745 models.
The ESS in 3745 Model 17A Data Flow
Diagram illustrating the ESS data flow for the 3745 Model 17A.
Introduction
Introduces the Ethernet LAN subsystem (ESS) and its capabilities.
System Environment
Describes the system environment for the ELA.
ELA Packaging
Details the ELA packaging, consisting of CSP and EAC cards.
Line Addressing
Explains line addressing for ELAs.
ELA Commands
Lists NCP commands supported by the ELA.
Interface or Port Types
Describes the two types of line interfaces supported by ELA.
ESS Data Flow
Diagram illustrating the ESS data flow.
Frame Types Supported
Lists the two types of frames supported by the ESS.
Ethernet Version 2
Details the Ethernet Version 2 frame format.
IEEE 802.3 Frame
Details the IEEE 802.3 frame format.
ELA Microcode Description
Describes the ELA microcode functions and structure.
ELA Microcode Functions
Lists the functions provided by the ELA RAM Microcode.
ELA Microcode Structure
Details the structure of the ELA microcode.
Internal Interconnections
Explains the interconnections between ELA components.
CSP-to-IOC Bus
Details the CSP-to-IOC bus connection for ELA.
NCP-ELA Microcode
Explains how CCU exchanges data with ELA CSP.
EAC to CSP
Explains the physical interconnection between EAC and CSP.
Microcode to EAC
Describes how microcode is loaded from CSP into EAC RAM.
EAC to DMA Bus
Explains the EAC to DMA bus connection.
Communication Scanner Processor (CSP)
Describes the CSP hardware's identity to LSS CSP.
CSP Layer
Details the CSP layer's interconnections and functions.
DMA Manager Layer
Describes the DMA manager layer's interconnections and functions.
Address PROM Layer
Details the address PROM contents for ELA.
Bus Interconnection Layer
Explains the bus interconnection layer's functions.
EAC Command Description
Lists commands received by CSP and their termination.
Set Mode
Explains how to select and personalize the line using Set Mode.
CSP Processing
Details the CSP processing steps for Enable command.
Enable
Explains the Enable command used to prepare the line for data transfer.
Disable
Describes the Disable command used to stop EAC.
Change
Explains how to update contiguous bytes of Set Mode data.
Transmit Data
Explains the Transmit Data command for Ethernet V2 and IEEE 802.3 frames.
Chapter 11. Error Logging
Introduction
Introduces hexadecimal codes and Box Event Records (BERs).
Hexadecimal Codes
Explains the hexadecimal codes displayed on the operator's panel.
Box Event Records (BERs)
Describes the event logging procedure of MOSS reporting errors.
BER Formatting
Explains how MOSS identifies and formats BERs.
Automatic BER Analysis
Describes the automatic BER analysis process.
General Process Flow
Details the automatic BER analysis functions.
CE Field Updating
Explains the 40-byte field available to CE for personal notes.
BER Reference Code
Explains reference codes for intermittent failures.
Manual FRU Correlation
Describes correlation of FRUs based on BER reference codes.
Automatic FRU Correlation
Explains the automatic FRU correlation process.
Reference Codes
Provides structure for reference codes related to hardware and software problems.
Chapter 12. Ethernet Subsystem (ESS)
The ESS in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the ESS data flow for specific 3745 models.
The ESS in 3745 Model 17A Data Flow
Diagram illustrating the ESS data flow for the 3745 Model 17A.
Introduction
Introduces the Ethernet LAN subsystem (ESS) and its capabilities.
System Environment
Describes the system environment for the ELA.
ELA Packaging
Details the ELA packaging, consisting of CSP and EAC cards.
Line Addressing
Explains line addressing for ELAs.
ELA Commands
Lists NCP commands supported by the ELA.
Interface or Port Types
Describes the two types of line interfaces supported by ELA.
ESS Data Flow
Diagram illustrating the ESS data flow.
Frame Types Supported
Lists the two types of frames supported by the ESS.
Ethernet Version 2
Details the Ethernet Version 2 frame format.
IEEE 802.3 Frame
Details the IEEE 802.3 frame format.
ELA Microcode Description
Describes the ELA microcode functions and structure.
ELA Microcode Functions
Lists the functions provided by the ELA RAM Microcode.
ELA Microcode Structure
Details the structure of the ELA microcode.
Internal Interconnections
Explains the interconnections between ELA components.
CSP-to-IOC Bus
Details the CSP-to-IOC bus connection for ELA.
NCP-ELA Microcode
Explains how CCU exchanges data with ELA CSP.
EAC to CSP
Explains the physical interconnection between EAC and CSP.
Microcode to EAC
Describes how microcode is loaded from CSP into EAC RAM.
EAC to DMA Bus
Explains the EAC to DMA bus connection.
Communication Scanner Processor (CSP)
Describes the CSP hardware's identity to LSS CSP.
CSP Layer
Details the CSP layer's interconnections and functions.
DMA Manager Layer
Describes the DMA manager layer's interconnections and functions.
Address PROM Layer
Details the address PROM contents for ELA.
Bus Interconnection Layer
Explains the bus interconnection layer's functions.
EAC Command Description
Lists commands received by CSP and their termination.
Set Mode
Explains how to select and personalize the line using Set Mode.
CSP Processing
Details the CSP processing steps for Enable command.
Enable
Explains the Enable command used to prepare the line for data transfer.
Disable
Describes the Disable command used to stop EAC.
Change
Explains how to update contiguous bytes of Set Mode data.
Transmit Data
Explains the Transmit Data command for Ethernet V2 and IEEE 802.3 frames.
Chapter 11. Error Logging
Introduction
Introduces hexadecimal codes and Box Event Records (BERs).
Hexadecimal Codes
Explains the hexadecimal codes displayed on the operator's panel.
Box Event Records (BERs)
Describes the event logging procedure of MOSS reporting errors.
BER Formatting
Explains how MOSS identifies and formats BERs.
Automatic BER Analysis
Describes the automatic BER analysis process.
General Process Flow
Details the automatic BER analysis functions.
CE Field Updating
Explains the 40-byte field available to CE for personal notes.
BER Reference Code
Explains reference codes for intermittent failures.
Manual FRU Correlation
Describes correlation of FRUs based on BER reference codes.
Automatic FRU Correlation
Explains the automatic FRU correlation process.
Reference Codes
Provides structure for reference codes related to hardware and software problems.
Chapter 12. Ethernet Subsystem (ESS)
The ESS in 3745 Models 130, 150, 160, and 170 Data Flow
Diagram illustrating the ESS data flow for specific 3745 models.
The ESS in 3745 Model 17A Data Flow
Diagram illustrating the ESS data flow for the 3745 Model 17A.
Introduction
Introduces the Ethernet LAN subsystem (ESS) and its capabilities.
System Environment
Describes the system environment for the ELA.
ELA Packaging
Details the ELA packaging, consisting of CSP and EAC cards.
Line Addressing
Explains line addressing for ELAs.
ELA Commands
Lists NCP commands supported by the ELA.
Interface or Port Types
Describes the two types of line interfaces supported by ELA.
ESS Data Flow
Diagram illustrating the ESS data flow.
Frame Types Supported
Lists the two types of frames supported by the ESS.
Ethernet Version 2
Details the Ethernet Version 2 frame format.
IEEE 802.3 Frame
Details the IEEE 802.3 frame format.
ELA Microcode Description
Describes the ELA microcode functions and structure.
ELA Microcode Functions
Lists the functions provided by the ELA RAM Microcode.
ELA Microcode Structure
Details the structure of the ELA microcode.
Internal Interconnections
Explains the interconnections between ELA components.
CSP-to-IOC Bus
Details the CSP-to-IOC bus connection for ELA.
NCP-ELA Microcode
Explains how CCU exchanges data with ELA CSP.
EAC to CSP
Explains the physical interconnection between EAC and CSP.
Microcode to EAC
Describes how microcode is loaded from CSP into EAC RAM.
EAC to DMA Bus
Explains the EAC to DMA bus connection.
Communication Scanner Processor (CSP)
Describes the CSP hardware's identity to LSS CSP.
CSP Layer
Details the CSP layer's interconnections and functions.
DMA Manager Layer
Describes the DMA manager layer's interconnections and functions.
Address PROM Layer
Details the address PROM contents for ELA.
Bus Interconnection Layer
Explains the bus interconnection layer's functions.
EAC Command Description
Lists commands received by CSP and their termination.
Set Mode
Explains how to select and personalize the line using Set Mode.
CSP Processing
Details the CSP processing steps for Enable command.
Enable
Explains the Enable command used to prepare the line for data transfer.
Disable
Describes the Disable command used to stop EAC.
Change
Explains how to update contiguous bytes of Set Mode data.
Transmit Data
Explains the Transmit Data command for Ethernet V2 and IEEE 802.3 frames.
Chapter 11. Error Logging
Introduction
Introduces hexadecimal codes and Box Event Records (BERs).
Hexadecimal Codes
Explains the hexadecimal codes displayed on the operator's panel.
Box Event Records (BERs)
Describes the event logging procedure of MOSS reporting errors.
BER Formatting
Explains how MOSS identifies and formats BERs.
Automatic BER Analysis
Describes the automatic BER analysis process.
General Process Flow
Details the automatic BER analysis functions.
CE Field Updating
Explains the 40-byte field available to CE for personal notes.
BER Reference Code
Explains reference codes for intermittent failures.
Manual FRU Correlation
Describes correlation of FRUs based on BER reference codes.
Automatic FRU Correlation
Explains the automatic FRU correlation process.
Reference Codes
Provides structure for reference codes related to hardware and software problems.
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