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MEDIATEK MT6765 Manuallines

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CONFIDENTIAL B
MT6765 PCB Design
Guidelines V0_1
2017/11/24

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Summary of Contents for MEDIATEK MT6765

  • Page 1 CONFIDENTIAL B MT6765 PCB Design Guidelines V0_1 2017/11/24...

  • Page 2: Revision History

    Revision History Version Date Description Editors Mavis Wang, Ivy Hsiao, V0_1 2017/11/24 First release Wanda Tseng, Zuoru Yi, YH Ku , PH Chang , PS Chen, FK Pan, Charles Chen CONFIDENTIAL B...
  • Page 3 Design Guidelines for High-speed Digital Signals • LPDDR4X/LPDDR3 • PDN design  Others • MT6765 RF interface - MT6177 (RF transceiver) • MT6765 RF interface - MT6177M (RF transceiver) • MT6357 (PMU) • MT6631 (BT/FM/Wi-Fi/GPS) • MT6371 (battery charger/USB_PD) • eMMC/USB/MIPI/SIM card/T-card...
  • Page 4 Design Guidelines for High-speed Digital Signals • LPDDR4X/LPDDR3 • PDN design  Others • MT6765 RF interface - MT6177 (RF transceiver) • MT6765 RF interface - MT6177M (RF transceiver) • MT6357 (PMU) • MT6631 (BT/FM/Wi-Fi/GPS) • MT6371 (battery charger/USB_PD) • eMMC/USB/MIPI/SIM card/T-card...
  • Page 5 Package Outline of MT6765 CONFIDENTIAL B...
  • Page 6 MT6765 Footprint Recommendation Note: • copper defined for all solder pads (see Figure 1). • Recommended stencil opening  0.24mm square with 0.075R angle (see green area in Figure 2) • Use 0.1/0.22mm (drill/land) laser via on PAD to improve the yield of SMT.
  • Page 7 MT6765 Ball Out Design eMMC DRAM I/F MT6631 I/F DVDD_EMI PMIC I/F DVDD_TOP MIPI CSI DVDD_MFGSYS MIPI DSI DVDD_MDSYS DVDD_VDD_ EINT MODEM DVDD_MCUSYS MSDC1 RF BPI RF IQ BPI BSI CONFIDENTIAL B...
  • Page 8 Design Guidelines for High-speed Digital Signals • LPDDR4X/LPDDR3 • PDN design  Others • MT6765 RF interface - MT6177 (RF transceiver) • MT6765 RF interface - MT6177M (RF transceiver) • MT6357 (PMU) • MT6631 (BT/FM/Wi-Fi/GPS) • MT6371 (battery charger/USB_PD) • eMMC/USB/MIPI/SIM card/T-card...
  • Page 9 PCB Stack-up Recommendation ▪ To keep the best power integrity, select PCB with thinner thickness, ≤ 0.8mm. ▪ Follow the relative stack-up arrangement listed on the following pages for LPDDR4X and power distribution network. ▪ Others signals can be routed in the rest of the area. ▪...
  • Page 10 PCB Stack-up: 8-layer HDI2 Layer definition HDI-2 (2-6-2) Signal/Power/Ground Layers Stack-up (S/P/G) Theoretic Theoretic Material LPDDR3 LPDDR4X Power thickness (um) thickness (mil) 0.79 3.4~3.6 0.98 Copper 2.36 Prepreg 3.4~3.6 0.75 Copper 2.36 Prepreg 3.2~3.4 0.87 Copper 2.95 Prepreg 3.2~3.4 0.59 Copper 12.0 Core...

  • Page 11: Placement Notes

    Placement Notes Main Audio Camera Camera Jack BT/FM/ LB/MB WiFi/GPS MT6631 DRX ANT WIFI/BT/ GPS ANT RF IC (MT6177) (MT6177M) eMCP 6765 LPDDR4X DRX ANT BATT PMIC DEBUG Conn (MT6357) card Conn Bottom side side card card Audio Conn CONFIDENTIAL B...
  • Page 12 Design Guidelines for High-speed Digital Signals • LPDDR4X/LPDDR3 • PDN design  Others • MT6765 RF interface - MT6177 (RF transceiver) • MT6765 RF interface - MT6177M (RF transceiver) • MT6357 (PMU) • MT6631 (BT/FM/Wi-Fi/GPS) • MT6371 (battery charger/USB_PD) • eMMC/USB/MIPI/SIM card/T-card...
  • Page 13 PCB Module Design ▪ We recommend you adopt modules by MediaTek as the first priority. As the design trend turns to developing light, thin and higher battery capacity on smart phones, the complexity on system design becomes a great challenge nowadays. It is a time and cost consuming process to meet the layout constraints and at the same time deliver a good signal and power integrity.
  • Page 14 Enabling your High-speed Digital Design~ (Signal Integrity Express): SI/PI simulation support CONFIDENTIAL B...
  • Page 15 LPDDR4X - Placement ▪ Please keep the spacing between MT6765 and DRAM as small as possible. ▪ Recommend the spacing is less than 0.5mm. Breakout DRAM 0.5mm MT6765 VDD1 VDDQ VDD2 CONFIDENTIAL B...
  • Page 16 PCB Design Guidelines for LPDDR4X (I) Grouping Signal Name Description EMI[0:1]_DQ[0:15] Data bus EMI[0:1]_DMI[0:1] Data mask EMI[0:1]_CA[0:5] Command/Address EMI[0:1]_CKE[0:1], EMI[0:1]_CS[0:1], Clock enable, Chip EMI_RESET_N select, Reset EMI[0:1]_DQS[0:1]_T, Data strobe EMI[0:1]_DQS[0:1]_C EMI[0:1]_CK_T, EMI[0:1]_CK_C Clock  Please remove test point if not necessary ...
  • Page 17 PCB Design Guidelines for LPDDR4X (II)  Keep solid L2&L4 reference plane (GND) • For DQ/CA at L1, refer to ground beneath • For DQ/CA/CLK/DQS at L3, refer to ground plane both above and below  Signals layout topology should be routed at L1 and L3 as illustrated below •...
  • Page 18 DRAM Device PDN guide line  2-sided SMT:  Make VDD2 PWR connection at L1 and place capacitor at each side • Get the power trace as wide as possible (60 mil is suggested)  Place capacitors beneath each region for VDD1, VDD2, and VDDQ ...
  • Page 19 LPDDR3 - Placement ▪ Please keep the spacing between MT6765 and DRAM as small as possible. ▪ Recommend the spacing is less than 0.5mm. Breakout DRAM 0.5mm MT6765 AVDD_EMI CONFIDENTIAL B...
  • Page 20 PCB Design Guidelines for LPDDR3 (I) Grouping Signal Name Description EMI0_DQ[0:31] Data bus EMI0_DMI[0:3] Data mask EMI0_CA[0:9] Command/Address Clock enable, Chip EMI0_CKE[0:1], EMI0_CS[0:1], select, Reset EMI0_DQS[0:3]_T, EMI0_DQS[0:3]_C Data strobe EMI0_CK_T, EMI0_CK_C Clock VREF_EMI Reference voltage  Please remove test point if not necessary ...
  • Page 21 PCB Design Guidelines for LPDDR3 (II)  Keep solid L2&L4 reference plane (GND) • For DQ/CA at L1, refer to ground beneath • For DQ/CA/CLK/DQS at L3, refer to ground/power plane both above and below  Signals layout topology should be routed at L1 and L3 as illustrated below •...
  • Page 22 Design Guidelines for High-Speed Digital Signals • LPDDR4X/LPDDR3 • PDN design  Others • MT6765 RF interface - MT6177 (RF transceiver) • MT6765 RF interface - MT6177M (RF transceiver) • MT6357 (PMU) • MT6631 (BT/FM/Wi-Fi/GPS) • MT6371 ( Battery Charger /USB_PD) •...
  • Page 23 Basic Concepts of Power Delivery Network ▪ With the increasing demand of switching current and power consumption, the conventional PCB design concept is no longer sufficient in dealing with high-performance smart phone. Thus, a well- designed PDN (Power Delivery Network) on PCB is greatly significant for system stability and performance.
  • Page 24 Ball List Table Signal Name Ball Description VPROC U16, Y16, AA16, AB16, U18, Y18, AA18, AB18, U20, Y20, Provides application processor CPU power AA20, Y21, AA21, U22, Y22, AA22 (DVDD_DVFS) L19, N19, K20, L20, M20, N20, P20, T20, T21 Provides application processor GPU power. VGPU (DVDD_GPU) VCORE...
  • Page 25 Decoupling Caps Placement Suggestions To maintain power integrity, place decoupling capacitors beneath power balls. VEMI_VDD2 VSRAM_CORE VEMI_VDDQ (SoC) VCORE VSRAM_GPU VSRAM_CORE (MODEM) VSRAM_PROC VPROC VMODEM CONFIDENTIAL B...
  • Page 26 Guidelines for Remote Sensing R_Remote Buck 0Ω network resistor converter PWR_FB/GND_FB Feedback network (remote sensing) To compensate voltage loss, each two feedback paths (PWR_FB and GND_FB) are connected from every critical power domain which is close to MT6177 to the buck converter (PMIC).
  • Page 27 Guidelines for Power Domain Bottom Cap 0201 , 0402 3-terminal decoupling caps group cap VPROC, VGPU, VCORE, PMIC 0402 , 0603 decoupling caps Network VMODEM, VSRAM_PROC, VSRAM_CORE, VEMI_VDD2 , VEMI_VDDQ critical path The whole PDN is from PMIC output pin, through (the LC low-pass filter) & decoupling caps to AP. PDN is the source of all switching currents. “Critical-Path”...
  • Page 28 Mounting Inductance Double-sided SMT example (recommended) The bigger/longer the loop, the higher the inductance (starting from PWR pad back to *Additional routing GND pad). connection between laser and PTH vias Best: Lowest mounting inductance Moderate Single-sided SMT example Bad PWR/GND plane coupling and largest current loop *PWR/GND route at adjacent and upper layers...
  • Page 29 Via Interconnection Minimize the distance Good: Lowest mounting inductance Bad: Excessive routing to increase inductance Decoupling cap Laser via PTH via  Design suggestions for via interconnection Via interconnect is critical in delivering current between each layer and is usually the bottleneck in the entire PDN networking.
  • Page 30 Design Guidelines for High-speed Digital Signals • LPDDR4X/LPDDR3 • PDN design  Others • MT6765 RF interface - MT6177 (RF transceiver) • MT6765 RF interface - MT6177M (RF transceiver) • MT6631 (BT/FM/Wi-Fi/GPS) • MT6371 (battery charger/USB_PD) • eMMC/USB/MIPI/SIM card/T-card CONFIDENTIAL B...
  • Page 31 MT6177 PCB Layout Guideline CONFIDENTIAL B...
  • Page 32 Package of MT6177 Outline CONFIDENTIAL B...
  • Page 33 MT6177 Ball Map RFPRX RFDRX 26MHz Output RF TX LTE BSI PRXIQ LTE TXIQ DRXIQ CONFIDENTIAL B...
  • Page 34 MT6177 Placement (1/3)  RF supports PRX (Primary RX) and DRX (Diversity RX). MT6177 has two receiver circuits.  DRX matching components should be placed near MT6177. MT6177 DRX IC ball number IC ball name PCB net name DRX1 RF_B12B17_DRX_RFIC MT6177 DRX2 RF_B8_DRX_RFIC...
  • Page 35 MT6177 Placement (2/3)  PRX matching components should be placed near MT6177. PRX matching MT6177 PRX close to MT6177 IC ball number IC ball name PCB net name PRX1 RF_B12B17_PRX_RFIC PRX2 RF_B8_PRX_RFIC PRX3 RF_B20_PRX_RFIC PRX4 RF_B5B26B27_PRX_RFIC PRX5 RF_B28_PRX_RFIC PRX6 RF_B34B39_PRX_RFIC PRX7 RF_B3_PRX_RFIC PRX8...
  • Page 36 MT6177 Placement (3/3)  MT6177 and PA IC should have their own shielding case to prevent de-sense issues. Top side Bottom side Shielding Case Shielding Case Shielding Case Shielding Case MT6177 Shielding Case Shielding Case Shielding Case CONFIDENTIAL B...
  • Page 37 MT6177 TX/RX Signals  Impedance control is necessary for all RF signals. Impedance 50Ω  Make sure that the routing impedance is single-ended 50Ω for TX/PDET/RX. MT6177 Impedance CONFIDENTIAL B 50Ω...
  • Page 38 MT6177 IQ Signals (1/3) a. All GND ball adjacent RXIQ must be well connected @ L1. (Fig-1) b. The RXIQ signal must have GND via close to its layer transition. (Fig-1) c. All RXIQ signals should have GND shielding by group (adjacent up/down layers). (Fig-2) d.
  • Page 39 MT6177 IQ Signals (2/3) Layout not recommended Layout recommended Figure 1 shows the ABB IQ are routed Figure 2 shows the ABB IQ are routed away beneath the PMIC power nets even with from PMIC power nets to avoid de-sense issue. ground plane shielding;...
  • Page 40 MT6177 IQ Signals (3/3) Layout not recommended Layout recommended Figure 1 shows the PMIC power nets via are Figure 2 shows PMIC power nets via are away routed in the ABB IQ region in the PCB inner from ABB IQ region at least 25mil to avoid de- layer even with ground shielding;...
  • Page 41 MT6177 Duplexer ▪ Duplexer notice a. Enlarge L1 copper pouring range for duplexer GND pins (2, 4, 5, 7, 8). b. Avoid parallel routing between ANT/RX/TX signals. L2 GND plane c. Maintain good isolation between ANT/RX/TX by: (blue) 1. GND shielding between these three paths. 2.
  • Page 42 Others for MT6177 a. CLK signal should have GND shielding and avoid routing this net between BSI signals. (Fig-1) b. BSI signals should have GND shielding by group (adjacent up/down layers). (Fig-1) c. Must have ground via close to the RXIQ when layer change happens. (Fig-2) d.
  • Page 43 Design Guidelines for High-speed Digital Signals • LPDDR4X/LPDDR3 • PDN design  Others • MT6765 RF interface - MT6177 (RF transceiver) • MT6765 RF interface - MT6177M (RF transceiver) • MT6631 (BT/FM/Wi-Fi/GPS) • MT6371 (battery charger/USB_PD) • eMMC/USB/MIPI/SIM card/T-card CONFIDENTIAL B...
  • Page 44 MT6177M PCB Layout Guideline CONFIDENTIAL B...
  • Page 45 Package of MT6177M Outline CONFIDENTIAL B...
  • Page 46 MT6177M Ball Map CONFIDENTIAL B...
  • Page 47 MT6177M Placement (1/3)  RF supports PRX (Primary RX) and DRX (Diversity RX).  DRX matching components should be placed near MT6177M as the figure below. MT6177M DRX IC ball number IC ball name PCB net name DRX1 RF_B1_DRX_RFIC DRX2 RF_B2_DRX_RFIC MT6177M DRX3...
  • Page 48 MT6177M Placement (2/3)  PRX matching components should be placed near MT6177M. PRX matching MT6177M PRX close to MT6177M IC ball number IC ball name PCB net name PRX1 RF_B3_PRX_RFIC PRX2 RF_B1_PRX_RFIC PRX3 RF_B4_PRX_RFIC PRX4 RF_B40B41_PRX_RFIC PRX5 RF_B26_PRX_RFIC PRX6 RF_B7_PRX_RFIC PRX7 RF_B2_PRX_RFIC PRX8...
  • Page 49 MT6177M Placement (3/3)  MT6177M and PA IC should have their own shielding case to prevent de-sense issues. Top side Bottom side Shielding Case Shielding Case Shielding Case Shielding Case MT6177M MT6177M Shielding Case MT6177M on top Shielding Case Shielding Case CONFIDENTIAL B...
  • Page 50 MT6177M TX/RX Signals  Impedance control is necessary for all RF signals.  Make sure that the routing impedance is single-ended 50Ω for TX/PDET/RX. Impedance 50Ω Impedance 50Ω MT6177M CONFIDENTIAL B...
  • Page 51 MT6177M IQ Signals a. All GND ball adjacent RXIQ must be well connected @ L1. (Fig-1) b. The RXIQ signal must have GND via close to its layer transition. (Fig-1) c. All RXIQ signals should have GND shielding by group (adjacent up/down layers). (Fig-2) d.
  • Page 52 MT6177M Duplexer ▪ Duplexer notice a. Enlarge L1 copper pouring range for duplexer GND pins (2, 4, 5, 7, 8). b. Avoid parallel routing between ANT/RX/TX signals. L2 GND plane c. Maintain good isolation between ANT/RX/TX by: (blue) 1. GND shielding between these three paths 2.
  • Page 53 Others for MT6177M a. XO signal should have GND shielding and avoid routing this net between BSI signals. Routing them in different layer is better. (Fig-1) b. BSI signals should have GND shielding by group (adjacent up/down layers). (Fig-1) c. Must have ground via close to the RXIQ when layer change happens. (Fig-2) d.
  • Page 54 Design Guidelines for High-speed Digital Signals • LPDDR4X/LPDDR3 • PDN design  Others • MT6765 RF interface - MT6177 (RF transceiver) • MT6765 RF interface - MT6177M (RF transceiver) • MT6357 (PMU) • MT6631 (BT/FM/Wi-Fi/GPS) • MT6371 (battery charger/USB_PD) • eMMC/USB/MIPI/SIM card/T-card...
  • Page 55 MT6357 PCB Layout Guideline CONFIDENTIAL B...
  • Page 56 Package Outline of MT6357 CONFIDENTIAL B...
  • Page 57 MT6357 Ball Map CONFIDENTIAL B...
  • Page 58 MT6357 Power Input (1/2) VSYS Input Fig. 4  VSYS 22uF capacitor is placed near MT6357 VSYS input balls (Fig. 2). IC Ball Name IMAX(mA)  Routing from 22uF VSYS capacitor uses start topology to connect to each VSYS_VPROC 3031 3384 VSYS_VCORE 2520...
  • Page 59 MT6357 Power Input (2/2)  Layout method of MT6357 power Input for Buck GND Buck GND balls are connected to buck capacitors close to pin with plane or trace (Trace Width > 8mil * N (ball number) + M (ball pitch)).
  • Page 60 MT6357 Buck Output (1/2)  The buck inductors should be placed near MT6357. (Fig.1)  The output current is shown in Fig.2. Fig.1 Fig.2 Output ball Output name current (mA) VMODEM 2500 VPROC 4210 VCORE 3500 Top side 1900 MT6357 1750 CONFIDENTIAL B...
  • Page 61 MT6357 Buck Output (2/2)  Those signals are differential pairs and should be shielded by GND and far away from noise signals (Fig.1 ~ Fig.2). 1) VMODEM_FB/GND_VMODEM_FB 2) VPROC_FB/GND_VPROC_FB 3) VCORE_FB/GND_VCORE_FB 4) VPA_FB , VS1_FB Fig. 2 Fig. 1 CONFIDENTIAL B...
  • Page 62 MT6357 LDO Output (1/2) LDO output layout suggestion Ball name Width/Trace length (mA)  See Fig. 1 for the suggested LDO output layout. VFE28 6mil/2500mil VXO22 6mil/2500mil VCN28 6mil/2500mil VCAMA 8mil/3000mil VAUX18 6mil/2500mil VAUD28 6mil/2500mil VCN33 12mil/1000mil VLDO28 12mil/3000mil VIO28 8mil/3000mil 8mil/3000mil 20mil/1000mil...
  • Page 63 MT6357 LDO Output (2/2)  VREF capacitor should be placed near T13/T14 pin. Update C2153 to 100nF from 1uF  DVDD18_DIG capacitor should be placed near L10 pin. VREF capacitor close to MT6357 Close to MT6357 DIG power capacitor close to MT6357 CONFIDENTIAL B...
  • Page 64 Table 1 MT6357 Audio (1/3) Ball PCB net name IC ball name number  AU_VIN0_P AU_VIN0_P The signals in Table 1 should be routed as differential pairs and shielded and trace width ≧ AU_VIN0_N AU_VIN0_N by GND (adjacent and up/down layers) 4mil.
  • Page 65 MT6357 Audio (2/3) Power  Audio Negative Charge Pump (AUDNCP) related pins: AVDD18_AUD/AVSS18_AUD/AN_V18N/ FLYP/FLYN  All traces are wide and short. To minimize ESR and ESL, all traces are on TOP layer without any PCB via. Avoid using PCB VIA between the 5 traces (from ball to cap). (Fig.1 ~ Fig.2) ...
  • Page 66 MT6357 Audio (3/3) Audio/CLK IF Schematic and Layout Notice  The trace length of AUD_CLK_MOSI/AUD_DAT_MOSI0/AUD_DAT_MOSI1/AUD_SYNC_MOSI should be the same as much as possible.  The trace length of AUD_CLK_MISO/AUD_DAT_MISO0/AUD_DAT_MISO1/AUD_SYNC_MISO should be the same as much as possible.  AUD_CLK_MOSI/AUD_CLK_MISO should have GND shielded and the spacing should be >= 3mil. ...
  • Page 67 MT6357 AUXADC  Recommended AUXADC layout Route AVDD18_AUXADC, AUXADC_VIN, and AVSS18_AUXADC with 3mils width traces and well GND shielding Use AVSS18_AUXADC or GND for AVDD18_AUXADC and AUXADC_VIN shielding. AUXADC capacitor should be placed near AVDD18_AUXADC/AUXADC_VIN pin. Please connect the AVSS18_AUXADC to GND by a inner-layer short-pad (SH2201). SH2201 AUXADC_VIN Ball number...
  • Page 68 Example: AUXADC Trace Routing (Recommended) Routed AVDD18/VIN on the top layer and AVSS on the layer. AVDD18_AUXADC/AUXADC_VIN on the top and AUXADC_GND on 2 layer 4mil 3mil 3mil 4mil PMIC AVDD18/VIN AVSS18 Top View Top/Bottom layer layout Side View GND or AVSS18_AUXADC Top Layer layer 4mil...
  • Page 69 PMIC with Co-TMS Layout Recommendation CONFIDENTIAL B...
  • Page 70 MT6357 DCXO (1/2)  XTAL1 and XTAL2 connection to TMS pin 1 and pin 3 can be swapped. Keep out Buck, NCP, Class-D or other toggling signals 9mm away. (Fig.1)  Short DCXO gnds to main GND directly by the GND vias. (Fig.2) AVSS22_XO_ISO AVSS22_XO AVSS22_XOBUF...
  • Page 71 MT6357 DCXO (2/2) ▪ XTAL1/2 shielding case 1 • Route XTAL1/2 on the 1 layer, with well-grounding in the 1 and 2 layers. • Any other signals crossing or parallel XTAL1/2 are not allowed. ▪ XTAL1/2 shielding case 2 • Well shielding XTAL1/2 (2 layer) with GND •...
  • Page 72 Others for MT6357 Gauge  CS_N/CS_P (ball: R10/T107) should be routed as differential pairs and far away from noise signals. DCXO_32K MT6357 CS_P CS_N CONFIDENTIAL B...
  • Page 73 AP Analog and Power List Group#1 Group#2 Voltage PMIC Pin Name (AP analog pin name) (AP analog pin name) AVDD18_MD, AVDD18_USB, 1.8V VIO18 AVDD18_AP, AVDD18_PLLGP, AVDD18_WBG AVDD18_CPU AVDD12_MD, AVDD12_CSI, 1.2V VA12 AVDD12_DSI, AVDD12_PLLGP, AVDD12_USB, AVDD12_WBG 3.075V VUSB AVDD33_USB CONFIDENTIAL B...
  • Page 74 Trace End PMIC VIO18 ball 0.600A 20mil 200mil 0.3oz 17.7m 10.6mV 0.085A 20mil 800mil 0.3oz 71.0m 6.0mV AP AVDD18_USB ball 0.030A 12mil 300mil 0.3oz 44.3m 1.3mV Pass ≦18mV CONFIDENTIAL B Copyright © MediaTek Inc. All rights reserved. 11/23/2017 - 73 -...
  • Page 75 AP AVDD12_xxx Layout Constraint Group#1: AVDD12_MD,AVDD12_DSI,AVDD12_USB,AVDD12_UFS Group#2: AVDD12_CSI,AVDD12_PLLGP,AVDD12_WBG Group#1 AVDD12_xxx1 AVDD12_xxx2 AVDD12_xxx3 PMIC Group#2 AVDD12_xxx4 VA12 AVDD12_xxx5 AVDD12_xxx6 PCB drop voltage≦12mV (PMIC VA12 ball to AP AVDD12_xxx ball) for layout example Average PCB drop Trace Start Trace End current Width Length Thicknes Resister...
  • Page 76 AP AVDD33_USB Layout Constraint PCB drop voltage≦30mV (PMIC VUSB ball to AP AVDD33_USB ball) for layout example Average PCB drop current Widt Length Thickne Resister voltage Trace Start Trace End PMIC VUSB ball 0.05A 8mil 500mil 0.3oz 110.9m 5.5mV AP AVDD33_USB ball 0.05A 8mil 2000mil...
  • Page 77 Design Guidelines for High-speed Digital Signals • LPDDR4X/LPDDR3 • PDN design  Others • MT6765 RF interface - MT6177 (RF transceiver) • MT6765 RF interface - MT6177M (RF transceiver) • MT6357 (PMU) • MT6631 (BT/FM/Wi-Fi/GPS) • MT6371 (battery charger/USB_PD) • eMMC/USB/MIPI/SIM card/T-card...
  • Page 78 MT6631 PCB Layout Guideline CONFIDENTIAL B...
  • Page 79 Package Outline of MT6631 CONFIDENTIAL B...
  • Page 80 MT6631 Pin Definition WiFi/BT 3V3 GPS RF Pin 36: FM 2V8 GPS 1V8 & Pin 37: FM RF_N WiFi /BT RF pin 6631 Top Pin 38: FM_RF_P logic power Host reset WiFi ePA feedback voltage detect Top digital control WiFi/BT 1V8 41 DVSS Package type: QFN 40-lead Package size: 5 x 5mm...
  • Page 81 MT6631 vs. MT6765 Placement ▪ Keep the distance between MT6631 and MT6765 between 0.7cm~5cm.  If < 0.7cm: It may cause connectivity RF de-sense.  If > 5cm: IQ signals will be distorted (like EVM fail, Critical). MT6631 MT6765 CONFIDENTIAL B...
  • Page 82 MT6631 IQ Trace  IQ signals are differential pairs. Every pair should be shielded by GND (adjacent and up/down layers). If the layout area is not enough, shield by groups, for example:  WiFi group: WF_IP/IN/QP/QN Pin 17 ~ Pin 20 ...
  • Page 83 MT6631 Control Trace  High-speed connectivity WF 3-wire control line • Routed together and shielded by GND for left and right. • Do not couple with Power Line and IQ trace, and route in inner layer away from WiFi/GPS RF trace. Group Pin no.
  • Page 84 MT6631 26MHz CLK ▪ Connectivity 26MHz (pin 8: XO_IN) should be shielded by GND and routed far away from noise signals. ▪ 26MHz trace length should be less than 10cm. ▪ When adding VIA to change layer, keep VIA in every layer well grounded. ▪...
  • Page 85 MT6631 RF Trace: WiFi/BT/GPS  WB_RF_2G (pin 31), WB_RF_5G (pin 34) and GPS_RFIN (pin 39) are RF antenna pin for WiFi/BT/GPS. Keep 50Ω impedance with good shielding by GND. (Fig. 1)  Route on L1 and avoid layer transition for RF trace route (affect impedance control and PCB trace loss). (Fig. 1) ...
  • Page 86 MT6631 RF Trace: FM  FM_LANT_N (pin 37) and FM_LANT_P (pin 38) are FM signals and required for differential pairs to get better noise immunity.  FM signals must be shielded by GND (left/right /upper/lower) with stitching GND via.  If RF trace cannot be well protected, it will produce noise to FM easily.
  • Page 87 MT6631 Power Trace (1/2)  AVDD33_WBT: Place decupling capacitors close to power pin 33. (Fig. 1, 3)  AVDD28_FM: Place decupling capacitors close to power pin 36. (Fig. 1~2)  Keep away from other noisy power traces and high speed digital traces. AVDD28_FM decupling Fig.1 capacitor close to pin 36...
  • Page 88 MT6631 Power Trace (2/2)  AVDD18_WBT: Place decupling capacitors close to power pin 26,27. (Fig.1~2)  AVDD18_GPS: Place decupling capacitors close to power pin 40. (Fig.1、3)  Power traces VCN18_PMU should be used star routing topology to connect AVDD18_WBT (pin 26,27) and AVDD18_GPS (pin 40).
  • Page 89 Design Guidelines for High-speed Digital Signals • LPDDR4X/LPDDR3 • PDN design  Others • MT6765 RF interface - MT6177 (RF transceiver) • MT6765 RF interface - MT6177M (RF transceiver) • MT6357 (PMU) • MT6631 (BT/FM/Wi-Fi/GPS) • MT6371 (battery charger/USB_PD) • eMMC/USB/MIPI/SIM card/T-card...
  • Page 90 MT6371 PCB Layout Guideline CONFIDENTIAL B...
  • Page 91 Package Outline of MT6371 CONFIDENTIAL B...
  • Page 92 MT6371 Pin Definition CONFIDENTIAL B...
  • Page 93 MT6371 Schematic/Layout Notice ▪ High current path must enlarge trace width as 25mil/1A. • CHG_VIN, CHG_VLX, VSYS and VBAT  4A • CHG_VMID, FL_VMID  2.5A • FLED1/2  1.5A ▪ Bypass CAP/Resistor near to related ball. • VDDM, VDDA, BL_VDDA, DB_VDDA, CHG_BOOT to CHG_VLX, and CHG_ILIM.
  • Page 94 MT6371 - Charger CHG_VIN Trace High current path CHG_VIN, CHG_VLX, VSYS and VBAT  4A ▪ L1: CHG_VIN trace must be > 2.5mm L2: Via numbers should be > 8ea for L4: CHG_VIN trace must be > 2.5mm current path. CONFIDENTIAL B...
  • Page 95 MT6371 - Charger CHG_VMID & CHG_VLX CHG_VMID Output Cap CHG_VMID (=FL_VMID) trace must be > 1.5mm place as close to IC (<2mm) for parallel charger application CHG_VLX Inductor place as close as possible to IC (<2mm) CONFIDENTIAL B...
  • Page 96 MT6371 – VSYS & VBAT VSYS trace VSYS trace VSYS-Via should be > VSYS trace must be > 2.5mm must be > 2.5mm 8ea for current path. must be > 2.5mm VBAT-Via should be > VBAT trace VBAT trace 8ea for current path. must be >...
  • Page 97 MT6371 – FLED/Display/VDDM Inductor Output Output FLED1/FLED2 (Pin: Display Bias (Pin: K7) VDDM/VDA A6,A7) Inductor and Output Cap Output Cap Close to IC < 2mm trace must be > 750um Close to IC < 2mm These output caps’ GND should be isolated from the nearby GND trace and plane then connected to main GND directly.
  • Page 98 Design Guidelines for High-speed Digital Signals • LPDDR4X • PDN design  Others • MT6765 RF interface - MT6177 (RF transceiver) • MT6765 RF interface - MT6177M (RF transceiver) • MT6357 (PMU) • MT6631 (BT/FM/Wi-Fi/GPS) • MT6371 (battery charger/USB_PD) • eMMC/USB/MIPI/SIM card/T-card...
  • Page 99 eMMC/USB/MIPI/ SIM Card/T-Card/MSDC CONFIDENTIAL B...
  • Page 100 eMMC 5.x BreakOut Region Topology: Main routing on L1/L3, L2/L4 solid reference gnd: Breakout length ≦ 3810 um (as short as possible) Keep L2 as solid reference gnd as possible. Place the gnd stitching via between BGA ball and L2 gnd on both AP/eMMC. Trace Width (w) = Minimum Trace Width Trace Spacing ≧...
  • Page 101 USB 2.0 Differential pairs are well-shielded by GND and GND vias (adjacent and up/down layers).  Routing differential pair straight and symmetrically on the same layer.  USB2.0: Maximum of 2 via-hole/layer change.  Differential impedance P/N skew Total length* USB_DP/DM 90ohm <...
  • Page 102 MIPI ▪ MIPI signals’ differential impedance: 100Ω ▪ Total length < 6 inch (PCB + FPC + Module)  Lane-to-clock matching ≤ 2.5mm  P/N skew: ≤ 0.625mm for > 1.5Gbps ≤ 1.5mm for ≤ 1.5Gbps ▪ Well shielded by GND (adjacent and up/down layers ) is recommended;...
  • Page 103 SIM Card SIM1_SCLK/ SIM2_SCLK should be shielded by GND. CONFIDENTIAL B...
  • Page 104 MSDC1 T-Card Break Out Region Topology: Main routing on L1/L3, L2/L4 solid reference GND: Breakout length ≦ 300mil (as short as possible) A. Keep L2 as solid reference GNN as possible. Place the gnd stitching via between BGA ball and L2 gnd on both AP/eMMC. Trace width (W) = Minimum trace width D.
  • Page 105 Copyright © MediaTek Inc. All rights reserved. Copyright © MediaTek Inc. All rights reserved.