MEDIATEK Ralink MT7620 Programming Manual

Integrated 802.11n mac/bbp and 2.4 ghz rf/fem router-on-a-chip

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MT7620

PROGRAMMING

GUIDE

Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

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Summary of Contents for MEDIATEK Ralink MT7620

Page 1 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip...
Page 2: Functional Block Diagram
The MT7620 SoC includes a high performance 580 MHz MIPS24KEc CPU core and USB host controller/PHY, which is designed to enable a multitude of high performance, cost-effective IEEE 802.11n applications with a MediaTek (Ralink) client card. Functional Block Diagram 16-Bit...
Page 3: Table Of Contents
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Table of Contents 1. MIPS 24K PROCESSOR 1.1 F EATURES 1.2 B LOCK IAGRAM 1.3 M EMORY UMMARY 1.4 C LOCK 1.5 CPU C LOCK 2. REGISTERS 2.1 N OMENCLATURE 2.2 S YSTEM...
Page 4 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.9.4 R 1000_0900) EGISTER ESCRIPTIONS BASE 2.10 NAND F LASH ONTROLLER 2.10.1 F EATURES 2.10.2 N ORMAL 2.10.3 ECC 2.10.4 L IST OF EGISTERS 2.10.5 R 1000_0800) EGISTER ESCRIPTIONS BASE 2.11 PCM C ONTROLLER...
Page 5 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.17.5 OHCI O 101C.1000) PERATION EGISTERS BASE 2.18 USB D EVICE ONTROLLER 2.18.1 F EATURES 2.18.2 B LOCK IAGRAM 2.18.3 B 2.18.4 L EGACY 2.18.5 A GGREGATION 2.18.6 D GGREGATION 2.18.7 B GGREGATION...
Page 6 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.21.8 M 1015_0000) EMORY INDOWS EGISTERS BASE 2.21.9 IO W 1016_0000) INDOWS BASE 2.22 802.11 2T2R MAC/BBP 2.22.1 F EATURES 2.22.2 B LOCK IAGRAM 2.22.3 802.11 2T2R MAC/BBP R EGISTER 2.22.4 SCH/WPDMA R 1018_0000)
Page 7 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 5.2 SD H LOCK IAGRAM 5.2.1 B DMA M ASIC 5.2.2 L DMA M INKED ASED 5.2.3 DMA G (GPD) F ENERIC ACKET ESCRIPTOR ORMAT 5.2.4 DMA B (BD) F UFFER ESCRIPTOR ORMAT...
Page 8: Table Of Figures
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Table of Figures 1-1 MT7620 B .......................... 2 IGURE LOCK IAGRAM 1-1 MIPS 24KE .......................... 12 IGURE ROCESSOR 1-2 MT7620 C ........................14 IGURE LOCK IAGRAM 1-3 CPU C .............................
Page 9 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 4-4 R .......................... 489 IGURE ESCRIPTOR ORMAT 4-5 RXINFO F ........................... 490 IGURE ORMAT 4-6 RXWI F ..........................492 IGURE RAME ORMAT 5-1 SD H ........................497 IGURE LOCK IAGRAM 5-2 B DMA............................
Page 10: List Of Tables
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip List of Tables 2-1 UART L ......................... 75 ABLE NTERRUPT RIORITIES 2-2 PDMA R ........................191 ABLE IELD ESCRIPTIONS 2-3 R ............................. 249 ABLE 2-4 R ............................249 ABLE ONTROL 2-5 R ............................
Page 11: Mips 24K Processor
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 1. MIPS 24K Processor 1.1 Features  8-stage pipeline  32-bit address paths  64-bit data paths to caches and external interfaces  MIPS32-Compatible Instruction Set  Multiply-Accumulate and Multiply-Subtract Instructions (MADD, MADDU, MSUB, MSUBU) ...
Page 12: Block Diagram
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 1.2 Block Diagram ISPRAM DMA OCP I/F Off/on chip EJTAG Instruction i-cache 0/8/16/32/64 KB trace I/F scratchpad 4-way set associative Trace User-defined Off-chip CorExtend Debug I/F block CorExtend Fetch Unit 8-entry instruction buffer 512-entry BHT 4-entry RPS...
Page 13: Memory Map Summary
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 1.3 Memory Map Summary Start Size Description 0000.0000 0FFF.FFFF 256 MBytes DDR2 256 MB/ DDR1 256 MB/SDRAM 128 MB 1000.0000 1000.00FF 256 Bytes SYSCTL 1000.0100 1000.01FF 256 Bytes TIMER 1000.0200 1000.02FF 256 Bytes...
Page 14: Clock Plan
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 1.4 Clock Plan CLK_PERI 20/40 MHz (Timer/Uart/I2C/I2S) CLK_SDHC 48 MHz 12 MHz USB PHY (TSMC) 12/48 MHz 20/40 MHz Xtal in 20/40 MHz DRAM_CLK 600 MHz CPU_CLK PLL_CLK * SYS_CLK (1/M) 20/40 MHz...
Page 15: Cpu Clock Mux
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 1.5 CPU Clock Mux 20/40 MHz Crystal 480 MHz DRAM_CLK Fractional CPU_CLK Clock SYS_CLK Generator 600 MHz CPU_CLK_AUX0 CPU_SYS_CLKCFG: (offset: 0x003C) CPLL_CFG0: (offset: 0x0054) CPLL_CFG1: (offset: 0x0058) CPU_CLK_AUX1 Figure 1-3 CPU Clock Mux PGMT7620_V.1.0_040503 Page 15 of 523...
Page 16: Registers
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2. Registers 2.1 Nomenclature The following nomenclature is used for register types: Read Only Write Only Read or Write Read Clear Write One Clear Reserved bit Undefined binary value PGMT7620_V.1.0_040503 Page 16 of 523...
Page 17: System Control
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.2 System Control 2.2.1 Features  Provides read-only chip revision registers  Provides a window to access boot-strapping signals  Supports memory remapping configurations  Supports software reset to each platform building block ...
Page 18: List Of Registers
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.2.3 List of Registers Offset Register Name Description Page 0x0000 CHIPID0_3 Chip ID ASCII Character 0-3 0x0004 CHIPID4_7 Chip ID ASCII Character 4-7 0x000C REVID Chip Revision Identification 0x0010 SYSCFG0 System Configuration Register 0 0x0014...
Page 19: 1000_0000)
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.2.4 Register Descriptions (base: 0x1000_0000) 1. CHIPID0_3: Chip ID ASCII Character 0-3 (offset: 0x0000) Bits Type Name Description Initial Value 31:24 CHIP_ID3 ASCII CHIP Name Identification Character 3 0x36 23:16 CHIP_ID2 ASCII CHIP Name Identification Character 2...
Page 20 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value DRAM_FROM_EE DRAM Configuration from EEPROM 0: DRAM/PLL configuration from EEPROM. 1: DRAM configuration from Auto Detect. For more information see the Bootstrapping Pins Description in the datasheet for this chip. DBG_JTAG_MODE Debug JTAG Mode 0: EPHY_LED...
Page 21 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 25:24 DDR_DPIN_DRV SDRAM Data Pin Driving Setting* (DQ/DQS/DQM) [25:24] DDR1 DDR2 (3.3 V) (2.5 V/ 1.8 V) 10 mA Class II Full 8 mA 16 mA 4 mA (Class I) (Half)
Page 22 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 13:12 GE1_MODE Gigabit Port #1 Mode Sets the interface mode on Gigabit port 1. 2’b00: RGMII Mode (10/100/1000 Mbps) 2’b01: MII Mode (10/100 Mbps) 2’b10: Reverse MII Mode (10/100 Mbps) 2’b11: Reserved Reserved...
Page 23 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 31:0 BOOTSRAM_BASE Boot from SRAM base address (Test mode only) 0x10240000 Addr_tuned = bootsram[31:0] | oc_maddr[15:0] 9. Reserved (offset: 0x0024) Bits Type Name Description Initial Value 31:0...
Page 24 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 16:12 INT_CLK_FFRAC Internal Clock Fraction-N Frequency A parameter used in conjunction with INT_CLK_FDIV to generate the Fraction-N clock frequency. Valid values range from 0 to 31. Fraction-N clock Frequency = (INT_CLK_FFRAC/INT_CLK_FDIV)*PLL_FREQ 11:9...
Page 25 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value Reserved FE_ CLK_EN FE clock enable Reserved UARTL_ CLK_EN UART Lite clock enable SPI CLK_EN SPI clock enable I2S CLK_EN I2S clock enable I2C CLK_EN I2C clock enable NAND_CLK_EN...
Page 26 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value Resets the SPI block. Resets the I S block. Resets the I C block. NAND Resets the NAND block. Resets the DMA block. Resets the PIO block.
Page 27 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value R/W1C SWCPURST Software CPU Reset Indicates when software has reset the CPU by writing to the RSTCPU bit in RSTCTL. 0: Has no effect. 1: Clears this bit.
Page 28 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 12:8 CPU_FDIV CPU Frequency Divider The frequency divider is used to generate the CPU frequency. The value must be larger than or equal to CPU_FFRAC. Valid values range from 1 to 31.
Page 29 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip CLK_LUT_CFG: CPU and SYS Clock Auto Control (offset: 0x0040) Bits Type Name Description Initial Value SLP_EN Sleep Mode Enable Enables sleep mode when MIPS SI_Sleep is asserted. 0: Disable 1: Enable Sleep Mode CPU Frequency = (1/CPU_FDIV)*PLL_FREQ...
Page 30 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value STEP_FFRAC Step Frequency Fraction Sets the fractional size of the increment in CPU frequency after the CPU exits from sleep mode and returns to normal operation. This step is only valid when SLP_STEP_EN is enabled.
Page 31 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 18. BPLL_CFG0: BB PLL Configuration 0 (offset: 0x0048) Bits Type Name Description Initial Value BPLL_SW_CFG BB PLL Software Configuration Sets BB PLL parameters set by software. 0: Apply default parameters set by hardware. 1: Apply new parameters set by software in BPLL_CFG0 &...
Page 32 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 29:28 BBPL_ICPP PLL CPP current control Sets the proportional charge pump current. (Default: 01) 00: 25 μA 10: 75 μA 01: 50 μA 11: 100 μA 27:26 BBPL_ICPI...
Page 33 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 12:11 BBPL_TLCK BB PLL Time Lock The delay from when AFC is ready to when PLL starts locking. 00: 5 μs 10: 20 μs 01: 10 μs 11: 40 μs BBPL_FORCE...
Page 34 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value EC_CUPLLOK CPU Lock OK 0: Check AFC. After AFC, if F is within ± 3.2% of the target value, this bit is set to 1. 1: Set this bit to always indicate CPU Lock status is OK, and disable the AFC check.
Page 35 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 11:10 PLL_DIV_RATIO PLL Dividing Ratio Sets the ratio between the VCO and PLL output frequency. PLL_DIV_RATIO = F OUT. where = VCO frequency = PLL output frequency 00: 2 (default) 01: 3...
Page 36 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 21. CPLL_CFG1: CPU PLL Configuration 1 (offset: 0x0058) Bits Type Name Description Initial Value 31:27 Reserved CPLL_PD CPU PLL Power Down 0: Power on 1: Power down CPU_CLK_AUX1 CPU Clock Source Select Selects CPU source clock from aux0 or Xtal_IN pins.
Page 37 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 31:30 SUTIF_SHARE_MODE Serial UTIF Pin Share Mode Sets the serial UTIF pin to operate in UARTL or C mode. 0: Not shared 1: Shared with UARTL -overwrites the UARTLITE_GPIO_MODE setting.
Page 38 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value WLED_GPIO_MODE WLAN LED GPIO Share Mode Sets the WLAN LED pin to operate in GPIO mode. 0: Normal mode 1: GPIO Mode SPI_REFCLK0_MODE SPI Reference Clock GPO Share Mode Sets SPI pins to operate in reference clock and GPO mode.
Page 39: Pdma R
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip NOTE: For more information on pin sharing schemes, see the datasheet for this chip. 24. PCIPDMA_STAT: Control and Status of PDMA in PCIe Device (offset: 0x0064) Bits Type Name Description Initial Value 31:4...
Page 40 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 23:20 Reserved A_SSCPERI Analog Spread Spectrum Clock Generator (SSCG) Modulation Period Select 0: 16.5 kHz 1: 33 kHz A_SSCGEN Analog Spread Spectrum Clock Generator Enable 0: Disable 1: Enable...
Page 41 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 29:28 DIG_LDO_GAIN DIG_LDO gain control 00: High DC gain 00: Reserved 10: Reserved 11: Low DC gain 27:26 Reserved DIG_SW_SEL SW Configured Digital LDO output level 0: HW controlled DIG LDO 1: SW controlled DIG LDO field [24:16] DIG_LDO_EN...
Page 42 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 23:22 AFC_WAIT_TIME Automatic Frequency Control (AFC) Wait Time The time AFC waits until BIAS is ready. 00: 5 μs 01: 10 μs 10: 20 μs 11: 40 μs 21:20 PLL_LOCK_TIME...
Page 43 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value SSC_UP_BOUND Spread Spectrum Clock (SSC) Frequency Upper Boundary 00: 0 (default) 01: 1/4 SSC swing 10: 2/4 SSC swing 11: 3/4 SSC swing SSC_EN SSC Enable Enables the spread spectrum clock (SSC) to...
Page 44 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value PPLL_LD PPLL Lock 0: Unlock 1: Lock 22:14 EC_PEAFCOUT PCIe PLL AFC output 13:10 EC_PEPHDRFT PCIe PLL Phase Drift SSCG output code (two’s complement) FR_PEAFCSET PCIe PLL AFC Set 0xxxxxxxxx: Normal...
Page 45 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Description 11:10 Output voltage level Value Description 0.7 V 0.8 V 0.75 V 0.85 V Reserved Output termination adjustment Value Description Value Description Value Description 00000 01010 10101 00001 01011 10110...
Page 46: Timer
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.3 Timer 2.3.1 Features  Independent clock pre-scale for each timer.  Independent interrupts for each timer.  Two general-purpose timers which run at a 40 MHz clock rate. The other two run at a 32 kHz clock rate. ...
Page 47: Block Diagram
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.3.2 Block Diagram Timer Timer 0 Test Control Clock Reset Load Value Prescale Counter Mode Control Timer 0 Interrupt Timer 1 Interrupt Interrupt Control Timer 1 Watchdog Timeout Watchdog Status Test Control Load Value...
Page 48: List Of Registers
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.3.3 List of Registers Offset Register Name Description Page 0x0000 TMRSTAT Timer Status 0x0010 TMR0LOAD Timer 0 Load Value 0x0014 TMR0VAL Timer 0 Counter Value 0x0018 TMR0CTL Timer 0 Control 0x0020 TMR1LOAD Timer 1 Load Value...
Page 49: Register Descriptions ( Base : 0 X 1000_0100)
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.3.4 Register Descriptions (base: 0x1000_0100) 30. TMRSTAT: Timer Status Register (offset: 0x0000) Bits Type Name Description Initial Value 31:6 Reserved TMR1RST Timer 1 Reset Read Reading this bit returns a 0. Write 0: No effect.
Page 50 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 31. TMR0LOAD: Timer 0 Load Value (offset: 0x0010) Bits Type Name Description Initial Value 31:16 Reserved 15:0 TMRLOAD Timer Load Value This register contains the load value for the timer.
Page 51 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value PRESCALE Timer Clock Pre-scale These bits are used to scale the timer clock in order to achieve higher resolution or longer timer periods. Their definitions are below. Value Timer Clock Frequency System clock...
Page 52 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 14:8 Reserved ENABLE Timer Enable Enables the 40 MHz timer1. 0: Disable the timer. The timer will stop counting and will retain its current value. 1: Enable the timer.
Page 53: Interrupt Controller
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.4 Interrupt Controller 2.4.1 Features  Supports a central point for interrupt aggregation for platform related blocks  Separated interrupt enable and disable registers  Supports global disable function ...
Page 54: List Of Registers
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.4.3 List of Registers Offset Register Name Description Page 0x0000 IRQ0STAT Interrupt Type 0 Status after Enable Mask 0x0004 IRQ1STAT Interrupt Type 1 Status after Enable Mask 0x0020 INTTYPE Interrupt Type 0x0030 INTRAW...
Page 55: Register Descriptions ( Base : 0 X 1000_0200)
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.4.4 Register Descriptions (base: 0x1000_0200) 37. IRQ0STAT: Interrupt Type 0 Status after Enable Mask (offset: 0x0000) Bits Type Name Description Initial Value 31:20 Reserved UDEV USB device interrupt status after mask UHST USB host interrupt status after mask Ethernet Switch interrupt status after mask...
Page 56 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value SDHC SDHC interrupt after mask Reserved UARTLITE UARTLITE interrupt status after mask SPI interrupt status after mask I2S interrupt status after mask MIPS performance counter interrupt status after mask Reserved DMA interrupt status after mask...
Page 57 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value PIO interrupt status type UART UART interrupt status type PCM interrupt status type ILL_ACC Illegal access interrupt status type WDTIMER Watchdog timer interrupt status type TIMER0 Timer 0 interrupt status type SYSCTL...
Page 58 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 41. INTENA: Interrupt Enable (offset: 0x0034) Bits Type Name Description Initial Value GLOBAL Global Interrupt Enable Allows local interrupts in this register to be individually enabled. Set this bit before enabling interrupts in this register.
Page 59 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value SDHC SDHC interrupt disable Reserved UARTLITE UARTLITE interrupt disable SPI interrupt disable I2S interrupt disable MIPS performance counter interrupt disable NAND NAND flash controller interrupt disable DMA interrupt disable PIO interrupt disable UART...
Page 60: System Tick Counter
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.5 System Tick Counter 2.5.1 List of Registers Offset Register Name Description Page 0x0000 STCK_CNT_CFG MIPS Configuration 0x0004 CMP_CNT MIPS Compare 0x0008 MIPS Counter PGMT7620_V.1.0_040503 Page 60 of 523...
Page 61: Register Descriptions ( Base : 0 X 1000_0 D 00)
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.5.2 Register Descriptions (base: 0x1000_0d00) 43. STCK_CNT_CFG: MIPS Configuration Register (offset: 0x0000) Bits Type Name Description Initial Value 31:2 Reserved EXT_STK_EN External System Tick Enable Selects the system tick source 0: Use the MIPS internal timer interrupt.
Page 62: Uart
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.6 UART 2.6.1 Features  16550-compatible register set, except for Divisor Latch register  5-8 data bits  1-2 stop bits (1 or 2 stop bits are supported with 5 data bits) ...
Page 63: List Of Registers
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.6.3 List of Registers Offset Register Name Description Page 0x0000 Receive Buffer Register 0x0004 Transmit Buffer Register 0x0008 Interrupt Enable Register 0x000C Interrupt Identification Register 0x0010 FIFO Control Register 0x0014 LCRLCR Line Control Register...
Page 64: Register Descriptions ( Base : 0 X 1000_0500)
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.6.4 Register Descriptions (base: 0x1000_0500) 46. RBR: Receive Buffer Register (offset: 0x0000) Bits Type Name Description Initial Value 31:8 Reserved Receive Buffer Data Data is transferred to this register from the receive shift register after a full character is received.
Page 65 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value ERBFI Enable Rx Buffer Full Interrupt Enables the receive buffer full interrupt, as well as the data ready (DR) and character time-out interrupts. NOTE: 0: Disable 1: Enable...
Page 66 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 50. FCR: FIFO Control Register (offset: 0x0010) Bits Type Name Description Initial Value 31:8 Reserved RXTRIG Rx Trigger Level Sets the number of characters contained by the receive buffer which triggers assertion of the data ready (DR) interrupt.
Page 67 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value SETBRK Set Break Condition 0: Normal functionality. 1: Force TXD pin to 0. Tx otherwise operates normally. FORCEPAR Force Parity Bit 0: Normal functionality. 1: If even parity is selected, the (transmitted and checked) parity is forced to 0.
Page 68 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value LOOP Loopback Mode Enable 0: Normal Operation. 1: The UART is put into loopback mode, and used for self-testiing. The TXD pin is driven high;...
Page 69 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value Break Interrupt Indicates that a break is received, that is, when the RXD signal is at a low state for more than one character transmission time (from Start Bit to Stop Bit).
Page 70 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value TERI Trailing Edge Ring Indicator Indicates when the RIN (Ring Indicator) pin changes from a low to a high value. DDSR Delta Data Set Ready Indicates when the DSRN (Data Set Ready) pin changes.
Page 71 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 57. DLLO: Clock Divider Divisor Latch Low (offset: 0x002C) Bits Type Name Description Initial Value 31:8 Reserved DLLO This register is the equivalent to the lower 8 bits of the DL register. It is provided for16550 compatibility.
Page 72: Uart Lite
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.7 UART Lite 2.7.1 Features  2-pin UART  16550-compatible register set, except for Divisor Latch register  5-8 data bits  1-2 stop bits (1 or 2 stop bits are supported with 5 data bits) ...
Page 73: List Of Registers
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.7.3 List of Registers Offset Register Name Description Page 0x0000 Receive Buffer Register 0x0004 Transmit Buffer Register 0x0008 Interrupt Enable Register 0x000C Interrupt Identification Register 0x0010 FIFO Control Register 0x0014 Line Control Register 0x0018...
Page 74: Register Descriptions ( Base : 0 X 1000_0C00)
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.7.4 Register Descriptions (base: 0x1000_0C00) 59. RBR: Receive Buffer Register (offset: 0x0000) Bits Type Name Description Initial Value 31:8 Reserved Receive Buffer Data Data is transferred to this register from the Rx shift register after a full character is received.
Page 75: Uart Lite Interrupt Priorities
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 62. IIR: Interrupt Identification Register (offset: 0x000C) Bits Type Name Description Initial Value 31:8 Reserved FIFOENA FIFOs Enabled These bits reflect the FIFO enable bit setting in the FIFO Control Register. 00: FIFO enable bit is cleared.
Page 76 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 63. FCR: FIFO Control Register (offset: 0x0010) Bits Type Name Description Initial Value 31:8 Reserved RXTRIG Rx Trigger Level Sets the number of characters contained by the receive buffer which triggers the data ready (DR) interrupt.
Page 77 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value SETBRK Set Break Condition 0: Normal functionality. 1: Force TXD pin to 0. Tx otherwise operates normally. FORCEPAR Force Parity Bit 0: Normal functionality. 1: If even parity is selected, the (transmitted and checked) parity is forced to 0.
Page 78 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 66. LSR: Line Status Register (offset: 0x001C) Bits Type Name Description Initial Value 31:8 Reserved ERINFIFO Error in FIFO Indicates that a FIFO contains data which was received with a parity error, framing error, or break condition.
Page 79 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 67. DL: Clock Divider Divisor Latch (offset: 0x0028) Bits Type Name Description Initial Value 31:16 Reserved 15:0 Divisor Latch This register is used in the clock divider to generate the baud clock. The baud rate (transfer rate in bits per second) is defined as: Baud rate = system clock frequency / (CLKDIV * 16).
Page 80 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 69. DLHI: Clock Divider Divisor Latch High (offset: 0x0030) Bits Type Name Description Initial Value 31:8 Reserved DLHI Divisor Latch High This register is the equivalent to the upper 8 bits of the DL register.
Page 81: Programmable I/O
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.8 Programmable I/O 2.8.1 Features  Supports 73 programmable I/Os  Parameterized numbers of independent inputs, outputs, and inputs  Independent polarity controls for each pin  Independently masked edge detect interrupt on any input transition ...
Page 82: List Of Registers
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.8.3 List of Registers Offset Register Name Description Page 0x0000 GPIO23_00_INT PIO Pin Ports 23 to 00 Interrupt Status 0x0004 GPIO23_00_EDGE PIO Pin Ports 23 to 00 Edge Status 0x0008 GPIO23_00_RMASK PIO Pin Ports 23 to 00 Rising Edge Interrupt Mask...
Page 83 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 0x00A8 GPIO72_RESET PIO Pin Port 72 Clear Data Bit 0x00AC GPIO72_TOG PIO Pin Port 72 Toggle Data Bit PGMT7620_V.1.0_040503 Page 83 of 523...
Page 84: Register Descriptions ( Base : 0 X 1000_0600)
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.8.4 Register Descriptions (base: 0x1000_0600) 71. GPIO23_00_INT: PIO Pin Interrupt Status (offset: 0x0000) Bits Type Name Description Initial Value 31:24 Reserved 23:0 PIOINT PIO Pin Interrupt A PIOINT bit is set when its corresponding PIO pin changes value and the edge for that pin is enabled via the PIORMASK or PIOFMASK register.
Page 85 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 73. GPIO23_00_RMASK: PIO Pin Rising Edge Interrupt Mask (offset: 0x0008) Bits Type Name Description Initial Value 31:24 Reserved 23:0 PIORMASK PIO Pin Rising Edge Interrupt Mask Masks the PIO interrupt indicating when data on the corresponding PIO pin transitions from a 0 to a 1, i.e.
Page 86 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 76. GPIO23_00_DIR: PIO Pin Direction (offset: 0x0024) Bits Type Name Description Initial Value 31:24 Reserved 23:0 PIODIR PIO Pin Direction Sets the data direction on PIO pins corresponding to bits in this register. 0: Set data direction to input.
Page 87 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 23:0 PIOTOG PIO Pin Toggle Toggles the corresponding bit in the PIODATA output register. 0: No effect. 1: Invert the selected PIODATA bit. 81.
Page 88 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:0 PIOEDGE The PIOEDGE bits have different meanings depending on whether the interrupt for that pin is enabled via the PIORMASK or PIOFMASK register.
Page 89 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 85. GPIO39_24_DATA: PIO Pin Data (offset: 0x0048) Bits Type Name Description Initial Value 31:16 Reserved 15:0 PIODATA PIO Pin Data These bits are used for driving or sensing static signals on the PIO pins.
Page 90 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 88. GPIO39_24_SET: Set PIO Pin Data Bit (offset: 0x0054) Bits Type Name Description Initial Value 31:16 Reserved 15:0 PIOSET PIO Pin Set Sets the corresponding bit in the PIODATA output register.
Page 91 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 92. GPIO71_40_EDGE: PIO Pin Edge Status (offset: 0x0064) Bits Type Name Description Initial Value 31:0 PIOEDGE The PIOEDGE bits have different meanings depending on whether the interrupt for that pin is enabled via the PIORMASK or PIOFMASK register.
Page 92 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 95. GPIO71_40_DATA: PIO Pin Data (offset: 0x0070) Bits Type Name Description Initial Value 31:0 PIODATA PIO Pin Data These bits are used for driving or sensing static signals on the PIO pins. To drive a value onto a PIO pin, the corresponding bit in the PIODIR register must be set.
Page 93 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 98. GPIO71_40_SET: Set PIO Pin Data Bit (offset: 0x007C) Bits Type Name Description Initial Value 31:0 PIOSET PIO Pin Set Sets the corresponding bit in the PIODATA output register. 0: No effect.
Page 94 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value PIOEDGE The PIOEDGE bits have different meanings depending on whether the interrupt for that pin is enabled via the PIORMASK or PIOFMASK register. Read If the PIO PIN Interrupt for this PIO pin is asserted, the corresponding PIOEDGE bit...
Page 95 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 105. GPIO72_DATA: PIO Pin Data (offset: 0x0098) Bits Type Name Description Initial Value 31:1 Reserved PIODATA PIO Pin Data These bits are used for driving or sensing static signals on the PIO pins. To drive a value onto a PIO pin, the corresponding bit in the PIODIR register must be set.
Page 96 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 108. GPIO72_SET: Set PIO Pin Data Bit (offset: 0x00A4) Bits Type Name Description Initial Value 31:1 Reserved PIOSET PIO Pin Set Sets the corresponding bit in the PIODATA output register. 0: No effect.
Page 97: I 2 C Controller
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.9 I C Controller 2.9.1 Features  Programmable I C bus clock rate  Supports the Synchronous Inter-Integrated Circuits (I C) serial protocol  Bi-directional data transfer  Programmable address width up to 8 bits ...
Page 98: List Of Registers
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.9.3 List of Registers Offset Register Name Description Page 0x0000 CONFIG C Configuration 0x0004 CLKDIV C Clock Divisor 0x0008 DEVADDR C Device Address 0x000C ADDR C Address 0x0010 DATAOUT C Data Out 0x0014 DATAIN...
Page 99: Register Descriptions ( Base : 0 X 1000_0900)
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.9.4 Register Descriptions (base: 0x1000_0900) 111. CONFIG: I C Configuration Register (offset: 0x0000) Bits Type Name Description Initial Value 31:8 Reserved ADDRLEN Address Length The value written to this register plus one indicates the number of address bits to be transferred from the I2C ADDR register.
Page 100 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:0 CLKDIV Clock Divisor The value written to this register is used to generate the I2C bus SCLK signal by applying the following equation: SCLK frequency = 40 MHz / ( 2 x CLKDIV ) NOTE: 1.
Page 101 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 116. DATAIN: I C Data In Register (offset: 0x0014) Bits Type Name Description Initial Value 31:8 Reserved DATAIN C Data In These bits store the 8-bits of data received from the external I2C slave devices during a read transaction.
Page 102 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value BUSY C State Machine Busy 0: The I2C interface is idle. Firmware may initiate an I2C transfer. 1: Indicates the I2C interface is active, and firmware should not modify any I2C host controller.
Page 103 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.9.4.1 I C Programming Description Write Operation: (Single) DEV_ADR A(S) SUB_ADR A(S) DATA A(S) DEV_ADR A(S) SUB_ADR A(S) DATA A(M) NOTE: The bit-width of DEV_ADR is defined in REG(CONFIG) bit[7:5] The bit-width of SUB_ADR is defined in REG(CONFIG) bit[4:2] NOTE: As REG(CONFIG) bit[1]=1'b1, the SUB_ADR field will be absent.
Page 104 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Multiple Data Transfer: (write operation.) E.g. we want to write (n+1) beats data by I2C DEV_ADR A(S) SUB_ADR A(S) DATA A(S) DATA A(S) (N+1) bytes Burst Write Operation: 1) Write the DEV_ADDR and SUB_ADDR to REG(DEVADDR) & REG(ADDR) 2) Write (N) to REG(BYTECNT).
Page 105: Nand Flash Controller
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.10 NAND Flash Controller 2.10.1 Features  Supports read/erase/page program NAND flash memory.  Hardware ECC engine. (Hardware generating and software correcting)  Supports NAND flash memory with 512-byte and 2048-byte page size. ...
Page 106 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 1 byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2 byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 P2048 3 byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0...
Page 107 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip The figure below shows the hardware ECC detection flow chart. New ECC generated during data read XOR previous ECC with new All results = 0 Error detected : No error 11 bits data = 1 (correctable error) 1 bit data = 1 (ECC error) Figure 2-10 Hardware ECC Detection Flowchart...
Page 108: List Of Registers
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.10.4 List of Registers Offset Register Name Description Page 0x0010 CTRL0 Control 0 0x0014 TRANS_CFG Transfer Configuration 0x0018 CMD1 Command 1 0x001C CMD2 Command 2 0x0020 CMD3 Command 3 0x0024 ADDR Address...
Page 109: Register Descriptions ( Base : 0 X 1000_0800)
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.10.5 Register Descriptions (base: 0x1000_0800) 120. CTRL0: Control 0 (offset: 0x0010) Bits Type Name Description Initial Value 31:24 Reserved 23:16 TWAITB Time Wait Busy Signal Dummy time period to wait for a busy signal = clock * (TWAITB + 1) 15:12 THOLD...
Page 110 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value BNUM_CMD1 Byte Number Of Commands 1 Sets the number of bytes in a command. (unit: bytes) RESPB_DATA Respect busy signal after data phase. 0: Disable 1: Enable RESPB_ADDR...
Page 111 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 31:24 Reserved 23:16 CMD2_BYTE3 3rd byte of command 2 15:8 CMD2_BYTE2 2nd byte of command 2 CMD2_BYTE1 1st byte of command 2 124. CMD3: Command 3 (offset: 0x0020) Bits Type Name...
Page 112 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value DEC_ERR Decode Error Shows the ECC decode check status. 0: No error 1: Correctable error or ECC error BUSY NAND flash controller is busy. 0: Idle 1: Busy 128.
Page 113 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:12 ECC_BYTE2_LOC The location of 2 ECC byte in spare 16-byte 11:8 ECC_BYTE1_LOCT The location of 1 ECC byte in spare 16-byte Reserved DATA_BYTE_SWAP Data Byte Swap Enable 0: Disable...
Page 114 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value ECC_ERR HW ECC Failed 0: Pass 1: Fail 136. ECC_ERR_PAGE2: ECC Error Information Page 2 (offset: 0x0054) Bits Type Name Description Initial Value 31:15 Reserved 14:6...
Page 115 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value ECC_ERR HW ECC Failed 0: Pass 1: Fail 139. ADDR2: Address 2 (offset: 0x0060) Bits Type Name Description Initial Value 31:24 Reserved 23:16 ADD_BYTE7 7th byte of NAND memory address 15:8...
Page 116: Pcm Controller
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.11 PCM Controller 2.11.1 Features  PCM module provides PBUS interface for register configuration and data transfer  Two clock sources are reserved for PCM circuit. (From internal clock generator, INT_PCM_CLK and EXT_PCM_CLK) ...
Page 117 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Two clock domains are partitioned in this design. PCM converter (u-law < = > raw-16-bit and A-law < = > raw 16-bit) are implemented in PCM. The threshold of FIFO is configurable. When the threshold is reached, PCM (a) triggers the DMA interface to notify external DMA engine to transfer data, and (b) triggers an interrupt to the host.
Page 118: List Of Registers
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.11.3 List of Registers Offset Register Name Description Page 0x0000 GLB_CFG Global Configuration 0x0004 PCM_CFG PCM Configuration 0x0008 INT_STATUS Interrupt Status 0x000C INT_EN Interrupt Enable 0x0010, 0x0110 CHA_FF_STATUSn Channel A FIFO Status n 0x0014, 0x0114 CHB_FF_STATUSn Channel B FIFO Status n...
Page 119: 1000_2000)
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.11.4 Register Descriptions (base: 0x1000_2000) 140. GLB_CFG: (offset: 0x0000) Bits Type Name Description Initial Value PCM_EN PCM Enable When disabled, all FSM of PCM are cleared to their default value. 0: Disable 1: Enable DMA_EN...
Page 120 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 141. PCM_CFG: (offset: 0x0004) Bits Type Name Description Initial Value Reserved for future. CLKOUT_EN PCM Clock Out Enable 0: A PCM clock is provided from the external Codec/OSC. 1: A PCM clock is provided from the internal dividor.
Page 121 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 142. INT_STATUS: (offset: 0x0008) Bits Type Name Description Initial Value 31:8 Reserved R/W1C CHT_DMA_ Channel Tx DMA Fault Interrupt FAULT Asserts when a fault has been detected in a CH- Tx DMA signal.
Page 122 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value INT4_EN INT_STATUS[4] Enable Enables the Channel Tx Threshold Interrupt. This interrupt when the CH-Tx FIFO is lower than the defined threshold. INT3_EN INT_STATUS[3] Enable Enables the Channel Rx DMA Fault Interrupt.
Page 123 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value CHRX_THRES Rx FIFO Below Threshold Interrupt Asserts when the Channel A FIFO is lower than the defined threshold. 15:8 Reserved CHRFF_AVCNT Channel A RXFIFO Available Space Count Counts the available space for reads in channel A RXFIFO.
Page 124 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value CHRX_THRES Rx FIFO Below Threshold Interrupt Asserts when the Channel B FIFO is lower than the defined threshold. 15:8 Reserved CHRFF_AVCNT Channel B Rx FIFO Available Space Count Counts the available space for reads in channel A Rx FIFO.
Page 125 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value TS_START Timeslot starting location (unit: clock cycles) 147. CHnB_CFG: (offset: 0x0024, 0x0124) (n=0, 1) Bits Type Name Description Initial Value 31:30 Reserved 29:27 CMP_MODE Compression Mode Sets the conversion method for the hardware...
Page 126 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value POS_DRV_DT Positive Edge Drive Data Sets the PCM controller to drive data on the negative or positive edge of the PCM clock. 0: Negative edge 1: Positive edge POS_CAP_FSYNC Positive Edge Capture FSYNC...
Page 127 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 151. IP_INFO: (offset: 0x0040) Bits Type Name Description Initial Value 31:16 Reserved 15:8 MAX_CH Maximum channel number. Version of this PCM Controller 152. RSV_REG16: (offset: 0x0038) Bits Type Name Description Initial Value 31:16...
Page 128 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value TXD_GLT_ST TXD Glitch Status Indicates if a glitch is detected in a TXD signal. It can be cleared by bit[31]. 0: Not detected. 1: Detected 25:23 Reserved...
Page 129 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value CHEN_DLYVAL Delay Count Value The delay error = CLK_PERIOD * (SYNC_DELAY + SYNC_DELTA + (DLYCNT_CFG) + 1) For example, DLYCNT_CFG = 4, (SYNC_DELAY is always fixed to 4) Final Delay = CLK_PERIOD * (2 + (-1/0/+1) + (4) + 1) = CLK_PERIOD * (6/7/8)= CLK_PERIOD * (6 to 8)
Page 130: Pcm Configuration
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.11.5 PCM Configuration 2.11.5.1 PCM Initialization Flow 1. Set PCM_CFG 2. Set CH0/1_CFG 3. Write PCM data to FIFO CH0/1_FIFO 4. Set GLB_CFG to enable the PCM and channel. 5.
Page 131 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Case 3: CFG_FSYNC Register: CFG_FSYNC_EN = 1, START_LOC=0x1A, interval=2 CH0_CFG Register: TS_START=1 (disable) CH1_CFG Register: TS_START=0x1A PCM_CFG Register: LONG_FSYNC=1’b0, FSYNC_POL=1’b0 (LOW active), DRX_TRI=1’b0, SLOT_MODE=3’b0, RAW16-bits PGMT7620_V.1.0_040503 Page 131 of 523...
Page 132: Generic Dma Controller
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.12 Generic DMA Controller 2.12.1 Features  Supports 16 DMA channels  Supports 32 bit address.  Maximum 65535 byte transfer  Programmable DMA burst size (1, 2, 4, 8, 16 double word burst) ...
Page 133: Peripheral Channel Connection
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.12.3 Peripheral Channel Connection Channel number Peripheral Reserved ND Controller I2S Controller (TXDMA) I2S Controller (RXDMA) PCM Controller (RDMA, channel-0) PCM Controller (RDMA, channel-1) PCM Controller (TDMA, channel-0) PCM Controller (TDMA, channel-1) PCM Controller (RDMA, channel-2) PCM Controller (RDMA, channel-3) PCM Controller (TDMA, channel-2)
Page 134: List Of Registers
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.12.4 List of Registers Offset Register Name Description Page 0x0000, 0x0010, 0x0020, GDMA_SAn GDMA Channel n Source Address 0x0030, 0x0040, 0x0050, 0x0060, 0x0070, 0x0080, 0x0090, 0x00A0, 0x00B0, 0x00C0, 0x00D0, 0x00E0, 0x00F0 0x0004, 0x0014, 0x0024, GDMA_DAn...
Page 135: Register Descriptions ( Base : 0 X 1000_2800)
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.12.5 Register Descriptions (base: 0x1000_2800) 160. GDMA_SAn: GDMA Channel n Source Address (offset: 0x0000, 0x0010, 0x0020, 0x0030, 0x0040, 0x0050, 0x0060, 0x0070, 0x0080, 0x0090, 0x00A0, 0x00B0, 0x00C0, 0x00D0, 0x00E0, 0x00F0) (n: 0 to 15) Bits Type Name...
Page 136 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value Channel Enable Channel Enable ‘b0: Disable ‘b1: Enable If CONTINUOUS MODE ENABLE=0, this bit is de- asserted by hardware after the number of bytes transferred reaches the Target Transfer Count.
Page 137 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 13:8 Destination DMA Request Selects the destination DMA request. 0: DMA_REQ0 1: DMA_REQ1 2: DMA_REQ2 … n: DMA_REQn 32: The destination of the transfer is memory. Others: Undefined Next Channel to Unmask Selects the next unmasked channel.
Page 138 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 31:0 Unmask Fail Interrupt Indicates the status of unmasked fail interrupt. This bit is set when the hardware tries to clear the Channel Mask bit of Next Channel to Unmask but the Channel Mask bit is 0 already.
Page 139: Spi Controller
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.13 SPI Controller 2.13.1 Features  Supports up to 2 SPI master operations  Programmable clock polarity  Programmable interface clock rate  Programmable bit ordering  Firmware-controlled SPI enable ...
Page 140: List Of Registers
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.13.3 List of Registers Offset Register Name Description Page 0x0000 SPISTAT0171 SPI Interface 0 Status 0x0004 Reserved 0x0008 Reserved 0x000C Reserved 0x0010 SPICFG0 SPI Interface 0 Configuration 0x0014 SPICTL0 SPI Interface 0 Control 0x0020 SPIDATA0...
Page 141: Register Descriptions ( Base : 0 X 1000_0B00)
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.13.4 Register Descriptions (base: 0x1000_0B00) 170. SPISTAT0: SPI Interface 0 Status (offset: 0x0000) Bits Type Name Description Initial Value 31:1 Reserved BUSY Indicates SPI transfer in progress 0: The SPI interface is inactive. 1: An SPI transfer is in progress.
Page 142 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value SPIENMODE SPI Enable Mode 0: SPI Enable is controlled by SW register settings (SPICTL0) 1: SPI Enable is controlled by HW (SPI Flash CMD) MSBFIRST Bit Transfer Order...
Page 143 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value START Start SPI Flash Transaction Mode 0: No effect 1: Starts SPI internal controller to start an SPI instruction transaction. NOTE: The BUSY bit in the SPISTAT register is set when this bit is set and is cleared when the data transfer is complete.
Page 144 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value SPIDATA SPI Data Transfer This register is used for command/data transfers on the SPI interface. The use of this register is given below: Write The bits to be transferred are written here, including both command and data bits.
Page 145 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value INSTR_PHASE Instruction Phase 0: No instruction bytes 1: One byte instruction phase (SPIDATA0) 19:17 ADDR_PHASE Address Phase 000: No address byte 001: One byte address phase (SPIADDR0[31:24]) 010: Two byte address phase (SPIADDR0[31:16])
Page 146 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value DATA_TYPE Data Transfer Type 001: Single Address Mode 010: Dual Address Mode 100: Quad Address Mode Others: Reserved 180. SPITXFIFO0: SPI Interface 0 TX_FIFO (offset: 0x0030) Bits Type Name...
Page 147 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 183. SPIMD0: SPI Interface 0 Mode (offset: 0x003C) Bits Type Name Description Initial Value 31:24 SPI_MODE SPI Flash Mode Selects the SPI flash mode. Available modes depend on the SPI flash vendor. For more information on available modes, please check the datasheet provided by the SPI vendor.
Page 148 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value SPICLKPOL SPI Clock Default Polarity Sets the default state of the SPICLK. 0: Logic 0 1: Logic 1 NOTE: This bit is ignored if the SPI interface block is a slave (SPISLAVE bit is set).
Page 149 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value STARTWR Start SPI Write Transfer 0: No effect. 1: The contents of the SPIDATA register are transferred to the SPI slave device. NOTE: The BUSY bit in the SPISTAT register is set when this bit is set and is cleared when the data transfer is complete.
Page 150 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 188. SPIDMA: SPI Interface DMA (offset: 0x0080) Bits Type Name Description Initial Value 31:11 Reserved 10:9 TxBurstSize The number of transfers in a Tx burst transaction. ‘b00: 1 transfer ‘b01: 2 transfers ‘b10: 4 transfers Others: Undefined...
Page 151 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 18:16 CSCTL Chip Select Control 000: SPI control for chip select 0 001: SPI control for chip select 1 010-111: Reserved 15:2 Reserved SPI1_POR SPI1 Pin Polarity Read Indicates that the SPI device on interface 1 is...
Page 152: I2S Controller
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.14 I2S Controller 2.14.1 Features  I2S transmitter/receiver, which can be configured as master or slave.  Supports 16-bit data, sampling rates of 8 kHz, 16 kHz, 22.05 kHz, 44.1 kHz, and 48 kHz ...
Page 153: I 2 S Signal Timing For I 2 S Data Format
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.14.3 I S Signal Timing For I S Data Format Figure 2-15 I2S Transmit/Receive Serial data is transmitted in 2’s complement with the MSB first. The transmitter always sends the MSB of the next word one clock period after the WS changes.
Page 154: List Of Registers
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.14.4 List of Registers Offset Register Name Description Page 0x0000 I2S_CFG S Configuration 0x0004 INT_STATUS Interrupt Status 0x0008 INT_EN Interrupt Enable 0x000C FF_STATUS FIFO Status 0x0010 TX_FIFO_WREG Transmit FIFO Write to Register 0x0014 RX_FIFO_RREG Receive FIFO Read Register...
Page 155: Register Descriptions ( Base : 0 X 1000_0A00)
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.14.5 Register Descriptions (base: 0x1000_0A00) 191. I2S_CFG: I S Tx/Rx Configuration Register (offset: 0x0000) Bits Type Name Description Initial Value I2S_EN S Enable Enables I S. When disabled, all I S control registers are cleared to their initial values.
Page 156 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 192. INT_STATUS: I S Interrupt Status (offset: 0x0004) Bits Type Name Description Initial Value 31:8 Reserved RX_DMA_FAULT Rx DMA Fault Detected Interrupt Asserts when a fault is detected in Rx DMA signals.
Page 157 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value TX_INT3_EN INT_STATUS[3] Enable Enables the Tx DMA Fault Detected Interrupt. This interrupt asserts when a fault is detected in Tx DMA signals. TX_INT2_EN INT_STATUS[2] Enable Enables the Tx FIFO Overrun Interrupt.
Page 158 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value EXT_LBK_EN Enables external loopback. 0: Normal mode 1: Enables external loop back. External A/D  Rx  Tx  External D/A 29:0 Reserved 198.
Page 159: Memory Controller
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.15 Memory Controller 2.15.1 Features  1 SDRAM/DDR2 (16 b) chip selection  128 MB (SDRAM)/128 MB (DDR1)/256 MB (DDR2) per chip selection  SDRAM transaction overlapping by early active and hidden pre-charge ...
Page 160: Sdram Power Saving Configuration
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.15.4 SDRAM Power Saving Configuration To configure power-saving, use the registers provided for each DRAM size. Size DRAM width (16-bit), total bus width 16 16 Mb SDRAM0: 0x11825282 SDRAM1: 0xFB000E7E 64 Mb SDRAM0: 0x12825282 SDRAM1: 0xC00103A9...
Page 161: Ddr Initialization Sequence
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.15.5 DDR Initialization Sequence DDR devices require an initialization sequence before they are ready for re-write access. The initialization sequence is described below. 1. Wait for 200 μs to set bit[10] to 0 in address 0x1000_0034. 2.
Page 162: List Of Registers
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.15.6 List of Registers Offset Register Name Description Page 0x0000 SDRAM_CFG0 SDRAM Configuration 0 0x0004 SDRAM_CFG1 SDRAM Configuration 1 0x0008 TCH_ARB_CFG Two Channel Arbiter Configuration 0x0010 ILL_ACC_ADDR Illegal Access Address Capture 0x0014 ILL_ACC_TYPE Illegal Access Type Capture...
Page 163: Register Descriptions ( Base : 0 X 1000_0300)
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.15.7 Register Descriptions (base: 0x1000_0300) 200. SDRAM_CFG0: SDRAM Configuration 0 (offset: 0x0000) Bits Type Name Description Initial Value DIS_CLK_GT Disable Clock Gating Disables clock gating of the SDR DRAM controller.
Page 164 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RBC_MAPPING RBC Mapping Selects the address mapping scheme. 0: {BANK ADDR, ROW ADDR, COL ADDR} address mapping scheme 1: {ROW ADDR, BANK ADDR, COL ADDR} address mapping scheme PWR_DOWN_EN Power Down Enable...
Page 165 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 202. TCH_ARB_CFG: (offset: 0x0008) Bits Type Name Description Initial Value 31:27 Reserved PREEMPT_EN Preemption Enable Requests preemption. A higher priority requestor may interrupt a lower priority channel. 0: Disable 1: Enable 25:0 Reserved...
Page 166 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 10:8 ILL_IID Illegal Access Initiator ID Indicates the initiator ID of the illegal access. 0: CPU 1: DMA 2: PPE 3: Ethernet PDMA Rx 4: Ethernet PDMA Tx 5: PCI/PCIE 6: Embedded WLAN MAC/BBP...
Page 167 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value SR_AUTO_EN Auto Self-Refresh Enable Enables auto self-refresh for power saving. 0: Disable 1: Enable Reserved SRACK_B Self-Refresh Acknowledge Status Indicates whether DDR2 is in self-refresh mode or has exited from self-refresh mode.
Page 168 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 23:0 SR_TAR_CNT Self-Refresh Time Count 0x3FFFF This counter is only referenced when the SDR (PWR_DOWN_EN ) or DDR2 (SR_AUTO_EN) is set. This counter measures the period SDR or DDR2 is in IDLE status.
Page 169 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 22:19 Pre-charge to Active The number of clock cycles needed for the command time SDRAM to recover from a pre-charge command and ready to accept the next active command. To obtain this value, one should divide the RAS# pre-charge time of the SDRAM (T ) by the clock...
Page 170 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 20:18 DDR2 size 000: Reserved 001: Individual DDR2 is 64 Mbit, (DDR only) 010: Individual DDR2 is 128 Mbit, (DDR only) 011: Individual DDR2 is 256 Mbit. 100: Individual DDR2 is 512 Mbit.
Page 171 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 210. DDR_CFG2: (offset: 0x0048) Bits Type Name Description Initial Value REGE This bit should be high when external registers are inserted in the controller and address signals are sent between the controller and the DDR SDRAM.
Page 172 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 23:22 DQS window control for Controls the mask of data strobe 3 (DQS3) DQS3 window leading and trailing edge. 00: Half extended cycle for the leading and trailing edge of DQS window (maximum window) 01: Only half extended cycle for leading edge of...
Page 173 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value Burst Length Indicates the burst length of the read/write transaction. 010: 4 bursts 011: 8 bursts NOTE: 1. A burst of 4 is not allowed when user data is 64-bit while SDRAM data is 16-bit.
Page 174 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RTT bit 1 Internal Termination Resistor (RTT) bit 1 Used together with bit 2 (RTT0) to control On- Die Termination (ODT). Combine values for (RTT1, RTT0) to select ODT settings.
Page 175 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 214. DDR_CFG8: (offset: 0x0060) Bits Type Name Description Initial Value 31:12 Reserved 11:8 DQ_GROUP1 _DELAY_SEL Data Output Delay Adjustment For Group1 (MD8 to MD15) 0x0 to 0x7: Decrease delay by 30 ps per step. 0x8: Keep DLL delay.
Page 176 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 22:20 DQS0_CD_ADJ DLL Coarse-Grain Delay Adjustment for MDQS0 0x0 to 0x3: Decrease delay by 250 ps per step. 0x4: Keep DLL master delay. 0x5 to 0x7: Increase delay by 250 ps per step.
Page 177 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value DLL_MAS_BYPASS_FD DLL Bypass Fine Grain Delay 0: Fine-grain delay code is determined by DLL. 1: Fine-grain delay code is fixed by DLL_MAS_FIXED_FD. DLL Bypass Coarse Grain Delay DLL_MAS_BYPASS_CD 0: Coarse-grain delay code is determined by DLL 1: Coarse-grain delay code is fixed by...
Page 178: Rbus Matrix And Qos Arbiter
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.16 RBUS Matrix and QoS Arbiter 2.16.1 Features  8 channel QoS Arbiter  Configurable Bandwidth and Duedate for each agent  QoS classifier can be programmed for RR, BW RR, Fixed Priority and QoS Arb 2.16.2 Block Diagram N requestors (N=8) Req#0...
Page 179: List Of Registers
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.16.3 List of Registers Offset Register Name Description Page 0x0000 DMA_ARB_CFG DMA Arbiter Configuration 0x0004 DMA_AG_BW DMA Agent Bandwidth 0x0010 OCP_CFG0 OCP Configuration0 0x0014 OCP_CFG1 OCP Configuration1 0x0024 R2P_MONITOR Rbus to Pbus Monitor 0x0028 ERR_ADDR...
Page 180: Register Descriptions ( Base : 0 X 1000_0400)
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.16.4 Register Descriptions (base: 0x1000_0400) 218. DMA_ARB_CFG: (offset: 0x0000) Bits Type Name Description Initial Value 31:27 Reserved PREEMPT_EN Preemption Enable Request preemption, higher priority requestor may change current request transaction 0: Disable Preemption 1: Enable Preemption TRTC_EN...
Page 181 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 25:24 AG_QOS_TYPE Agent QoS Type 0: Latency critical 1: Latency sensitive 2: Bandwidth sensitive (default) 3: Best Effort 23:16 AG_DUEDATE Due date for latency critical agent 0x20 (unit: system bus clock cycle - system bus is 200 MHz or 120 MHz depending...
Page 182 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RD_BYPASS_WR Read Bypass Write Enable Allows read commands to bypass write commands for OCP_IF when the address does not conflict. 0: Disable 1: Enable 221.
Page 183: Usb Host Controller & Phy
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.17 USB Host Controller & PHY 2.17.1 Features  Complies with the USB 2.0 Specifications  Complies with Host Controller Interface (OHCI) Specifications, Version 1.0a.  Supports ping and split transactions ...
Page 184: Ehci Operation Registers
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.17.4 EHCI Operation Registers (base: 0x101C.0000) 2.17.4.1 EHCI Capability Register Mnemonic Register Name Offset from EHCI AHB Slave Start Address Default Value HCCAPBASE Capability Register USBBASE + 00h (see NOTE 1) 32’h01000010 HCSPARAMS Structural Parameter...
Page 185 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.17.5 OHCI Operation Registers (base: 0x101C.1000) Offset HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRHDescriptor A HcRhDescriptor B HcRhStatus HcRhPortStatus[1] …...
Page 186 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.18 USB Device Controller 2.18.1 Features  Supports the USB 2.0 Specification (Revision 1.0a), operates in High-Speed (HS, 480 Mbps)  Supports up to 2 bulk-in and 2 bulk-out endpoints, and including control endpoint 0. ...
Page 187 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.18.4 Legacy Mode USB device core operates in legacy mode when EPOUT_AGGEN = 0. In this mode, Host driver does not need to do anything but send a non-full bulk as the end of a packet. On PDMA side, 4 bytes of PDMA_RX_INFO will be added at the beginning of received packets to indicate the actual received byte count.
Page 188 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.18.6 De-Aggregation Mode USB_TX_INFO (1 DW) PDMA_RX_INFO TX WI (2/4/8 DW) TX WI (2/4/8 DW) Tx length Tx length Tx Pkt (bytes) + Tx Pkt (bytes) + padding padding 802.11 header and 802.11 header (1/2/3...
Page 189 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.18.7 Bulk-out Aggregation Format AGG_HDR[31:0] Payload Padding AGG_HDR[31:0] Payload Padding AGG_HDR[31:0] AGG_HDR[31:0] AGG_HDR[31:16] reserved; AGG_HDR[15:0] payload_length; NOTE: Payload 1) Each aggregation frame should add padding to align with the 4-byte boundary. 2) The payload_length indicates the length of Padding payload (padding not included).
Page 190 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.18.9 PDMA Descriptor Format bit 31 bit 0 SDP0[31:0] DDONE SDL0[13:0] BURST SDL1[13:0] SDL1[31:0] Reserved EP[3:0] Reserved[23:0] [3:0] Figure 2-22 PDMA Tx Descriptor Format The following is a detailed description of each field in the PDMA TXD. 2.18.9.1 PDMA Tx Field Descriptions Name Description...
Page 191 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.18.9.2 PDMA Rx Descriptor Format bit 31 bit 0 SDP0[31:0] SDL0[13:0] DDONE BURST SDL1[13:0] SDP1[31:0] Reserved EP[3:0] Reserved[23:16] Received Byte Count [15:0] [3:0] Figure 2-23 PDMA Rx Descriptor Format The following is a detailed description of each field in the PDMA RXD.
Page 192 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.18.10 Register Descriptions (base: 0x1012_0000) 0000 H USB controller registers 0800 H UDMA registers 1000 H PDMA registers 1400 H Reserved 1FFF H Figure 2-24 USB Device Register Mapping 2.18.11 USB Device Controller Registers Refer to CAST CUSB2 Core USB2.0 function controller technical specification.
Page 193 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.18.12 UDMA Registers 224. UDMA_CTR: (offset: 0x0800, default: 0x0000_0000) Bits Type Name Description Initial Value 31:26 Reserved EPOUT1_DMAEN Enables EPOUT1 UDMA. EPOUT0_DMAEN Enables EPOUT0 UDMA. 23:18 Reserved EPOUT1_AGGEN Enables EPOUT1 UDMA De-aggregation. EPOUT0_AGGEN Enables EPOUT0 UDMA De-aggregation.
Page 194 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.18.13 PDMA Registers 2.18.13.1 List of Registers Offset Register Name Description Page 0x1000, 0x1010 TX_BASE_PTRn Tx Ring n Base Address Pointer 0x1004, 0x1014 TX_MAX_CNTn Tx Ring n Maximum Count 0x1008, 0x1018 TX_CTX_IDXn Tx Ring n CPU TXD Index...
Page 195 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.18.13.2 Register Descriptions 226. TX_BASE_PTRn: (offset: 0x1000, 0x1010) (n=0, 1) Bits Type Name Description Initial Value 31:0 TX_BASE_PTRn Tx Base Pointer n Points to the base address of TX_Ring n (4-DWORD aligned address).
Page 196 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 11:0 RX_CALC_IDXn Rx CPU RXD Index n Points to the next RXD the CPU will allocate to RXD Ring n. 233. RX_DRX_IDXn: (offset: 0x110C, 0x111C) (n=0, 1) Bits Type Name...
Page 197 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value BIG_ENDIAN Selects the Endian mode for the SoC platform section. DMA applies the endian rule to convert payload and Tx/Rx information. DMA does not apply the endian rule to registers or descriptors.
Page 198 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RST_DTX_IDX0 Reset TX_DMATX_IDX0 Resets index 0 of the Tx link table to 0. NOTE: 0: Disassert reset 1: Reset 237. DELAY_INT_CFG: (offset: 0x120C) Bits Type Name...
Page 199 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RXMAX_PTIME Rx Maximum Pending Time Specifies the maximum pending time for the internal RX_DONE_INT. When the pending time is equal to or greater than RXMAX_PTIME x 20 μs, or the number of pended RX_DONE_INT is equal to or greater than RXMAX_PCNT (see above), a final RX_DLY_INT is generated.
Page 200 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RX_DONE_INT0 Rx Queue 0 Done Interrupt Asserts when an Rx packet is received on Queue 0. 15:2 Reserved TX_DONE_INT1 Tx Queue 1 Done Interrupt Asserts when a Tx Queue 1 packet is transmitted.
Page 201 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:2 Reserved TX_DONE_INT_MSK1 Masks the Tx Queue 1 Done interrupt. This interrupt asserts when a Tx packet is transmitted on Queue 1. TX_DONE_INT_MSK0 Masks the Tx Queue 0 Done interrupt.
Page 202 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.19 Frame Engine 2.19.1 PSE Features  Wire-speed (1000 Mbps) Ethernet LAN/WAN NAT/NAPT routing  Egress rate limiting/shaping (by GDMA)  Flow control for no-packet-loss guarantee  Emulated multicast support for keep-alive (can mirror a Tx packet to CPU) ...
Page 203 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.19.4 Block Diagram SoC High-Speed Bus CPU port (Port #0) FOE entry Scatter/Gathering PDMA (Packet Processing Engine) TSO /CSO Page Switch Fabric PBus Rx Checksum / GDM (w/. PCI supported) Shaper Packet Switch PBus...
Page 204 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.19.5 PDMA FIFO-like Ring Concept Software Driver TX_Driver RX_Driver (j=0) (i=0-1) RX_CRX_IDX(j) RX_PKT #a points to non- RX_PKT #b received CPU FSD TX_CTX_IDX (i) RX_PKT #c points to non- TX_PKT #l RX_PKT #d transmitted CPU TSD...
Page 205 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.19.6 PDMA Tx Descriptor Format bit 31 bit 0 SDP0[31:0] SDL0[13:0] DDONE BURST SDL1[13:0] SDP1[31:0] VIDX FP_BMAP[7:0] UDF[4:0] SIDX[3:0] VPRI [2:0] [3:0] Figure 2-27 PDMA Tx Descriptor Format The following is a detailed description of each field in the PDMA TXD. PGMT7620_V.1.0_040503 Page 205 of 523...
Page 206 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.19.6.1 PDMA Tx Field Descriptions Name Description DWORD0 31:0 SDP0 Segment Data Pointer0 DWORD1 DDONE DMA Done: Indicates DMA has transferred the segment pointed to by this Tx descriptor. Last Segment0: Data pointed to by SDP0 is the last segment.
Page 207 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.19.7 PDMA Rx Descriptor Format bit 31 bit 0 SDP0[31:0] SDL0[13:0] DDONE BURST SDL1[13:0] SDP1[31:0] UDF[4:0] SP[2:0] CRSN[4:0] PPE_Entry[13:0] PKT_INFO[5:0] Figure 2-28 PDMA Rx Descriptor Format The following is a detailed description of each field in the PDMA RXD. PGMT7620_V.1.0_040503 Page 207 of 523...
Page 208 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.19.7.1 PDMA Rx Field Descriptions Name Description DWORD0 31:0 SDP0 Segment Data Pointer 0 for header (if HP_SEP_EN = 1) or the whole packet (if HP_SEP_EN = DWORD1 DDONE DMA Done: Indicates DMA has received the segments pointed to by this Rx descriptor.
Page 209 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.19.8 Global Registers (base: 0x1010_0000) 2.19.8.1 List of Registers Offset Register Name Description Page 0x0000 FE_GLO_CFG Frame Engine Global Configuration 0x0004 FE_RST_GLO Frame Engine Global Reset 0x0008 FE_INT_STATUS Frame Engine Interrupt Status 0x000C FE_INT_ENABLE Frame Engine Interrupt Enable...
Page 210 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.19.8.2 Register Descriptions 241. FE_GLO_CFG: Frame Engine Global Configuration (offset: 0x0000) Bits Type Name Description Initial Value 31:16 EXT_VLAN Extended VLAN protocol ID 0x8100 15:8 Reserved 0x7D L2_SPACE L2 Space (unit: 8 bytes) Reserved RATE_MINUS...
Page 211 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value PPE_CRC_DROP PPE GE1 CRC Error Dropped Packet Interrupt Asserts when the GE1 discards a packet due to CRC error. PPE_P1_FC PPE Port 1 Flow Control Asserted Interrupt Asserts when flow control is asserted on port 1 (GDMA1).
Page 212 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value CPU_FQ_EMPTY CPU PSE Free Queue Empty Threshold Reached Interrupt Asserts when the remaining buffers on the free queue are lower than the empty threshold and a forced drop condition has occurred.
Page 213 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value TSO_ILLEGAL Enables the TCP Segmentation Offload (TSO) Illegal packet interrupt. This interrupt asserts when the packet format is not supported by TSO (e.g., not TSO or IPv4/v6) but when TSO is enabled for that packet.
Page 214 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 23:16 ADD_RATE_BYTE Add Rate Byte 0x18 The number of bytes that should be added to the frame byte length while calculating the rate limit.
Page 215 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:12 LAN_TR3_FCON PDMA Tx Ring #3 Flow Control by LAN port of the switch Selects when to pause Tx ring #3. Bit[19]: When GSW LAN Q3 is full. Bit[18]: When GSW LAN Q2 is full.
Page 216 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.19.9 CPU Port Registers (base: 0x1010_0400) 2.19.9.1 List of Registers Offset Register Name Description Page 0x0000 CDM_CSG_CFG CDMA Checksum Generation Configuration 0x0010 PPPOE_SID_0001 PPPoE Session ID Index 0, 1 0x0014 PPPOE_SID_0203 PPPoE Session ID Index 2,3...
Page 217 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.19.9.2 Register Descriptions 249. CDM_CSG_CFG: CDM Checksum Generation Configuration (offset: 0x0000) Bits Type Name Description Initial Value 31:16 INS_VLAN Inserted VLAN protocol ID 0x8100 15:8 SP_RING Source Port to PDMA Ring selection Selects the source port for packets entering the PDMA Ring #1.
Page 218 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:0 PPPOE_SID8 PPPoE Session ID for SID INDEX#8 255. PPPOE_SID_1011: PPPoE Session Identification (offset: 0x0024) Bits Type Name Description Initial Value 31:16 PPPOE_SID11 PPPoE Session ID for SID INDEX#11 15:0 PPPOE_SID10...
Page 219 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 31:28 Reserved 27:16 VLAN_ID7 VLAN ID of VLAN7 15:12 Reserved 11:0 VLAN_ID6 VLAN ID of VLAN6 262. VLAN_ID_0809: VLAN Identification (offset: 0x0040) Bits Type Name Description...
Page 220 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 23:16 FQ_MAX_PCNT Maximum Free Queue Page Count 0x18 Please reset PSE after re-programming this register. 15:8 FQ_FC_RLS Free Queue Flow Control Release Page Count FQ_FC_ASRT Free Queue Flow Control Assertion Page Count 267.
Page 221 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value GDM_DROP_256B GDM Drop 256-Byte Packets A special mode to drop packets with payload > 256 bytes. 0: Drop packets according to standard Ethernet frame length limitation.
Page 222 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 13:0 GDM_TK_RATE GDM Output Shaper Token Rate Based on settings in GDM1_20US_TICK_SLT, bit[25]in the GDM_FWD_CFG register. (unit: 8 B/ms or 8 B/20 μs) PGMT7620_V.1.0_040503 Page 222 of 523...
Page 223 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.19.10 PDMA Registers (base: 0x1010_0800) 2.19.10.1 List of Registers Offset Register Name Description Page 0x0000, 0x0010, TX_BASE_PTRn Tx Ring n Base Address Pointer 0x0020, 0x0030 0x0004, 0x0014, TX_MAX_CNTn Tx Ring n Maximum Count 0x0024, 0x0034 0x0008, 0x0018, TX_CTX_IDXn...
Page 224 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.19.10.2 Register Descriptions 271. TX_BASE_PTRn: (offset: 0x0000, 0x0010, 0x0020, 0x0030) (n: 0 to 3) Bits Type Name Description Initial Value 31:0 TX_BASE_PTR Tx Base Pointer Points to the base address of TX_Ring n (4-DWORD aligned address).
Page 225 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 11:0 RX_CALC_IDX Rx CPU RXD Index Points to the next RXD the CPU will allocate to RXD Ring n. 278. RX_DRX_IDXn: (offset: 0x010C, 0x011C) (n: 0, 1) Bits Type Name...
Page 226 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value BIG_ENDIAN Selects the Endian mode. Sets the PDMA to perform byte swapping on the Tx/Rx packet header and payload. 0: Little endian 1: Big endian TX_WB_DDONE Tx Write Back DDONE Enables TX_DMA writing back DDONE into TXD.
Page 227 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RST_DTX_IDX2 Reset TX_DMATX_IDX2 Resets index 2 of the Tx link table to 0. RST_DTX_IDX1 Reset TX_DMATX_IDX1 Resets index 1 of the Tx link table to 0. RST_DTX_IDX0 Reset TX_DMATX_IDX0 Resets index 0 of the Tx link table to 0.
Page 228 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RXMAX_PTIME Rx Maximum Pending Time Specifies the maximum pending time for the internal RX_DONE_INT. When the pending time is equal to or greater than RXMAX_PTIME x 20 μs, or the number of pended RX_DONE_INT is equal to or greater than RXMAX_PCNT (see above), a final RX_DLY_INT is generated.
Page 229 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value TX_DONE_INT3 Tx Queue 3 Done Interrupt Asserts when a Tx Queue 3 packet is transmitted. TX_DONE_INT2 Tx Queue 2 Done Interrupt Asserts when a Tx Queue 2 packet is transmitted.
Page 230 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RX_DONE_INT_MSK0 Rx Queue 0 Done Interrupt Mask Masks the Rx Queue 0 Done interrupt, which indicates Rx Queue 0 has received a packet. 15:2 Reserved TX_DONE_INT_MSK3...
Page 231 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value Maximum Weight 1 29:28 MAX_WEIGHT1 Defines the auto-reload bucket size if MAX_RATE_ULMT1 is set to 1. It also serves as excess bandwidth allocation ratio for servicing queue #1.
Page 232 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value Maximum Weight 0 13:12 MAX_WEIGHT0 Defines the auto-reload bucket size if MAX_RATE_ULMT0 is set to 1. It also serves as excess bandwidth allocation ratio for servicing queue #0.
Page 233 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value Maximum Rate Limitation 3 MAX_RATE_ULMT3 0: Enables the maximum rate limitation function for queue #3. The maximum rate for queue #3 is defined by MAX_RATE3. 1: Disables the maximum rate limitation function for queue #3.
Page 234 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value Maximum Bucket Size 2 MAX_BKT_SIZE2 Defines the limited maximum rate for queue #3 if MAX_RATE_ULMT3 is 0. The value specified represents the size of the 4- byte quota to be added into the queue #1 bucket per 125 μs.
Page 235 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.19.11 MIB Counter Description (base: 0x1010_1000) Accounting, Meter and GDMA Counter Table Offset Name Description 0x000 PPE_AC_BCNT0 PPE Accounting Group #0 Byte Counter 0x004 PPE_AC_PCNT0 PPE Accounting Group #0 Packet Counter …..
Page 236 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Offset Name Description 0x378 GDM2_RX_CERCNT Received IP/TCP/UDP checksum error packet count for PPE GDM 0x37C GDM2_RX_FCCNT Received flow control pkt count for PPE GDM PGMT7620_V.1.0_040503 Page 236 of 523...
Page 237 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20 Ethernet Switch 2.20.1 Features  IEEE 802.3 full duplex flow control  5x10/100 Mbps PHY  Supports Spanning Tree port (STP) states  IEEE 802.1w Rapid Spanning Tree ...
Page 238 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.2 Block Diagram P6 (G1) Link table Data buffer Address table Link Data Address Bridge Management Management Management 5 ports FE PHY Figure 2-29 Ethernet Switch Block Diagram 2.20.3 Frame Classfication 2.20.3.1 Broadcast Frames FTAG Type...
Page 239 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.3.2 Multicast Frames FTAG Type IP4/IP6 Protocol Description The first bit of MSB is Multicast Frames 1’b1. IGMP 08-00 0x02 IGMP Message IP_MULT 01-00-5E-xx-xx-xx IP Multicast (UDP) 86-DD 0x00 Hop-by-Hop 0x3A ICMPv6 (MLDv2)
Page 240 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.3.3 Unicast Frames FTAG Type Description The 1st bit of MSB is 1’b0 Unicast Frames FF-FF-FF-FF-FF-FF 08-06 ARP Request Frames 08-06 ARP Reply Frames RARP FF-FF-FF-FF-FF-FF 80-35 RARP Request Frames 80-35 RARP Reply Frames 2.20.4 Switch L2/L3 Address Table...
Page 241 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bytes Bits Name Description LEAKY_EN Leaky VLAN Enable 1’b0: This frame address will be blocked by VLAN (default) 1’b1: This frame address can pass through VLAN NOTE: Leaky VLAN can be configured by ARL or Port Control Register based on the indication of MFC.UC_ARL_LKYV or MFC.MC_ARL_LKYV.
Page 242 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.4.2 DIP address table Bytes Bits Name Description 15:0 RESP_CNT Response Counter[15:0] A response counter for each port is used to count the number of consecutive No IGMP Report Messages received before the Response Timer counts to zero.
Page 243 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bytes Bits Name Description 15:13 EG_TAG Egress VLAN Tag Attribution 3’b000: System default (Default) 3’b001: Consistent 3’b010 to 3’b011: Reserved 3’b100: Untagg 3’b101: Swap 3’b110: Tagged 3’b111: Stack 18:16 USR_PRI User Priority from IGMP Table 0: Default...
Page 244 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.5 Virtual LAN 2.20.5.1 VLAN Table Bits Name Description VALID VLAN Entry Valid Filtering Database 3’h0: Default FID for all MAC addresses … 3’h7 15:4 S_TAG1 (1) Service Tag Identification 12-bit Service Tag ID for VLAN translation or Stack VLAN (2) Service Tag Index bit[6:4]: Port 0 STAG index...
Page 245 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Name Description 59:48 S_TAG2 (2) Service Tag Index b[50:48]: Port 4 STAG index b[53:51]: Port 5 STAG index b[56:54]: Port 6 STAG index b[59:57]: Port 7 STAG index 2.20.5.2 VLAN tagging The switch can support customer and service VLAN tags (inner/ outer VLAN tags) inside a frame.
Page 246 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.5.4 Translation port Translation Port Look-up TX_CTRL RX_CTRL PARSER Engine untagged or Untag / Consistent for untagged VID 1 VID 0 priority-tagged VID 1 PVID # CVID # Data PVID # Data Data E/L SA DA...
Page 247 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.5.6 Transparent port Transparent Port TX_CTRL RX_CTRL PARSER Look-up Engine VID 1 untagged or Untag / Consistent priority-tagged PVID # Type + Data Data Data Type + Data PVID# VID 1 VID 0 VID1...
Page 248 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.6.1 ACL Block Diagram Packet Parser (Pipe-0) Look-Up Engine (Pipe-1) Hit Flag Hit Flag Packet Parser ACL Rule Table ACL Rule Control Source Port 16-bits N-bits CTRL Header Hit Word Offset 40 39 16 15...
Page 249: Table 2-3 Rule Mask
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.6.3 ACL Rule Control Table 2-3 Rule Mask Bytes Bits Name Description 63:0 HIT_PAT Hit Pattern When a valid bit is set in this table, it means that the corresponding pattern in the rule table must be hit and necessary.
Page 250 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bytes Bits Name Description EG_TAG Egress VLAN Tag Attribution 3’b000: System Default (Disable) 3’b001: Consistent 3’b010, 3’b011: Reserved 3’b100: Untagged 3’b101: Swap 3’b110: Tagged 3’b111: Stack LKY_VLAN Leaky VLAN PPP_RM PPPoE Header Removal SA_SWAP...
Page 251: Table 2-6 Trtcm Meter Table
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Table 2-6 trTCM Meter Table Bytes Bits Name Description Intial Value 63:48 Committed Information Rate 16’h0: 0 * 64 Kbps 16’h1: 1 * 64 Kbps … 16’hFFFF: 65536* 64 Kbps NOTE: 1* 64 Kbps means that ACL will add 1 token (1-Byte) to the CBS burst bucket every 125 μs.
Page 252 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.7 ARL Registers (base: 0x1011_0000) 2.20.7.1 List of Registers Offset Register Name Description Page 0x0000 MISC1 MISC I Register 0x0004 PPE Forward Control Register 0x0008 AISR ACL Interrupt Status Register 0x000C ARL Global Control Register 0x0010...
Page 253 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 0x0090 VTCR VLAN Table Control Register 0x0094 VAWD1 VLAN and ACL Write Data-I Register 0x0098 VAWD2 VLAN and ACL Write Data-II Register 0x009C TRTCM Two Rate Three Color Mark Register 0x00A0 Address Age Control Register 0x00A4...
Page 254 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.7.2 Register Descriptions 288. MISC1: MISC I Register (offset: 0x0000) Bits Type Name Description Initial Value 31:0 Reserved 289. PFC: PPE Forward Control Register (offset: 0x0004) Bits Type Name Description Initial Value 31:4...
Page 255 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value LOCAL_EN Local Port Forwarding Enable 1'b0: Drop frames at the local port. 1'b1: Allow frame forwarding to the local port. ARL_PADDING ARL Data Padding Sets ARL to add byte padding up to 46 bytes when the length of the data field of the incoming frame is less than 46 bytes.
Page 256 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 23:16 UNM_FFP Unknown Multicast Frame Flooding Ports 0x7F If MAC receives multicast frames which can not be found on the ARL, this field indicates the flooding ports.
Page 257 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value UC_ARL_LKYV Unicast Frame ARL Leaky VLAN Enable 1’b1: Use LEAKY_EN in ARL to control the unicast frames 1’b0: Use PVC.UC_LKYV_EN in Port Control register to control the unicast frames 15:8 Reserved...
Page 258 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:8 QRY_INTL Query Interval 0x7D Together with the Robustness Variable, the Query Interval sets the age-out time for router ports automatically learned from IGMP Query frames.
Page 259 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value MLD_LKY_VLAN MLD Leaky VLAN Enable 1’b0: Disable 1’b1: Enable MLD_PRI_HIGH MLD Force the Highest Priority 1’b0: System default 1’b1: Assigned to the highest priority queue. MLD_QUE_MIR MLD Query Message to Mirror Port 1’b0: Disable...
Page 260 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value IGMP_EG_TAG IGMP Message Egress VLAN Tag Attribution 3’b000: System Default (Disable) 3’b001: Consistent 3’b010,3’b011: Reserved 3’b100: Untagged 3’b101: Swap 3’b110: Tagged 3’b111: Stack IGMP_LKY_VLAN IGMP Leaky VLAN Enable 1’b0: Disable...
Page 261 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 24:22 PPP_EG_TAG PPPoE Discovery Egress VLAN Tag Attribution 3’b000: System Default (Disable) 3’b001: Consistent 3’b010, 3’b011: Reserved 3’b100: Untagged 3’b101: Swap 3’b110: Tagged 3’b111: Stack PPP_LKY_VLAN PPPoE Discovery Leaky VLAN Enable...
Page 262 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value ARP_LKY_VLAN ARP/RARP Leaky VLAN Enable 1’b0: Disable 1’b1: Enable ARP_PRI_HIGH ARP/RARP Force the Highest Priority 1’b0: System default 1’b1: Assigned to the highest priority queue ARP_MIR ARP/RARP Mirror Port 1’b0: Disable...
Page 263 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value PAE_MIR PAE to Mirror Port 1’b0: Disable 1’b1: Frame copied to Mirror port 18:16 PAE_PORT_FW PAE TO_CPU Forwarding Ports 3’b0xx: System default (disable) 3’b100: System default and CPU port excluded 3’b101: System default and CPU port included 3’b110: CPU port only (As long as the ingress...
Page 264 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value BPDU_PORT_FW BPDU TO_CPU Forwarding 3’b0xx: System default (disable) 3’b100: System default and CPU port excluded 3’b101: System default and CPU port included 3’b110: CPU port only (As long as the ingress port is not the CPU port.
Page 265 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 18:16 R02_PORT_FW REV_02 TO_CPU Forwarding 3’b0xx: System default (disabled) 3’b100: System default and CPU port excluded 3’b101: System default and CPU port included 3’b110: CPU port only (As long as the ingress port is not the CPU port.
Page 266 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 299. RGAC2: REV_03 and REV_0E Control Register (offset: 0x002C) Bits Type Name Description Initial Value 31:28 Reserved R0E_MANG_FR REV_0E as Management Frame 1’b0: Disable 1’b1: Regarded as management frame R0E_PAE_FR REV_0E as PAE Frame 1’b0: Disable...
Page 267 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value R03_BPDU_FR REV_03 as BPDU Frame 1’b0: Disable 1’b1: Regarded as BPDU frame R03_EG_TAG REV_03 Egress VLAN Tag Attribution 3’b000: System default (disabled) 3’b001: Consistent 3’b010, 3’b011: Reserved 3’b100: Untagged 3’b101: Swap...
Page 268 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 24:22 R20_EG_TAG REV_20 Egress VLAN Tag Attribution 3’b000: System default (disabled) 3’b001: Consistent 3’b010, 3’b011: Reserved 3’b100: Untagged 3’b101: Swap 3’b110: Tagged 3’b111: Stack R20_LKY_VLAN REV_20 Leaky VLAN Enable 1’b1: Enable...
Page 269 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value R10_LKY_VLAN REV_10 Leaky VLAN Enable 1’b1: Enable 1’b0: Disable R10_PRI_HIGH REV_10 Force the Highest Priority 1’b1: Assigned to the highest priority queue 1’b0: System default R10_MIR REV_10 to Mirror Port 1’b0: Disable...
Page 270 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RUN_MIR REV_UN to Mirror Port 1’b0: Disable 1’b1: Frame copied to Mirror port 18:16 RUN_PORT_FW REV_UN TO_CPU Forwarding 3’b0xx: System default (disabled) 3’b100: System default and CPU port excluded 3’b101: System default and CPU port included 3’b110: CPU port only (As long as the ingress port is not the CPU port.
Page 271 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value R21_PORT_FW REV_21 TO_CPU Forwarding 3’b0xx: System default (disabled) 3’b100: System default and CPU port excluded 3’b101: System default and CPU port included 3’b110: CPU port only (As long as the ingress port is not the CPU port.
Page 272 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 303. PBG1: Protocol Based Group ID-I Register (offset: 0x003C) Bits Type Name Description Initial Value 31:16 TYPE1 TYPE 1 Value 0x0000 Ethernet II: Matched with EtherType RFC_1042: Matched with SNAP Type IPX Raw 802.3: “Don’t care”...
Page 273 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 10:8 QUE_CPU_0 User Priority 0 CPU Queue Selection QUE_LAN_0 User Priority 0 LAN Queue Selection DSCP_PRI_0 User Priority 0 DSCP Value 307. PEM2: User Priority Egress Mapping II Register (offset: 0x004C) Bits Type Name...
Page 274 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value QUE_LAN_6 User Priority 6 LAN Queue Selection DSCP_PRI_6 User Priority 6 DSCP Value 0x30 310. PIM1: DSCP Priority Ingress Mapping I Register (offset: 0x0058) Bits Type Name...
Page 275 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 14:12 PRI_DSCP_24 User Priority for DSCP 0b011_000 11:9 PRI_DSCP_23 User Priority for DSCP 0b010_111 PRI_DSCP_22 User Priority for DSCP 0b010_110 PRI_DSCP_21 User Priority for DSCP 0b010_101 PRI_DSCP_20 User Priority for DSCP 0b010_100 313.
Page 276 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 20:18 PRI_DSCP_56 User Priority for DSCP 0b111_000 17:15 PRI_DSCP_55 User Priority for DSCP 0b110_111 14:12 PRI_DSCP_54 User Priority for DSCP 0b110_110 11:9 PRI_DSCP_53 User Priority for DSCP 0b110_101 PRI_DSCP_52 User Priority for DSCP 0b110_100...
Page 277 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 319. ATWD: Address Table Write Data Register (offset: 0x007C) Table 2-7 Address Table Write Data Register: MAC Address Bits Type Name Description Initial Value 31:24 TIMER Age Timer MY_MAC MAC address is reserved for MY_MAC attribute 22:20 SA_PORT_FW...
Page 278 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value BUSY Address Table Is Busy SW can set this bit to 1 only if this bit is reset. After ATWD registers are written and this bit is set, this chip will perform the corresponding function according to AC_CMD, AC_SAT, and AC_MAT included in this register.
Page 279 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value AC_SAT Address Table Single Access Target Whenever MATC register is written and bit.31 is set, this chip will perform the corresponding function on the Address table based on FUNC bits.
Page 280 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 22:20 SA_PORT_FW Source Address Hit Frame Port Forwarding SA_MIR_EN Source Address Hit to Mirror Port 18:16 USER_PRI User Priority 15:13 EG_TAG Egress VLAN Tag Attribute LEAKY_EN Leaky VLAN Enable 11:4...
Page 281 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:12 FUNC Access Control Function Whenever VTCR register is written and bit.31 is set, this chip will perform the corresponding function on the VLAN table based on FUNC bits. 4’b0000: Read the specified VID Entry from VAWD# register based on VID bits 4’b0001: Write the specified VID Entry though...
Page 282 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:4 S_TAG1 Service Tag I Filtering Database VALID VLAN Entry Valid Table 2-14 VLAN and ACL Write Data-I Register: ACL Rule Table Bits Type Name Description...
Page 283 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value PRI_USER User Priority from ACL MIR_EN Frame Copy to Mirror Port PORT_FW Frame TO_CPU Forwarding NOTE: For more information on this register, see the ACL Rule Control section. Table 2-18 VLAN and ACL Write Data-I Register: trTCM Meter Table Bits Type...
Page 284 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 31:24 Reserved 23:19 ACL_CLASS_IDX ACL Class Index The ACL flow meter allows users to color code IP packet flows based on their rate. RED_DROP_G RED Engine Drop Green Sets the RED engine to drop green color...
Page 285 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 30:26 Reserved 25:16 RED_HTH RED High Threshold The highest threshold for Random Early Detection. Sets a high threshold number of packets in a queue.
Page 286 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value DHCP6_BPDU_FR DHCPv6 Discover as Bridge Protocol Data Unit (BPDU) Frame DHCP server treats DHCPv6 packets as BPDU frames. 1’b0: Non-BPDU Frame 1’b1: Regarded as BPDU frame 24:22 DHCP6_EG_TAG DHCPv6 Discovery Egress VLAN Tag Attribution...
Page 287 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value DHCP4_BPDU_FR DHCPv4 as BPDU Frame 1’b0: Non-BPDU Frame 1’b1: Regarded as BPDU frame DHCP4_EG_TAG DHCPv4 Egress VLAN Tag Attribution 3’b000: System default (disabled) 3’b001: Consistent 3’b010, 3’b011: Reserved 3’b100: Untagged...
Page 288 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 23:12 VID5 VLAN Identifier for VLAN Table Index 5 0x006 11:0 VID4 VLAN Identifier for VLAN Table Index 4 0x005 333. VTIM4: VID to Table Index Map 4 Register (offset: 0x010C) Bits Type Name...
Page 289: Table 2-25 Debug Control Register : D
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 30:26 Reserved SIM_AGE Age Timer Simulation Mode Enables simulation mode on the age timer. 1'b0: Disable 1'b1: Only the first 8 entries are used and fast age-out is performed on the age timer.
Page 290 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip DBG_ID Module DBG_CTRL Action Reserved 13:12 DATA_SEL Output Data Selection 2’b00: TBL_ACL_HIT[63:0] 2’b01: TBL_ACL_FLAG[31:0] 2’b10 to 2’b11: Reserved DP Filter Filter by Destination Port 10:6 Dest. Port Indicates Destination Port SP Filter Filter by Source Port Source Port...
Page 291 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.8 BMU Registers 2.20.8.1 List of Registers Offset Register Name Description Page 0x1000, 0x1100, 0x1200, MMSCR0_Q0Pn Max-Min Scheduler Control Register 0 of 0x1300, 0x1400, 0x1500, Queue 0/Port n 0x1600, 0x1700 0x1004, 0x1104, 0x1204, MMSCR1_Q0Pn Max-Min Scheduler Control Register 1 of...
Page 292 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 0x1038, 0x1138, 0x1238, MMSCR0_Q7Pn Max-Min Scheduler Control Register 0 of 0x1338, 0x1438, 0x1538, Queue 7/Port n 0x1638, 0x1738 0x103C, 0x113C, 0x123C, MMSCR1_Q7Pn Max-Min Scheduler Control Register 1 of 0x133C, 0x143C, 0x153C, Queue 7/Port n 0x163C, 0x173C 0x1040, 0x1140, 0x1240,...
Page 293 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.8.2 Register Descriptions 342. MMSCR0_Q0Pn: Max-Min Scheduler Control Register 0 of Queue 0/Port n (offset: 0x1000, 0x1100, 0x1200, 0x1300, 0x1400, 0x1500, 0x1600, 0x1700) Bits Type Name Description Initial Value MIN_SP_WRR_Qx_Pn Port n Queue x Minimum Traffic Arbitration Scheme...
Page 294 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 23:16 Reserved MAX_RATE_EN_Qx_Pn Port n Queue x Maximum Rate Control Enable 1’b0: Disable queue 0 max. rate limit control. When disabled, the shaper always lets packets pass.
Page 295 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 345. MMSCR1_Q1Pn: Max-Min Scheduler Control Register 1 of Queue 1/Port n (offset: 0x100C, 0x110C, 0x120C, 0x130C, 0x140C, 0x150C, 0x160C, 0x170C) Bits Type Name Description Initial Value MAX_SP_WFQ_Qx_Pn Port n Queue x Max. Traffic Arbitration Scheme 1'b0: Weighted Fair Queuing (WFQ) 1'b1: Strict Priority (SP) 30:28...
Page 296 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 347. MMSCR1_Q2Pn: Max-Min Scheduler Control Register 1 of Queue 2/Port n (offset: 0x1014, 0x1114, 0x1214, 0x1314, 0x1414, 0x1514, 0x1614, 0x1714) Bits Type Name Description Initial Value MAX_SP_WFQ_Qx_Pn Port n Queue x Max. Traffic Arbitration Scheme 1'b0: Weighted Fair Queuing (WFQ) 1'b1: Strict Priority (SP) 30:28...
Page 297 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value MIN_RATE_CTRL Mantissa part of Port n Queue x Min. Shaper 0x00 _MAN_Qx_Pn Rate Limit Control Value range: 0 to 100 349. MMSCR1_Q3Pn: Max-Min Scheduler Control Register 1 of Queue 3/Port n (offset: 0x101C, 0x111C, 0x121C, 0x131C, 0x141C, 0x151C, 0x161C, 0x171C) Bits Type...
Page 298 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 11:8 MIN_RATE_CTRL_EXP Exponent part of Port n Queue x Min. Shaper _Qx_Pn Rate Limit Control Value range: 0 to 4 Reserved MIN_RATE_CTRL_MAN Mantissa part of Port n Queue x Min. Shaper 0x00 _Qx_Pn Rate Limit Control...
Page 299 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value MIN_RATE_EN_Qx_Pn Port n Queue x Min. Rate Control Enable 1’b0: Disable queue 5 min. rate limit control. When disabled, shaper always lets the packet pass.(infinite rate) 1'b1: Enable queue 0 min.
Page 300 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value MIN_SP_WRR_Qx_Pn Port n Queue x min. traffic arbitration scheme 1'b0: Round-Robin (RR) 1'b1: Strict Priority (SP) 30:16 Reserved MIN_RATE_EN_Qx_Pn Port n Queue x min. rate control enable 1’b0: Disable queue 6 min.
Page 301 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 356. MMSCR0_Q7Pn: Max-Min Scheduler Control Register 0 of Queue 7/Port n (offset: 0x1038, 0x1138, 0x1238, 0x1338, 0x1438, 0x1538, 0x1638, 0x1738) Bits Type Name Description Initial Value MIN_SP_WRR_Qx_Pn Port n Queue x Min. Traffic Arbitration Scheme 1'b0: Round-Robin (RR) 1'b1: Strict Priority (SP) 30:16...
Page 302 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 358. ERLCR_Pn: Egress Rate Limit Control Register of Port n (offset: 0x1040, 0x1140, 0x1240, 0x1340, 0x1440, 0x1540, 0x1640, 0x1740) Bits Type Name Description Initial Value 31:16 Reserved EG_RATE_LIMIT_EN _Pn Port n Egress Rate Limit Control Enable 1’b0: Disable 1'b1: Enable egress rate limit control...
Page 303 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 11:8 IGC_RATE_EXP_Pn Exponent part of Port n Ingress Rate Limit Control Value range: 0 to 4 ‘d0: 1 kbps ‘d1: 10 kbps ‘d2: 100 kbps ‘d3: 1 Mbps ‘d4: 10 Mbps Reserved...
Page 304 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 31:25 Reserved 24:16 EPC_QUE5 Egress Page Count at Queue 5 Indicates the page count at egress queue 5. NOTE: Only the CPU port is supported. 15:9 Reserved EPC_QUE4...
Page 305 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 25:16 MIN_FREE_PL_CNT Minimal Free Page Link Count in LMU from last 0x1E8 read access 15:10 Reserved FREE_PL_CNT Free Page Link Count in LMU. 0x1E8 367.
Page 306 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value FC_BLK_THD_Q1 Tx Queue 1 Block Threshold For Flow Control FC_BLK_THD_Q0 Tx Queue 0 Block Threshold For Flow Control NOTE: Current associated port will start the flow control mechanism (or discard when flow control scheme is disabled) if the following conditions (a) &&...
Page 307 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value IGC_MFRM_EX Ingress Rate Excludes Management Frames Management frames will be ignored by rate limit. 1’b0: Management frame included 1’b1: Management frame excluded NOTE: Management frame type is set by ARL registers.
Page 308 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.9 PORT Registers 2.20.9.1 List of Registers Offset Name Description Page 0x2000, 0x2100, 0x2200, 0x2300, STP State Control Register 0x2400, 0x2500, 0x2600, 0x2700 0x2004, 0x2104, 0x2204, 0x2304, Port Control Register 0x2404, 0x2504, 0x2604, 0x2704 0x2008, 0x2108, 0x2208, 0x2308, Port IGMP Control Register...
Page 309 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.9.2 Register Descriptions 373. SSC: STP State Control Register (offset: 0x2000, 0x2100, 0x2200, 0x2300, 0x2400, 0x2500, 0x2600, 0x2700) Bits Type Name Description Initial Value 31:16 Reserved 15:14 FID7_PST (Rapid) Spanning Tree Protocol Port State 13:12 FID6_PST (Rapid) Spanning Tree Protocol Port State...
Page 310 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value UP2DSCP_EN User Priority To DSCP Enable Replaces DSCP according to user priority. 0: Disable 1: Enable UP2TAG_EN User Priority To Tag Enable Replace 802.Q priority by user priority 0: Disable 1: Enable ACL_EN...
Page 311 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value PORT_VLAN Port-based VLAN Mechanism Select 2’b00: Port Matrix Mode Frames are forwarded by the Port Matrix Member. 2’b01: Fallback Mode Forward received frames with ingress ports that do not belong to the VLAN member.
Page 312 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:14 ROBUST_VAR Robustness Variable Defines the number of times an IGMP report message may be lost consecutively. 0: Unlimited (No Age out) 1: One time 2: Two times (default) 3: Three times MLD _HW_LEAVE...
Page 313 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value IGMP3_JOIN_EN IGMP v3 HW Join Enable Enables HW IGMP snooping. Group Address will be learned and filled in the ADDR Table automatically for the specific Record Type – IS_EX(), TO_EX().
Page 314 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 376. PSC: Port Security Control Register (offset: 0x200C, 0x210C, 0x220C, 0x230C, 0x240C, 0x250C, 0x260C, 0x270C) Bits Type Name Description Initial Value 31:20 SA_LRN_CNT Learned Source Address Number 19:8 MAX_SA_LRN Rx SA Allowable Learning Number 0xFFF Sets the maximum number of SA learned...
Page 315 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 377. PVC: Port VLAN Control Register (offset: 0x2010, 0x2110, 0x2210, 0x2310, 0x2410, 0x2510, 0x2610, 0x2710) Bits Type Name Description Initial Value 31:16 STAG_VPID Stack Tag VPID (VLAN Protocol ID) Value 0x8100 The received frame will be regarded as a legal stack tag frame if the following conditions are...
Page 316 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value MC_LKYV_EN Multicast Leaky VLAN Enable 1’b0: Multicast frames received by this port will be blocked by VLAN. 1’b1: Multicast frames received by this port can pass through VLAN.
Page 317 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 31:29 G3_PORT_PRI Group 3 Port Priority (optional) The Group 3 Priority for per port according to IEEE 802.1Q definition. Reserved 27:16 G3_PORT_VID Group 3 Port VLAN ID (optional) The Group 3 VID for per port according to IEEE 802.1Q definition.
Page 318 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value STORM_10M 10 Mbps Broadcast Storm Rate Limit Control The broadcast storm rate limit for 10 Mbps link speed. 8’h0: (0* STORM_UNIT) packets or bps 8’h1: (1 * STORM_UNIT) packets or bps …...
Page 319 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value IP6_PPE_UC IPv6 Learned UC Frame to PPE Forwarding Forwards IPv6 learned UC frames to the PPE port instead of the CPU port. IP6_PPE_BC IPv6 Broadcast Frame to PPE Forwarding Forwards IPv6 broadcast frames to the PPE port instead of the CPU port.
Page 320 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.10 MAC Registers 2.20.10.1 List of Registers Offset Name Description Page 0x3000, 0x3100, PMCR_Pn Port n MAC Control Register 0x3200, 0x3300, 0x3400, 0x3500, 0x3600, 0x3700 0x3004, 0x3104, PMEEECR_Pn Port n MAC EEE Control Register 0x3204, 0x3304, 0x3404, 0x3504, 0x3604, 0x3704...
Page 321 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.10.2 Register Descriptions 386. PMCR_Pn: Port n MAC Control Register (offset: 0x3000, 0x3100, 0x3200, 0x3300, 0x3400, 0x3500, 0x3600, 0x3700) Bits Type Name Description Initial Value 31:20 Reserved 19:18 IPG_CFG_Pn Port n Inter-Frame Gap (IFG) Shrink For CPU Port: 2’b00: Normal 96-bit IFG...
Page 322 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value BACKPR_EN_Pn Port n Back Pressure Enable Enables the back pressure mechanism when operating in half-duplex mode and internal resources are low. 1’b0: Disable 1’b1: Enable FORCE_EEE1G_Pn Port n Force LPI Mode For 1000 Mbps...
Page 323 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value FORCE_LNK_Pn Port n Force MAC Link Up When (FORCE_MODE_PN = 1), this bit is used to control link status of port n. 1’b0: Link down 1’b1: Link up 387.
Page 324 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value EEE100_STS_Pn Port n LPI Status Mode For 100 Mbps Indicates if capable of entering EEE Low Power Idle mode for 100 Mbps link speed. 1’b0: Not capable 1’b1: Capable RX_FC_STS_Pn...
Page 325 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value TX_GPAGE_TOUT_INT TX_CTRL Get Page Timeout Interrupt Enable TX_RDPB_TOUT_INT _EN TX_CTRL RD_PB Timeout Interrupt Enable TX_DEQ_TOUT_INT_EN TX_CTRL DEQ Timeout Interrupt Enable Reserved RX_AFF_FULL_INT_EN RX_CTRL Agent FIFO Full Interrupt Enable RX_ARL_TOUT_INT_EN RX_CTRL ARL Timeout Interrupt Enable RX_WRPB_TOUT_INT...
Page 326 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 391. GMACCR: Global MAC Control Register (offset: 0x3FE0) Bits Type Name Description Initial Value 31:18 Reserved PRMBL_LMT_EN Preamble Limit Enable 1’b0: RXMAC can recognize the Start Frame Delimiter (SFD), without needing to receive a byte with the value of 55 in the preamble.
Page 327 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:0 SYS_MAC_ADDR1 System MAC Address, SYS_MAC [47:32] 0x0000 The second 16-bit of system MAC address. It is unique and specified for pause frame. 394.
Page 328 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value PC6_INT_EN Port Controller 6 Interrupt Enable PC5_INT_EN Port Controller 5 Interrupt Enable PC4_INT_EN Port Controller 4 Interrupt Enable PC3_INT_EN Port Controller 3 Interrupt Enable PC2_INT_EN Port Controller 2 Interrupt Enable PC1_INT_EN...
Page 329 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.11 MIB Registers 2.20.11.1 List of Registers Offset Name Description Page 0x4000, 0x4100, 0x4200, 0x4300, ESRn Event Status Register of Port n 0x4400, 0x4500, 0x4600, 0x4700 0x4004, 0x4104, 0x4204, 0x4304, IntSn Interrupt Status Register of Port n 0x4404, 0x4504, 0x4604, 0x4704...
Page 330 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.11.2 Register Descriptions 397. ESRn: Event Status Register of Port n (offset: 0x4000, 0x4100, 0x4200, 0x4300, 0x4400, 0x4500, 0x4600, 0x4700) Bits Type Name Description Initial Value 31:26 Reserved TX_PAUSE_EVENT Tx Pause Event Indicates a pause frame transmitted without any error.
Page 331 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RX_ JABB_ERR_CNT Rx Jumbo Frame Error Count Counts frame received that were longer than MAX_RX_PKT_LEN (default 1518) octets (excluding framing bits, but including FCS octets), and had either a bad Frame Check Sequence (FCS) with an integral number of octets (FCS Error) or a bad FCS with a non-...
Page 332 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RX_ UCAST_CNT Rx Unicast Frame Counts the unicast frame with length between 64 bytes and the maximum frame size, received without any error. Includes MAC control frames.
Page 333 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value INT_RX_BOCT_CNT Rx Bad Octets Collision Count Interrupt Asserts when RX_BOCT_CNT reaches the total threshold level. INT_RX_GOCT_CNT Rx Good Octets Collision Count Interrupt Asserts when RX_GOCT_CNT reaches the total threshold level.
Page 334 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 400. TGPCn: Tx Packet Counter of Port n (offset: 0x4010, 0x4110, 0x4210, 0x4310, 0x4410, 0x4510, 0x4610, 0x4710) Bits Type Name Description Initial Value 31:16 TX_BAD_CNT Tx Bad Frames Count 0x0000 Counts the number of frames transmitted with collision.
Page 335 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 405. RBOCn: Rx Bad Octet Counter of Port n (offset: 0x4024, 0x4124, 0x4224, 0x4324, 0x4424, 0x4524, 0x4624, 0x4724) Bits Type Name Description Initial Value 31:0 RX_BOCT_CNT Rx Bad Octets Error Count 0x0000 Counts the number of good bytes of data _0000...
Page 336 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 22:16 MIB_INT_MASK MIB Interrupt Mask for each port 0x00 0: Unmask 1: Mask 15:12 Reserved 11:8 ARL_CNT_EN ARL Event Counter Enable 0: Disable 1: Enable Reserved ARL_CNT_MASK...
Page 337 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value INT_AE0CNT ACL Event 0 Counter Interrupt Asserts when AE0CNT reaches the total threshold level. NOTE: Read Write 0: Interrupt not asserted. 1: Clear the interrupt 1: Interrupt asserted NOTE: 1.
Page 338 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.12 GSW Configuration Registers 2.20.12.1 List of Registers Offset Register Name Description Page 0x7000 PPSC PHY Polling and SMI Master Control 0x7004 PIAC PHY Indirect Access Control 0x7008 Interrupt Mask Register 0x700C Interrupt Status Register 0x7010...
Page 339 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.12.2 Register Descriptions 413. PPSC: PHY Polling & SMI Master Control (offset: 0x7000) Bits Type Name Description Initial Value PHY_AP_EN PHY Auto Polling Enable Enables PHY status updates to the PHY status registers by the PHY auto-polling process.
Page 340 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 414. PIAC: PHY Indirect Access Control (offset: 0x7004) Bits Type Name Description Initial Value PHY_ACS_ST PHY Access Start Starts indirect access to the PHY register. When PHY register access is complete, this bit is self- cleared to 0.
Page 341 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 27:26 Reserved MIB_INT MIB Interrupt Asserts when a bit status is set in the IntSn and AEISR registers. It only can be reset after CPU read-clears the corresponding register.
Page 342 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value P4_LINK_CHG Port 4 Link Status Change interrupt P3_LINK_CHG Port 3 Link Status Change interrupt P2_LINK_CHG Port 2 Link Status Change interrupt P1_LINK_CHG Port 1 Link Status Change interrupt P0_LINK_CHG Port 0 Link Status Change interrupt NOTE: Where applicable,...
Page 343 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value FEQUE_XFC Enable Per-Queue Flow Control on FE PDMA The individual PDMA Tx Ring of the frame engine can be paused due to the egress queue congestion on the embedded switch.
Page 344 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 12:8 LED_POLAR LED Polarity Ports 0 to 4 LED polarity control. 1'b0: LED Pin is low active 1'b1: LED Pin is high active Reserved TMII_FREQ TMII Frequency Selection...
Page 345 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip DBG_PROBE_SEL[9:0] Internal Probe Signals 4’h0 to 4’hF Pn MAC 3’h0 to 3’h6 4’h0 to 4’hF Pn Port Ctrl (port select) 4’h0 to 4’hF Pn Scheduler 4’h0 to 4’hF Reserved 6’h00 to 6’h3F 7’h00 to 7’h7F BMU (See NOTE below)
Page 346 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value TMII_MODE TMII Mode Switch to Turbo MII interface. TX_CLK_MODE P4 Tx Clock Control 0: HP mode (clock and data are in-phase) 1: 3Com mode (clock and data is 90 degree offset) RX_CLK_MODE P4 Rx Clock Control...
Page 347 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.13 MDIO Control 2.20.13.1 IntPHY and ExtPHY address for MDIO Ethernet Switch includes an internal 5-port EPHY and a 1 or 2 RGMII interface for the external EPHY modules. All EPHY can be accessed by a 2-wire MDC/MDIO serial management interface.
Page 348 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip MDIO[addr] 1. MDIO[addr] > GPC1.PHY_BASE + 4 MDIO[addr] ExtPHY5 2. MDIO[addr] < GPC1.PHY_BASE + 0 1. MDIO[addr] > GPC1.PHY_BASE + 4 MDIO[addr] ExtPHY4 2. MDIO[addr] < GPC1.PHY_BASE + 0 MDIO[data] NOTE: ExtPHY5 address must be equal to (ExtPHY4 +1) 1.
Page 349 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.13.2 MDIO Register These registers can be accessed by PIAC (PHY Indirect Access Control) indirectly. Among them, PHY register 0-1 and 4-6 are unique for each port. PHY register 2-3 are common for all 5 ports. Legend: SC: Self-clearing, RC: Read-clearing LL: Latching Low, LH: Latching High...
Page 350 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.20.13.4 Register Descriptions 421. MII Control Register, CR Address: 00(d00), Reset State: 3100 Bits Type Name Description Default MR_MAIN _RESET Resets all digital logic, except PHY_REG. 1’h0 0: Normal 1: Reset LOOPBACK_MII MII loopback...
Page 351 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Default Autoneg Ability Indicates the availablility of the PHY auto- 1’h1 negotiation capability. 0: PHY cannot auto-negotiate. 1: PHY can auto-negotiate. Link Status Indicates link status. 1’h0 0: Down 1: Up...
Page 352 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Default 100 Base-TX Half Duplex 0: Not Capable 1’h1 Capable 1: Capable of Half Duplex 10 Base-T Full Duplex 0: Not Capable 1’h1 Capable 1: Capable of Full Duplex 10BASE-T 10 Base-T Half Duplex 0: Not Capable 1’h1...
Page 353 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Default MR_NP_ABLE Indicates that the local device supports next 1’h0 paging. 0: Not supported 1: Supported Page Received Indicates that a new page has been received. 1’h0 0: Not received 1: Received...
Page 354 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.21 PCI/PCIe Controller PCI Express Controller  Supports both RC(PCI-PCI bridge) and Endpoint mode  Support PCIe Gen1 X1 lane  Support maximum one external PCI Express endpoint when RC mode ...
Page 355 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.21.1 Block Diagram 2.21.1.1 Host bridge with PCIe Slot AP Mode (as a standalone SoC) RBus EPHYx5 FEx4 Host 4FE+2GE 5FE+1GE PDMA GEx2 RGMIIx2 GE PHYx2 MIPS BAR1 5 GHz BUS0 PCIe PDMA...
Page 356 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.21.2 PCIe Controller Acting as a PCIe Device For example, as shown in the following figure, MT7620 works as an intelligent NIC to offload the external third party SoC by performing wireless and Ethernet packet format conversion functions. NOTE: 1.
Page 357 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.21.3 Block Diagram RTRGT1 Rbus1 XP_ETG2RB XP_ETG XALI1 Pbus ELBI ELBI2PB INT_VEC RX_FIFO XP_INT PDMA TX_FIFO XALI0 XP_RB2RQT DWC_PCIE RCPL PCIe Link PCIE_RC_MODE XP_PIO_MA PBus1 XP_CSR PB2DBI DEBUG_SIGNAL XP_DBG UTIF0 XP_UTIF SRAM for...
Page 358 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.21.4 PCI/PCIe Master Access In Host Mode For PCI/PCIe Memory space access, there are two approaches. One approach is fixed mapping the address space from 32’h2000_0000 to 32’h2FFF_FFFF (256 MByte). The other apprach is PCI memory space programmable mapping which is supported via the membase register + memwin offset.
Page 359 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.21.5 PCIe Controller Host Mode Initializaton Example 1. Set the PCIRST bit in PCICFG register to assert reset the PCI device card, then reset the PCIRST bit to de- assert the reset output.
Page 360 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.21.6.2 Register Descriptions 428. PCICFG: PCI Configuration and Status Register (offset: 0x0000) Bits Type Name Description Initial Value 31:24 Reserved 23:20 P2P_BR_DEVNUM1 Device number setting of Virtual PCI-PCI bridge 19:16 P2P_BR_DEVNUM0 Device number setting of Virtual PCI-PCI bridge...
Page 361 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 431. CFGADDR: CONFIG_ADDR Register (offset: 0x0020) Bits Type Name Description Initial Value 31:28 Reserved 27:24 EXTREGNUM Extent Register Number only available for PCIe 23:16 BUSNUM Bus Number 15:11 DEVICENUM Device Number 10:8 FUNNUM...
Page 362 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 435. PHY0_CFG: PCIe PHY0 Control Register via SPI Configuration (offset: 0x0090) Bits Type Name Description Initial Value SPI_BUSY SPI Busy Status 0: Idle 1: Busy 30:24 Reserved SPI_WR SPI Write Sets the SPI transfer to read or write.
Page 363 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.21.7 PCIe0 RC Control Registers (base: 0x1014_2000) 2.21.7.1 List of Registers Offset Register Name Description Page 0x0010 PCIE0_BAR0SETUP Setup for BAR0 of PCIe Controller 0x0014 PCIE0_BAR1SETUP Setup for BAR1 of PCIe Controller 0x0018 PCIE0_IMBASEBAR0 Internal Memory Base address for BAR0 Space of...
Page 364 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.21.7.2 Register Descriptions 436. PCIE0_BAR0SETUP: Setup for BAR0 of PCIe Controller (offset: 0x0010) Bits Type Name Description Initial Value 31:16 BAR0MSK Mask Setup for Base Address Register BAR0 0x1ff 0: The corresponding address bit will be used for address comparison to determine an address hit.
Page 365 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 437. PCIE0_BAR1SETUP: Setup for BAR1 of PCIe Controller (offset: 0x0014) Bits Type Name Description Initial Value 31:16 BAR1MSK Mask Setup for Base Address Register BAR1 0: The corresponding address bit will be used for address comparison to determine an address hit.
Page 366 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 438. PCIE0_IMBASEBAR0: Internal Memory Base address for BAR0 Space of PCIe Controller (offset: 0x0018) Bits Type Name Description Initial Value 31:16 IMBASEBAR0 Internal Memory Base address for BAR0 This register is used when CHIP behaves as a PCI Express RC.
Page 367 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 444. ECRC: Error Counter Register (offset: 0x0064) Bits Type Name Description Initial Value 31:0 ECRC_ERR_CNT ECRC Error Counter Records how many times an ECRC error occurred. 2.21.8 Memory Windows Registers (base: 0x1015_0000) 445.
Page 368 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22 802.11n 2T2R MAC/BBP 2.22.1 Features  1x1/1x2/2x1/2x2 modes  300 MHz PHY Rate Support  Legacy and high throughput modes  20 MHz/40 MHz bandwidth  Reverse direction data flow and frame aggregation ...
Page 369 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.3 802.11n 2T2R MAC/BBP Register Map 0000h Reserved (200h) 0200h SCH/DMA register (200h) Distributed 0400h SYS/PBF/FCE/MISC register (400h) register 0800h Reserved (800h) 1000h MAC register (800h) 1800h SRAM (2 KB) MAC search table (800h) 2000h SRAM (8 KB)
Page 370 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.4 SCH/WPDMA Registers (base: 0x1018_0000) 2.22.4.1 List of Registers Offset Register Name Description Page 0x0200 INT_STATUS Interrupt Status 0x0204 INT_MASK Interrupt Mask 0x0208 WPDMA_GLO_CFG WPDMA Global Configuration 0x020C WPDMA_RST_IDX WPDMA Reset Index 0x0210 DELAY_INT_CFG...
Page 371 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.4.2 Register Descriptions 447. INT_STATUS: (offset: 0x0200) Bits Type Name Description Initial Value 31:21 Reserved RADAR_INT Baseband Radar Interrupt Asserts when the BBP has detected radar tones. 19:18 Reserved TX_COHERENT Tx Coherent Interrupt Asserts when the Tx DMA is ready to handle a...
Page 372 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value TX_DONE_INT4 Tx Queue 4 Done Interrupt Asserts when a Tx Queue 4 packet is transmitted. TX_DONE_INT3 Tx Queue 3 Done Interrupt Asserts when a Tx Queue 3 packet is transmitted.
Page 373 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RX_COHERENT_EN Enables the Rx Coherent interrupt. This interrupt asserts when the Rx DMA is ready to handle a queue, but cannot access the queue because the driver is not ready.
Page 374 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value TX_DONE_INT_MSK 0 Masks the Tx Queue 0 Done interrupt. This interrupt asserts when Tx Queue 0 has transmitted a packet. RX_DONE_INT_MSK Masks the Rx Done interrupt. This interrupt asserts a packet is received.
Page 375 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RX_DMA_BUSY Rx DMA Busy Indicates the busy status of the Rx DMA. 0: Not busy. 1: Busy. RX_DMA_EN Rx DMA Enable Enables the Rx DMA. When disabled, RX_DMA finishes processing the current received packet, then stops.
Page 376 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 451. DELAY_INT_CFG: (offset: 0x0210) Bits Type Name Description Initial Value TXDLY_INT_EN Tx Delay Interrrupt Enable Enables the Tx delayed interrupt mechanism. 0: Disable 1: Enable 30:24 TXMAX_PINT Tx Maximum Pending Interrupts Sets the maximum pended interrupts.
Page 377 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 452. WMM_AIFSN_CFG: (offset: 0x0214) Bits Type Name Description Initial Value 31:16 Reserved 15:12 AIFSN3 AIFSN for Access Category 3 The arbitration inter-frame spacing number which specifies the channel idle period after which a back-off occurs in AC3.
Page 378 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value CW_MIN1 CWmin for Access Category 1 The minimum contention window from which the back-off timer value is derived in AC1. CW_MIN1 AC1 CWmin = 2 0: 1 1: 2 2: 4, and so on...
Page 379 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value CW_MAX0 CWmax for Access Category 0 The maximum contention window which specifies maximum value for the back-off timer in AC0. CW_MAX0 AC0 CWmax = 2 0: 1 1: 2 2: 4, and so on...
Page 380 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 459. TX_CTX_IDX_n: (offset: 0x0238, 0x0248, 0x0258, 0x0268, 0x0278, 0x0288) (n: 0 to 5) Bits Type Name Description Initial Value 31:12 Reserved 11:0 TX_CTX_IDXn Tx CPU TXD Index n Points to the next TXD to be used by the CPU. 460.
Page 381 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 465. US_CYC_CNT: (offset: 0x02A4) Bits Type Name Description Initial Value 31:25 Reserved TEST_EN Enables test mode. 0: Disable 1: Enable 23:16 TEST_SEL Selects test mode. 0xf0 15:9 Reserved BT_MODE_EN Enables Bluetooth mode.
Page 382 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.5 PBF Registers (base: 0x1018_0000) 2.22.5.1 List of Registers Offset Register Name Description Page 0x0400 SYS_CTRL System Control 0x0404 HOST_CMD Host Command 0x0408 PBF_CFG Packet Buffer Configuration 0x040C MAX_PCNT Maximum Packet Count 0x0410 BUF_CTRL...
Page 383 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.5.2 Register Descriptions 466. SYS_CTRL: (offset: 0x0400) Bits Type Name Description Initial Value 31:20 Reserved SHR_MSEL Shared Memory Select Sets access to shared memory. 0: Map address 0x4000 – 0x7FFF to the lower 16 KB of shared memory.
Page 384 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value PBF_RESET Resets the PBF hardware. MAC_RESET Resets the MAC hardware. DMA_RESET Resets the DMA hardware. MCU_RESET Resets the MCU hardware. This bit is auto-cleared after several clock cycles.
Page 385 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value TX2Q_MODE Tx2Q Operation Mode 0: Auto mode 1: Manual mode RX0Q_MODE Rx0Q Operation Mode 0: Auto mode 1: Manual mode HCCA_MODE HCCA Auto Mode Enables HCCA Auto mode.
Page 386 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value READ_TX1Q Manually reads Tx1Q. READ_TX2Q Manually reads Tx2Q. READ_RX0Q Manually reads Rx0Q. 471. MCU_INT_STA: (offset: 0x0414) Bits Type Name Description Initial Value 31:28 Reserved MAC_INT_11 MAC interrupt 11: Reserved...
Page 387 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value DTX0_INT DMA Tx Queue 0 Interrupt Asserts when frame transfer from the DMA to TX0Q is complete. DTX1_INT DMA Tx Queue1 Interrupt Asserts when frame transfer from the DMA to TX1Q is complete.
Page 388 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value MAC_INT8_EN Enables MAC Interrupt 8: Rx QoS CF-Poll Interrupt. This interrupt asserts after receiving a QoS Data (+) CF-Poll frame. MAC_INT7_EN Enables MAC interrupt 7. MAC_INT6_EN Enables MAC interrupt 6.
Page 389 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value N1TX_INT_EN Enables the Null 1 Frame Tx Interrupt. This interrupt asserts when NULL1 frame Tx is complete. BCNTX_INT_EN Enables the Beacon Frame Tx Interrupt. This interrupt asserts when Beacon frame Tx is complete.
Page 390 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:0 RX0Q_IO RX0Q IO port. This register is used in manual mode. 477. BCN_OFFSET0: (offset: 0x042C) Bits Type Name Description Initial Value 31:24 BCN3_OFFSET Beacon 3 address offset in shared memory.
Page 391 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 480. TXRXQ_PCNT: (offset: 0x0438) Bits Type Name Description Initial Value 31:24 RX0Q_PCNT Page count in RxQ 23:16 TX2Q_PCNT Page count in Tx2Q 15:8 TX1Q_PCNT Page count in Tx1Q TX0Q_PCNT Page count in Tx0Q 481.
Page 392 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.6 RF TEST Registers (base: 0x1018_0000) 2.22.6.1 List of Registers Offset Register Name Description Page 0x0500 RF_CFG Radio Frequency (RF) Configuration 0x0504 Reserved 0x0560 2.22.6.2 Register Descriptions 483. RF_CFG: (offset: 0x0500) Bits Type Name...
Page 393 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.7 MAC Registers (base: 0x1018_0000) 2.22.7.1 List of Registers Offset Register Name Description Page 0x1000 ASIC_VER_ID ASIC Verification ID 0x1004 MAC_SYS_CTRL MAC System Control 0x1008 MAC_ADDR_DW0 MAC Address DWORD 0 0x100C MAC_ADDR_DW1 MAC Address DWORD 1...
Page 394 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.7.2 Register Descriptions 485. ASIC_VER_ID: (offset: 0x1000) Bits Type Name Description Initial Value 31:16 VER_ID ASIC version ID 0x5390 15:0 Reserved 486. MAC_SYS_CTRL: (offset: 0x1004) Bits Type Name Description Initial Value 31:15 Reserved...
Page 395 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value MAC_SRST MAC Soft-Reset 0: MAC in normal state 1: MAC in reset state NOTE: 1. MAC registers and tables are NOT reset. 2. MAC hard-reset is outside the scope of MAC registers.
Page 396 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 490. MAC_BSSID_DW1: (offset: 0x1014) Bits Type Name Description Initial Value 31:27 Reserved 26:24 MULTI_BSSID Multiple BSSID Index Byte Selection _BYTE_SEL (only for New BSSID mode) 0: Use MAC address byte0.bit[5:2] as BSSID index 1: Use MAC address byte1.bit[3:0] as BSSID index...
Page 397 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value NEW_MULTI New Multiple BSSID Mode _BSSID_MODE 0: Disable. Use MAC address Byte5 to distinguish different BSSID. 1: Enable. Use MAC address Byte0.bit[5:0] as local administration bit for multiple BSSID addresses, as follows.
Page 398 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value BSSID_4 BSSID byte4 NOTE: RXINFO bit17 is extension BSS_INDEX bit 3, it is used together with RXWI BSS_INDEX bit2:bit0 to represent 16 multiple BSS. 491.
Page 399 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value BBP_CSR_KICK Baseband Control Status Register Kick Read this bit to find the status of BBP read/write operations, or write to this bit to start read/writes to the BBP register.
Page 400 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RF_DUR RF Duration Gap between BB_CONTROL_RF and RF_LE 0: 3 system clock cycle (37.5 usec) 1: 5 system clock cycle (62.5 usec) 23:0 RF_REG_1 RF register1 ID and contents 495.
Page 401 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 497. AMPDU_MAX_LEN_20M1S: (offset: 0x1030) Bits Type Name Description Initial Value 31:28 AMPDU_MAX_BW20_MCS7 Maximum A-MPDU for BW=20 MHz, MCS 27:24 AMPDU_MAX_BW20_MCS6 Maximum A-MPDU for BW=20 MHz, MCS 23:20 AMPDU_MAX_BW20_MCS5 Maximum A-MPDU for BW=20 MHz, MCS 19:16 AMPDU_MAX_BW20_MCS4 Maximum A-MPDU for BW=20 MHz, MCS...
Page 402 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 1: Per MCS maximum A-MPDU length = 2^(AMPDU_MAX – 5) bytes. For example, set to 15 means the maximum A-MPDU length is 1024 KB. 2. The maximum AMPDU length depends on either the maximum AMPDU length set in this register or the maximum length set by 0x1018 MAX_PSDU_LEN.
Page 403 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 07:04 AMPDU_MAX_BW40_MCS9 Maximum A-MPDU for BW=40 MHz, MCS 03:00 AMPDU_MAX_BW40_MCS8 Maximum A-MPDU for BW=40 MHz, MCS NOTE: 1: Per MCS maximum A-MPDU length = 2^(AMPDU_MAX – 5) bytes. For example, set to 15 means the maximum A-MPDU length is 1024 KB 2.
Page 404 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 504. TX_WCID_DROP_MASK2: Tx Wireless Client ID Drop Mask 2 (offset: 0x1074, default: 0x0000_0000) Bits Type Name Description Initial Value 31:0 TX_WCID_DROP_ Drops the Tx frame with the specified WCID. 0x0000_0000 MASK64-95 0: WCID64...
Page 405 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 31:0 TX_WCID_DROP_ Drops the Tx frame with the specified WCID. 0x0000_0000 MASK192-223 0: WCID192 1: WCID193 … 31: WCID223 0: Disable 1: Enable 509.
Page 406 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value APC_BSSID0_4 AP client BSSID0 byte4 0x00 513. AP_CLIENT_BSSID1_L: AP Client Base Station ID 1 Low (offset: 0x1098, default: 0x0000_0000) Bits Type Name Description Initial Value 31:24 APC_BSSID1_3...
Page 407 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 31:24 APC_BSSID4_3 AP client BSSID4 byte3 0x00 23:16 APC_BSSID4_2 AP client BSSID4 byte2 0x00 15:8 APC_BSSID4_1 AP client BSSID4 byte1 0x00 APC_BSSID4_0 AP client BSSID4 byte0 0x00 520.
Page 408 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:8 APC_BSSID7_1 AP client BSSID7 byte1 0x00 APC_BSSID7_0 AP client BSSID7 byte0 0x00 526. AP_CLIENT_BSSID7_H: AP Client Base Station ID 7 High (offset: 0x10CC, default: 0x0000_0000) Bits Type Name...
Page 409 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.8 MAC Timing Control Registers (base: 0x1018_0000) 2.22.8.1 List of Registers Offset Register Name Description Page 0x1100 XIFS_TIME_CFG Inter-Frame Space Time Configuration 0x1104 BKOFF_SLOT_CFG Back-off Slot Configuration 0x1108 NAV_TIME_CFG Network Allocation Vector Time Configuration 0x110C CH_TIME_CFG...
Page 410 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.8.2 Register Descriptions 529. XIFS_TIME_CFG: (offset: 0x1100) Bits Type Name Description Initial Value 31:30 Reserved BB_RXEND_EN Enables the BB_RX_END signal. Starts deferring the Short Inter-Frame Space (SIFS) from the BB_RX_END signal from the BBP Rx logic circuit.
Page 411 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value SLOT_TIME Slot Time 0x14 This value specifies the slot boundary after deferring SIFS time. NOTE: Default 20 μs is for 11b/g. 11a and 11g- short-slot-mode is 9 μs.
Page 412 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 533. PBF_LIFE_TIMER: (offset: 0x1110) Bits Type Name Description Initial Value 31:0 PBF_LIFE_TIMER Reads the current time value of the Tx/Rx MPDU timestamp timer (always in free run mode) (unit: 1 μs) 534.
Page 413 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:0 BCN_INTVAL Beacon Interval 0x640 This value specifies the interval between Beacon frames. The maximum Beacon interval is approx. 4 sec. The minimum is approx. 100 msec.
Page 414 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 538. TBTT_TIMER: (offset: 0x1124) Bits Type Name Description Initial Value 31:17 Reserved 16:0 TBTT_TIMER TBTT Timer Shows the time remaining on the TBTT timer as it counts down to the TBTT. 0: The timer is disabled and stays at 0.
Page 415 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 543. EXT_CH_BUSY_STA: (offset: 0x1138) Bits Type Name Description Initial Value 31:0 EXT_CH_BUSY_TIME Extension Channel Busy Time (unit: μs) 544. BBP_IPI_TIMER: (offset: 0x113C) Bits Type Name Description Initial Value 31:17 Reserved BBP_IPI_KICK Baseband IPI Kick...
Page 416 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.9 MAC Power Save Configuration Registers (base: 0x1018_0000) 2.22.9.1 List of Registers Offset Register Name Description Page 0x1200 MAC_STATUS_REG MAC Status Register 0x1204 PWR_PIN_CFG Power Pin Configuration 0x1208 AUTO_WAKEUP_CFG Auto-Wakeup Configuration 0x120C AUX_CLK_EN...
Page 417 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.9.2 Register Descriptions 545. MAC_STATUS_REG: (offset: 0x1200) Bits Type Name Description Initial Value 31:2 Reserved RX_STATUS Rx Status Indicates that Rx is busy. 0: Idle 1: Busy TX_STATUS Tx Status. Indicates that Tx is busy.
Page 418 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value WAKEUP_LEAD_TIME Auto-Wakeup Lead Time 0x14 Sets the auto-wakeup lead time. (unit: 1 TU (1024 μs)) 548. AUX_CLK_EN (offset: 0x120C, default: 0x0000_0001) Bits Type Name Description Initial Value...
Page 419 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value BB_PA_MODE_CCK2 BB PA CCK2 Mode Select BB_PA_MODE_CCK1 BB PA CCK1 Mode Select NOTE: 00: OFDM EVM limited 01: OFDM spectrum mask limited 10: CCK EVM limited 11: CCK spectrum mask limited 551.
Page 420 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 11:10 RF_PA_MODE_OFDM9 BB PA OFDM9 Mode Select RF_PA_MODE_OFDM6 BB PA OFDM6 Mode Select RF_PA_MODE_CCK11 BB PA CCK11 Mode Select RF_PA_MODE_CCK5 BB PA CCK5 Mode Select RF_PA_MODE_CCK2 BB PA CCK2 Mode Select RF_PA_MODE_CCK1...
Page 421 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.10 MAC Tx Configuration Registers (base: 0x1018_0000) 2.22.10.1 List of Registers Offset Register Name Description Page 0x1300 EDCA_AC0_CFG (BE) Enhanced Distributed Channel Access (EDCA) Access Category 0 Configuration (Best Effort) 0x1304 EDCA_AC1_CFG (BK) EDCA Access Category 1 Configuration (Background)
Page 422 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 0x1390 TX_MPDU_UP_DOWN_TH Tx MPDU Upgrade Downgrade Threshold 0x1394 TX_AMPDU_UP_DOWN_T Tx A-MPDU Upgrade Downgrade Threshold HRES 0x1398 TX_FBK_LIMIT Tx Fallback Limit 0x13A0 TX0_RF_GAIN_CORRECT Tx0 RF Gain Correction 0x13A4 TX1_RF_GAIN_CORRECT Tx1 RF Gain Correction 0x13A8 TX0_RF_GAIN_ATTEN Tx0 RF Gain Attenuation...
Page 423 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.10.2 Register Descriptions 554. EDCA_AC0_CFG (BE): (offset: 0x1300) Bits Type Name Description Initial Value 31:20 Reserved 19:16 AC0_CWMAX Sets the maximum contention window for access category 0. AC0_CWMAX AC0 CWmax = 2 0: 1 1: 2 2: 4, and so on...
Page 424 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 556. EDCA_AC2_CFG (VI): (offset: 0x1308) Bits Type Name Description Initial Value 31:20 Reserved 19:16 AC2_CWMAX Sets the maximum contention window for access category 2 as follows: AC2_CWMAX AC2 CWmax = 2 0: 1 1: 2 2: 4, and so on...
Page 425 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:14 TID7_AC_MAP Traffic ID 7 Access Control Mapping Sets the AC value when TID=7. 13:12 TID6_AC_MAP Traffic ID 6 Access Control Mapping Sets the AC value when TID=6. 11:10 TID5_AC_MAP Traffic ID 5 Access Control Mapping...
Page 426 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 8-bit signed value (unit: 0.5 dB), valid range: -16 dB to 15.5 dB 562. TX_PWR_CFG_3: (offset: 0x1320) Bits Type Name Description Initial Value 31:24 TX_PWR_STBC_2 Tx power for STBC MCS=2, 3 23:16 TX_PWR_STBC_0 Tx power for STBC MCS=0, 1...
Page 427 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 31:22 Reserved RFRX_POL RF Receive Polarity Sets the polarity of the RF Rx. RFRX_EN RF Receive Enable Enables RF Receiving TRSW_POL Transmit Switch Polarity Sets the polarity of the antenna switch.
Page 428 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip NOTE: Where applicable, 0: Disable 0: Maintain original polarity settings. 1: Enable 1: Invert existing polarity settings. 568. TX_BAND_CFG: (offset: 0x132C) Bits Type Name Description Initial Value 31:1 Reserved TX_BAND_SEL Tx Band Selection Selects the lower or upper 40 MHz band in 20...
Page 429 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:8 DLY_TRSW_DIS Delay of TR_SW Disassertion Sets the delay period for disassertion of the TRSW interrupt, from when a switch between Rx and Tx occurs, to when the interrupt is disasserted.
Page 430 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 23:16 CF_END_THRES CF-END Threshold When the remaining TXOP is greater than the threshold, the CF-END is sent to release the remaining TXOP reserved by long NAV. 0xFF: Disable CF-END transmission.
Page 431 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value TXOP_TRUN_EN Enables TXOP truncation. 0x3F Bit5: Reserved Bit4: Truncation for MIMO power save RTS/CTS Bit3: Truncation for user TXOP mode Bit2: Truncation for Tx rate group change Bit1: Truncation for AC change Bit0: TXOP timeout truncation 0: Disable...
Page 432 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value TX_AUTOFB_EN Tx Auto-Fallback Enable Enables auto-fallback of the PHY rate for retry 0: Disable 1: Enable AGG_RTY_MODE A-MPDU Retry Mode Sets expiration of the A-MPDU retry mode. 0: Expired by retry limit 1: Expired by MPDU life timer NAG_RTY_MODE...
Page 433 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 23:20 HT_MCS5_FBK Auto-fallback MCS when HT MCS =5 19:16 HT_MCS4_FBK Auto-fallback MCS when HT MCS =4 15:12 HT_MCS3_FBK Auto-fallback MCS when HT MCS =3 11:8 HT_MCS2_FBK Auto-fallback MCS when HT MCS =2...
Page 434 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 31:16 Reserved 15:12 CCK3_FBK Auto-fallback MCS when the previous Tx rate is CCK 11 Mbps. 11:8 CCK2_FBK Auto-fallback MCS when the previous Tx rate is CCK 5.5 Mbps.
Page 435 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:0 CCK_PROT_RATE CCK Protection Rate Sets the protection control frame rate for CCK Tx, including RTS, CTS-to-self, and CF-END. Default: CCK 11 Mbps 583.
Page 436 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value MM20_RTSTH_EN Mixed Mode 20 MHz RTS Threshold Enable Enables RTS threshold in 20 MHz mixed mode 0: Disable 1: Enable 25:20 MM20_PROT_TXOP Mixed Mode 20 MHz Protection TXOP Sets the transmission mode for MM-20 TXOP.
Page 437 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 25:20 MM40_PROT_TXOP Mixed Mode 40 MHz Protection TXOP Sets the transmission mode for MM40 TXOP. Bit25: Allow GF 40 MHz Tx. Bit24: Allow GF 20 MHz Tx. Bit23: Allow MM 40 MHz Tx.
Page 438 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 19:18 GF20_PROT_NAV Green Field 20 MHz Protection NAV Sets the TXOP protection type for GF 20 MHz 0: None 1: Short NAV protection 2: Long NAV protection 3: Reserved (None) 17:16...
Page 439 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 17:16 GF40_PROT_CTRL Green Field 40 MHz Protection Control Sets the protection control frame type for GF 40 MHz Tx. 0: None 1: RTS/CTS 2: CTS-to-self 3: Reserved (None) 15:0...
Page 440 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RTS_FBK_TO RTS Fallback To Legacy Enable _LEGACY_EN Enables RTS Tx rate fallback to legacy OFDM/CCK. 0: Disable 1: Enable 11:8 RTS_FBK_TO RTS Fallback To Legacy Rate _LEGACY_RATE Sets the target legacy OFDM/CCK rate for RTS when a fallback from MCS0 occurs.
Page 441 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:8 TX_AMPDU_ADJ_INT1 AMPDU Tx Rate Adjustment Interval at Tx Fallback Level 1 (unit: number of MPDU) TX_AMPDU_ADJ_INT0 AMPDU Tx Rate Adjustment Interval at Tx Fallback Level 0 (unit: number of MPDU) 593.
Page 442 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value TX_RATE_LUT_EN Tx Rate Lookup Table Enable Copies the Tx rate from per WCID lookup table when TXWI.TXLUT is also set to 1. 0: Disable 1: Enable TX_AMPDU_UP _CLEAR Tx A-MPDU Upgrade Clear...
Page 443 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 21:16 GAIN_CORR_2 Gain Correction 2 0x00 Tx1 Gain Correction when RF_ALC[3:2]==2. Unit: 0.1 dB, Range: -3.2 dB to 3.1 dB 15:14 Reserved 0x00 13:8 GAIN_CORR_1 Gain Correction 1...
Page 444 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 14:8 RF_GAIN_ATTEN_1 Tx1 RF Gain Attenuation Level 1 0x6C Format: 7-bit, signed value Unit: 0.5 dB, Range: -20 dB to -5 dB Reserved 0x00 RF_GAIN_ATTEN_0 Tx1 RF Gain Attenuation Level 0...
Page 445 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 23:22 TX1_RF_GAIN_ATTEN Tx1 RF Gain Attenuation Mode Sets the Tx1 RF gain attentuation according to settings available in the TX1_RF_GAIN_ATTEN (offset: 0x13A8) register. 0: Applies RF_GAIN_ATTEN_0 (bit[6:0]) settings.
Page 446 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value RF_GAINATT_DBG Tx ALC RF Gain Attenuation Debug Value 0x00 Applied to RF when TX_ALC_RF_DBG_EN is set to 1. TX_ALC_RF_DBG_EN Tx ALC RF Control Pin Debug Enable 0x00 0: Disable 1: Enable...
Page 447 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value BB_GAIN_ATTEN_0 Tx1 Baseband Gain Attenuation Level 0 0x18 Format: 5-bit, signed value Unit: 0.5 dB, Range: -8 dB to 7 dB 605. TX_ALC_VGA3: (offset: 0x13C8, default: 0x0000_0000) Bits Type Name...
Page 448 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value TX_AC_RTY_LIMIT_EN Tx AC Retry Limit Enable Applies per AC Tx retry limit parameters. 0: Disable 1: Enable 608. PIFS_TX_CFG: (offset: 0x13EC) Bits Type Name Description Initial Value...
Page 449 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.11 MAC Rx Configuration Registers (base: 0x1018_0000) 2.22.11.1 List of Registers Offset Register Name Description Page 0x1400 RX_FILTR_CFG Receive Filter Configuration 0x1404 AUTO_RSP_CFG Auto-Respond Configuration 0x1408 LEGACY_BASIC_RATE Legacy Basic Rate 0x140C HT_BASIC_RATE High Throughput Basic Rate...
Page 450 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.11.2 Register Descriptions 609. RX_FILTR_CFG: (offset: 0x1400) Bits Type Name Description Initial Value 31:17 Reserved DROP_CTRL_RSV Drops reserve control subtype. DROP_BAR Drops BAR frames. DROP_BA Drops BA frames. DROP_PSPOLL Drops PS-Poll frames.
Page 451 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value CTS_40M_REF CTS Legacy Reference When in duplicate legacy CTS response mode, this bit enables the use of the extension CCA signal to decide whether to duplicate or not. CTS_40M_MODE CTS Legacy Response Enable Enables duplicate legacy CTS response mode.
Page 452 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value HT_CTRL_THRES HT Control Threshold 0x100 Sets the remaining TXOP threshold for HT control frame auto-response. (unit: 1 μs) 614. SIFS_COST_CFG: (offset: 0x1414) Bits Type Name Description...
Page 453 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 617. MAC_ADDR_EXT0_31_0 (offset: 0x1480, default: 0x0000_0000) Bits Type Name Description Initial Value 31:0 MAC_ADDR_EXT0_31_0 Extended MAC Address0 bit[31:0] 618. MAC_ADDR_EXT0_47_32 (offset: 0x1484, default: 0x0000_0000) Bits Type Name Description Initial Value 31:16 Reserved 15:0...
Page 454 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 627. MAC_ADDR_EXT5_31_0 (offset: 0x14A8, default: 0x0000_0000) Bits Type Name Description Initial Value 31:0 MAC_ADDR_EXT5_31_0 Extended MAC Address5 bit[31:0] 628. MAC_ADDR_EXT5_47_32 (offset: 0x14AC, default: 0x0000_0000) Bits Type Name Description Initial Value 31:16 Reserved 15:0...
Page 455 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:0 MAC_ADDR_EXT9_47_32 Extended MAC Address9 bit[47:32] 637. MAC_ADDR_EXT10_31_0 (offset: 0x14D0, default: 0x0000_0000) Bits Type Name Description Initial Value 31:0 MAC_ADDR_EXT10_1_0 Extended MAC Address10 bit[31:0] 638.
Page 456 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 31:16 Reserved 15:0 MAC_ADDR_EXT14_47_32 Extended MAC Address14 bit[47:32] 647. MAC_ADDR_EXT15_31_0 (offset: 0x14F8, default: 0x0000_0000) Bits Type Name Description Initial Value 31:0 MAC_ADDR_EXT15_31_0 Extended MAC Address15 bit[31:0] 648.
Page 457 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.12 MAC Security Configuration Registers (base: 0x1018_0000) 649. TX_SEC_CNT0: (offset: 0x1500) Bits Type Name Description Initial Value 31:16 TX_SEC_ERR_CNT Tx Security Error Count Counts the number of transmitted frames that do not successsfully pass the security engine.
Page 458 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.13 MAC HCCA/PSMP Control Status Registers (base: 0x1018_0000) 2.22.13.1 List of Registers Offset Register Name Description Page 0x1600 TXOP_HLDR_ADDR0 Transmit Opportunity Holder Address 0 0x1604 TXOP_HLDR_ADDR1 Transmit Opportunity Holder Address 1 0x1608 TXRX_MICS_CTRL Tx/Rx MICS Control...
Page 459 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.13.2 Register Descriptions 652. TXOP_HLDR_ADDR0: (offset: 0x1600) Bits Type Name Description Initial Value 31:24 TXOP_HOL_3 TXOP holder MAC address byte3 23:16 TXOP_HOL_2 TXOP holder MAC address byte2 15:8 TXOP_HOL_1 TXOP holder MAC address byte1 TXOP_HOL_0 TXOP holder MAC address byte0...
Page 460 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value PAPE_MAP1S_EN Power Amplifier Power Enable 1 Stream Mapping Enable Sets PAPE to turn on only in 1S transmission. TX_BCN_HIPRI_DIS Tx Beacon High Priority Disable Disables high priority beacon transmission.
Page 461 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip NOTE: CFPOLL_RA_DW0, CFPOLL_RA_DW1, and CFPOLL_QC are updated after receiving a QoS Data (+)CF-Poll frame. An Rx QoS CF-Poll interrupt (RX_QOS_CFPOLL_INT) is then launched. PGMT7620_V.1.0_040503 Page 461 of 523...
Page 462 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.14 MAC Statistic Counters (base: 0x1018_0000) 2.22.14.1 List of Registers Offset Register Name Description Page 0x1700 RX_STA_CNT0 Receive Status Counter 0 0x1704 RX_STA_CNT1 Receive Status Counter 1 0x1708 RX_STA_CNT2 Receive Status Counter 2 0x170C TX_STA_CNT0...
Page 463 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.14.2 Register Descriptions 658. RX_STA_CNT0: (offset: 0x1700) Bits Type Name Description Initial Value 31:16 PHY_ERRCNT PHY Error Count Counts the number of frames with Rx PHY errors. 15:0 CRC_ERRCNT CRC Error Count Counts the number of frames with Rx CRC errors.
Page 464 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 662. TX_STA_CNT1: (offset: 0x1710) Bits Type Name Description Initial Value 31:16 TX_RTY_CNT Tx Retry Count Counts the number of times delivery of a frame was reattempted after initial failure. 15:0 TX_SUCC_CNT Tx Successful Count...
Page 465 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:0 TX_NAG_CNT Tx Unaggregated Count Counts the number of unaggregated MPDUs transmitted. 666. TX_AGG_CNT0: (offset: 0x1720) Bits Type Name Description Initial Value 31:16 TX_AGG_2_CNT A-MPDU Size 2 Tx Count Counts the number of A-MPDUs with aggregate...
Page 466 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:0 TX_AGG_9_CNT A-MPDU Size 9 Tx Count Counts the number of A-MPDUs with aggregate size = 9. 671. TX_AGG_CNT5: (offset: 0x1734) Bits Type Name Description Initial Value...
Page 467 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:0 RTS_TX_OK_CNT RTS Frames Tx Succeeded Count Counts the number of successful RTS frames transmitted. 676. CTS_TX_CNT: (offset: 0x1748) Bits Type Name Description Initial Value 31:16 Reserved...
Page 468 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:0 TX_AGG_23_CNT A-MPDU Size 23 Tx Count Counts the number of A-MPDUs with aggregate size = 24. 681. TX_AGG_CNT12: (offset: 0x175C) Bits Type Name Description Initial Value...
Page 469 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 15:0 WCID_A_TXOK_CNT WCID Tx OK Count 0 Counts the number of successful Tx for WCID_A. 686. WCID_B_TX_CNT: (offset: 0x1770) Bits Type Name Description Initial Value 31:16 WCID_B_TXRTY_CNT...
Page 470 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Type Name Description Initial Value 31:16 WCID_G_TXRTY_CNT WCID Tx Retry Count 0 Counts the number of Tx retries for WCID_G. 15:0 WCID_G_TXOK_CNT WCID Tx OK Count 0 Counts the number of successful Tx for WCID_G.
Page 471: Table 2-27
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.22.15 MAC Search Table (base: 0x1018_1800) 2.22.15.1 Rx WCID Search Entry Format (8 bytes) Offset Type Name Description Initial Value 0x00 WC_MAC_ADDR0 Client MAC address byte0 0x01 WC_MAC_ADDR1 Client MAC address byte1 0x02 WC_MAC_ADDR2 Client MAC address byte2...
Page 472: Table 2-29
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Table 2-29: 0x1398 TX_RATE_LUT_EN = 1 and MULTI_MAC_ADDRESS = 1 Offset Type Name Description Initial Value 0x1800 WC_ENTRY_0 WC MAC address with WCID=0 0x1808 WC_ENTRY_1 WC MAC address with WCID=1 ….
Page 473 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3. Security Entry Formats and Key Tables 3.1 Security Entry Format Tables (base: 1018.0000, offset: 0x4000) Table Name Description The location and format of the security key. Security Key Format (8DW) IV/EIV/WAPI_PN Format The location and format of the (Extend) Initialization Vector and WAPI (4DW)
Page 474 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.1.2.2 WAPI_PN Format Offset Type Name Description Initial Value 0x00 WAPI_PN_MSB WAPI PN byte11 to byte8 0x04 WAPI_PN_MSB WAPI PN byte15 to byte12 Table 3-2 WAPI_PN Format NOTE: 1. The key index and extension IV bit are initialized by software. The MSB octet of IV is not modified by hardware.
Page 475: Table 3-4 Shared Key Mode Entryf
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Offset Type Name Description Initial Value RX_PKEY_MODE Pairwise Key Security Mode 0: No security 1: WEP40 2: WEP104 3: TKIP 4: AES-CCMP 5: CKIP40 6: CKIP104 7: CKIP128 RX_PKEY_EN Key Table Selection 0: Shared key table 1: Pairwise key table...
Page 476 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.2 Security Tables (offset: 0x4000) The following security tables are found in this section. Table Name and Offset Description Pairwise Key Table (offset: 0x4000) The location and format of the pairwise keys. IV/EIV Table (offset: 0x6000) The location and format of the (Extended) Initialization Vectors.
Page 477: Table 3-5 Pairwise Key Table
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.3.1 Pairwise Key Table (offset: 0x4000) Offset Type Name Description Initial Value 0x4000 PKEY_0 Pairwise key for WCID0 0x4020 PKEY_1 Pairwise key for WCID1 …. …. Pairwise key for WCID2 to 253 0x5FC0 PKEY_254 Pairwise key for WCID254...
Page 478: Table 3-8 Shared Key Table
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Offset Type Name Description Initial Value 0x6D60 SKEY_11 Shared key for BSS_IDX=2, KEY_IDX=3 0x6D80 SKEY_12 Shared key for BSS_IDX=3, KEY_IDX=0 0x6DA0 SKEY_13 Shared key for BSS_IDX=3, KEY_IDX=1 0x6DC0 SKEY_14 Shared key for BSS_IDX=3, KEY_IDX=2 0x6DE0 SKEY_15...
Page 479: Table 3-10 Shared Key Mode Extension
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.3.7 Shared Key Mode Extension (for BSS_IDX=8 to 15) (offset: 0x73F0) Offset Type Name Description Initial Value 0x73F0 SKEY_MODE_32_39 Shared mode for SKEY32 to SKEY39 0x73F4 SKEY_MODE_40_47 Shared mode for SKEY40 to SKEY47 0x73F8 SKEY_MODE_48_55 Shared mode forSKEY48 to SKEY55...
Page 480: Table 3-11 Shared Key Table Extension
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Offset Type Name Description Initial Value 0x7780 SKEY_60 Shared key for BSS_IDX=15, KEY_IDX=0 0x77A0 SKEY_61 Shared key for BSS_IDX=15, KEY_IDX=1 0x77C0 SKEY_62 Shared key for BSS_IDX=15, KEY_IDX=2 0x77E0 SKEY_63 Shared key for BSS_IDX=15, KEY_IDX=3 Table 3-11 Shared Key Table Extension (for BSS_IDX=8 to15) (offset: 0x7400) 3.3.9 WAPI PN Table (Extension of IV/EIV Table) (offset: 0x7800)
Page 481 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 4. Tx/Rx Descriptors and Wireless Information 4.1 Tx Descriptors and Frame Information To transmit a frame, the driver needs to prepare the Tx frame information for hardware. The Tx frame information contains the transmission control, the header, and the payload.
Page 482 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 4.1.1 TXD Format bit 31 bit 0 SDP0[31:0] SDL0[13:0] SDL1[13:0] SDP1[31:0] Reserved [4:0] QSEL Reserved[23:0] Figure 4-2 TXD Format The following is a detailed description of each field in the TXD. PGMT7620_V.1.0_040503 Page 482 of 523...
Page 483: Table 4-1 T Xdescriptor Format Field
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 4.1.1.1 TXD Field Descriptions Bits Name Description DWORD0 31:0 SDP0 Segment Data Pointer0 DWORD1 DDONE DMA Done: DMA has transferred the segments pointed to by this Tx descriptor. Last Segment0: Data pointed to by SDP0 is the last segment. 29:16 SDL0 Segment Data Length0: Segment data length for the data pointed to by SDP0.
Page 484 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 4.1.2 Tx Wireless Information Tx wireless information (TXWI) is prepared by the host driver and used for passing information to the MAC. Its size is 4 DW and it is put at the head of each Tx frame. bit 0 MPDU STBC...
Page 485 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 4.1.2.1 TXWI Field Descriptions Bits Name Description DWORD0 MIMO Selects the PHY mode. Combine MIMO and OFDM bit values to select options. 00: CCK 01: OFDM OFDM 10: Mixed mode 11: Green field For example, MIMO = 1, OFDM =0 ...
Page 486 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Name Description Time Stamp Requests the MAC to insert an 8-byte timestamp after the 802.11 WLAN header in Beacon or ProbeResponse frames. 0: No timestamp 1: Inserts a timestamp CFACK Combines ACK and DATA frames.
Page 487 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bits Name Description PIFS_REV_EN After TxOP ACK, enable PIFS Time reversed direction Tx. 0: Disable 1: Enable 21:20 Reserved 19:16 Tx_Pwr_Adj Transmit Power Adjustment Sets Tx power to a value from -16 dB to +7 dB. When negative, each unit represents 2 dB;...
Page 488 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 4.2 Rx Descriptors and Wireless Information The Rx descriptor (RXD) specifies the location to place the payload of the received frame (the Rx payload) and the associated receiving information (RXWI). One RXD serves for one receiving frame. Only SDP0 and SDL0 are useful in the RXD.
Page 489 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 4.2.1 RXD Format bit 31 bit 0 SDP0[31:0] DDONE SDL0[13:0] SDL1[13:0] SDP1[31:0] RXINFO Figure 4-4 Rx Descriptor Format The following is a detailed description of each field in the RXD. 4.2.1.1 RXD Field Descriptions Name Description...
Page 490 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 4.2.2 RXINFO Format RXINFO is prepared by the MAC and used for passing information to the host driver. Its size is 1 DW and it is put at the head of each Rx frame. bit 0 DATA NULL...
Page 491 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 4.2.2.1 RXINFO Field Descriptions Name Description 31:22 Reserved 21:19 PN_LEN IV/EIV/PN padding length (unit: DW) WAPI_KID WAPI Key ID BSSIDX3 BSS index bit3, use together with BSS index bit[2:0] in RXWI Indicates this frame is a decrypted frame AMPDU Indicates this frame has been de-aggregated from an AMPDU.
Page 492 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 4.2.3 RXWI Format RXWI is prepared by the MAC and used for passing information to the host driver. Its size is 6 DW and it is put at the head of each Rx frame. bit 31 bit 0 BSS idx...
Page 493 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 4.2.3.1 RXWI Field Descriptions Name Description DWORD0 31:28 Traffic ID extracted from the 802.11 QoS control field. 27:16 MPDU total byte The entire MPDU length. count 15:13 User defined field. 12:10 BSSID idx (index) 0 to 7 for BSSID0:7.
Page 494 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 4.3 Brief PHY Rate Format and Definition A 16-bit brief PHY rate is used in MAC hardware. It is the same PHY rate field as that referred to in TXWI and RXWI sections.
Page 495 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 4.3.1 Modulation and Coding Scheme Modulation and Coding Scheme (MCS) Description MODE = Legacy CCK MCS = 0 Long Preamble CCK 1 Mbps MCS = 1 Long Preamble CCK 2 Mbps MCS = 2 Long Preamble CCK 5.5 Mbps MCS = 3...
Page 496 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Modulation and Coding Scheme (MCS) Description MCS = 13 (BW=0, SGI=0) 104 Mbps MCS = 14 (BW=0, SGI=0) 117 Mbps MCS = 15 (BW=0, SGI=0) 130 Mbps MCS = 32 (BW=1, SGI=0) HT duplicate 6 Mbps When BW=1, PHY_RATE = PHY_RATE * 2.
Page 497 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 5. SD Host Controller 5.1 Features SD Host Controller contains:  32-bit access for control registers  8-bit/16-bit/32-bit access for FIFO in PIO mode  Built-in 128-byte FIFO buffers for transmit and receive ...
Page 498 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 5.2.1 Basic DMA Mode The operation in basic DMA mode is the same as conventional DMA operation. In this mode, the DMA controller moves a bulk of data from the source to MSDC. MSDC Controller FDSAR...
Page 499 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip MSDC Controller DSAR SD1 DSAR SD2 Host to Card Transfer/ Card to Host Transfer Data Data Data Data Data Data Figure 5-3 Descriptor DMA PGMT7620_V.1.0_040503 Page 499 of 523...
Page 500 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 5.2.3 DMA Generic Packet Descriptor (GPD) Format Figure 5-4 GPD Format The structure of a DMA Generic Packet Descriptor (GPD) is defined in the following table. Please note that the start address of a descriptor should be 4 B alignment. Offset Field Description...
Page 501 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Bit 1: Buffer Descriptor Present This bit is set according to the following conditions: 0: A data buffer is directly pointed to by the DATA_BUFF_PTR field in this descriptor. In this case, only one data buffer is associated with this DMA GPD. 1: The DATA_BUFF_PTR field does not directly point to a data buffer, but a linked list of DMA Buffer Descriptors instead.
Page 502 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 0x14 to BLOCK_NUMBER Enhance Mode SD Block Number 0x17 This field defines SDC_BLOCK_NUMBER. 0x18 to Enhance Mode SD Command 0x1B This field defines SDC_CMD. 5.2.4 DMA Buffer Descriptor (BD) Format Figure 5-5 BD Format The structure of a DMA Buffer Descriptor (BD) is defined in the following table.
Page 503 The length of the data buffer that is pointed to by the Data Buffer Pointer field, (unit: bytes) 5.2.5 Register Description (base: 0x1013_0000) These registers are used for the SD driver. For more information on these registers, please contact MediaTek. PGMT7620_V.1.0_040503 Page 503 of 523...
Page 504 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 6. List of Registers 1. CHIPID0_3: C ID ASCII C 0-3 ( 0000) ................... 19 HARACTER OFFSET 2. CHIPID4_7: C ASCII C 4-7 ( 0004) ................19 HARACTER OFFSET 3.
Page 505 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 49. IIR: I 000C) ..................65 NTERRUPT DENTIFICATION EGISTER OFFSET 50. FCR: FIFO C 0010) ....................66 ONTROL EGISTER OFFSET 51. LCR: L 0014) ..................... 66 ONTROL EGISTER OFFSET 52.
Page 506 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 99. GPIO71_40_RESET: C PIO P 0080)................93 LEAR ATA BIT OFFSET 100. GPIO71_40_TOG: T PIO P 0084) ................93 OGGLE ATA BIT OFFSET 101. GPIO72_INT: PIO P 0088) ................. 93 NTERRUPT TATUS OFFSET...
Page 507 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 149. CHA_CFG2: ( 0034, 0 0134) ( =0, 1) ..................... 126 OFFSET 150. CHB_CFG2: ( 0034, 0 0138) ( =0, 1) ..................... 126 OFFSET 151. IP_INFO: ( 0040) ..........................127 OFFSET 152.
Page 508 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 195. TX_FIFO_WREG: T 0010) ................157 RITE UFFER OFFSET 196. RX_FIFO_RREG: R 0014)................. 157 UFFER OFFSET 197. I2S_CFG1: I 0018) ..............157 OOPBACK ONTROL EGISTER OFFSET 198. DIVCOMP_CFG: I 0020) ..............
Page 509 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 245. FOE_TS_T: T 0010) ....................... 213 TAMP OFFSET 246. IPV6_EXT: IP 0014) ..................214 XTENSION EADER OFFSET 247. G2P_FC: GSW PDMA F 0018) ................214 ONTROL OFFSET 248. P2G_FC: PDMA GSW F 001C) ................
Page 510 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 295. IMC: IGMP/MLD M 001C) ..............258 ESSAGE ONTROL EGISTER OFFSET 296. APC: ARP 0020) ................260 ONTROL EGISTER OFFSET 297. BPC: BPDU PAE C 0024) ................262 ONTROL EGISTER OFFSET 298.
Page 511 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 343. MMSCR1_Q0P 1004, 0 1104, 0 1204, CHEDULER ONTROL EGISTER UEUE ORT N OFFSET 1304, 0 1404, 0 1504, 0 1604, 0 1704) ......................293 344. MMSCR0_Q1P 1008, 0 1108, 0 1208, CHEDULER...
Page 512 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 371. GIRLCR: G 1FF0) ............306 LOBAL NGRESS IMIT ONTROL EGISTER OFFSET 372. GFCCR2: G 1FF4) ............307 LOBAL ONTROL ONTROL EGISTER OFFSET 373. SSC: STP S 2000, 0 2100, 0 2200, 0 2300, 0...
Page 513 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 400. TGPC 4010, 0 4110, 0 4210, 0 4310, 0 4410, 0 4510, 0 4610, ACKET OUNTER OF ORT N OFFSET 4710) ................................334 401. TBOC 4014, 0 4114, 0 4214, 0 4314, 0 4414, 0...
Page 514 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 441. PCIE_SUBID: S 0038) ..........366 ENDOR AND EVICE ONTROLLER OFFSET 442. PCIE0_STATUS: PCI 0050) .................. 366 TATUS EGISTER OFFSET 443. DLECR: D 0060) ..............366 ATALINK AYER RROR OUNTER EGISTER OFFSET...
Page 515 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 491. MAX_LEN_CFG: ( 1018) ......................... 398 OFFSET 492. BBP_CSR_CFG: ( 101C) ........................398 OFFSET 493. RF_CSR_CFG0: ( 1020) ........................399 OFFSET 494. RF_CSR_CFG1: ( 1024) ........................399 OFFSET 495. RF_CSR_CFG2: ( 1028) ........................
Page 516 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 541. CH_IDLE_STA: ( 1130) ........................414 OFFSET 542. CH_BUSY_STA: ( 1134) ........................414 OFFSET 543. EXT_CH_BUSY_STA: ( 1138) ......................415 OFFSET 544. BBP_IPI_TIMER: ( 113C) ........................ 415 OFFSET 545. MAC_STATUS_REG: ( 1200) ......................
Page 517 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 591. TX_MPDU_ADJ_INT: ( 1388) ......................440 OFFSET 592. TX_AMPDU_ADJ_INT: ( 138C) ....................... 440 OFFSET 593. TX_MPDU_UP_DOWN_THRES: ( 1390) ..................441 OFFSET 594. TX_AMPDU_UP_DOWN_THRES: ( 1394) ..................441 OFFSET 595. TX_FBK_LIMIT: ( 1398) ........................
Page 518 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 641. MAC_ADDR_EXT12_31_0 ( 14E0, 0000_0000) ............455 OFFSET DEFAULT 642. MAC_ADDR_EXT12_47_32 ( 14E4, 0000_0000) ............455 OFFSET DEFAULT 643. MAC_ADDR_EXT13_31_0 ( 14E8, 0000_0000) ............455 OFFSET DEFAULT 644. MAC_ADDR_EXT13_47_32 ( 14EC, 0000_0000) ............
Page 519 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 691. WCID_G_TX_CNT: ( 1784) ......................469 OFFSET 692. WCID_H_TX_CNT: ( 1788) ......................470 OFFSET 693. WCID_X_SELECT: ( 178C) ......................470 OFFSET 694. WCID_X_SELECT: ( 1790) ......................470 OFFSET 695. TX_REPORT_CNT: ( 1794) ......................
Page 520 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 7. Abbreviations Abbrev. Description Abbrev. Description Access Category Cyclic Redundancy Check Acknowledge/ Acknowledgement Control Status Register Access Control List Clear to Send ACPR Adjacent Channel Power Ratio Contention Window AD/DA Analog to Digital/Digital to Analog CWmax...
Page 521 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Abbrev. Description Abbrev. Description General Purpose Output MLNA Monolithic Low Noise Amplifier GPON Gigabit Passive Optical Network Mixed Mode GPIO General Purpose Input/Output MOSFET Metal Oxide Semiconductor Field Effect Transistor GPRS General Packet Radio Service MPDU...
Page 522 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Abbrev. Description Abbrev. Description Rbus to Pbus Transmitter Address Reverse Direction Grant TBTT Target Beacon Transmission Time Random Access Memory TDLS Tunnel Direct Link Setup Root Complex TKIP Temporal Key Integrity Protocol Radio Frequency Tx Offset RGMII...
Page 523: Revision History
MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 8. Revision History Date From Description 2012/01/18 Lancelot Lin Initial Release (Split programming guide from original spec) This product is not designed for use in medical, life support applications. Do not use this product in these types of equipments or applications .This document is subject to change without notice and Ralink assumes no responsibility for any inaccuracies that nay be contained in this document.

MEDIATEK Ralink MT7620 Programming Manual

Integrated 802.11N Mac/Bbp and 2.4 Ghz Rf/Fem Router-On-A-Chip

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