MEDIATEK MT6252 Design Manual

Design notice

page of 166

/ 166
Bookmarks

Quick Links

Download this manual

MT6252

MT6252 Design

Design Notice

Notice

V0.1

2010/12/10

Summary of Contents for MEDIATEK MT6252

Page 3 2.8V IO LCM 1.8V IO LCM 1. 1.8V IO LCM 4 bit IO 1 bit IO 1.IOT MSDC 2.DAT3 as Card detect Quad band SOC Same with 53 1.Schematic notice 2.Layout notice Copyright © MediaTek Inc. All rights reserved. 2011/1/17 3.BPI modification...
Page 4 Placement notice TXM(PRF88144B) +Rx SAWs 26MHz crystal , must close to BB C-load, Must close 32.768KHz MT6252 SOC 32.768KHz crystal , Serial Flash , must close to BB must close to BB Copyright © MediaTek Inc. All rights reserved. 2008/06...
Page 5 MT6252 Chip configuration design notice (BB) MT6252 Chip configuration design notice (BB) 1.TESTMODE TESTMODE(Pin (Pin J6) should be connected to ground. J6) should be connected to ground. 2.PMU_TESTMODE PMU_TESTMODE(Pin (Pin H5) should be connected to ground. H5) should be connected to ground.
Page 6 MT6252 Chip configuration design notice (BB) MT6252 Chip configuration design notice (BB) 1.There should be a 100K ohm resistor connected to ground on 1.There should be a 100K ohm resistor connected to ground on if PWM is if PWM is used.
Page 7 MT6252 Chip configuration design notice (BB) MT6252 Chip configuration design notice (BB) 1.There should be a 100K ohm resistor connected to VIO on DAIRST and DAISYNC. 1.There should be a 100K ohm resistor connected to VIO on DAIRST and DAISYNC.
Page 8 VM = 1.8V. VM = 1.8V. MT6252 only support 1.8V memory. VMSEL should always be low. MT6252 only support 1.8V memory. VMSEL should always be low. Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 9 MT6252 Chip configuration design notice (BB) MT6252 Chip configuration design notice (BB) 1.FSOURCE FSOURCE should be connected to ground. should be connected to ground. Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 10 MT6252 Chip configuration design notice (MSDC) MT6252 Chip configuration design notice (MSDC) 1.MT6252 only support 1 bit MSDC. If 1.MT6252 only support 1 bit MSDC. If DAT3 is not used as card detection DAT3 is not used as card detection...
Page 11 MT6252 Chip configuration design notice(4 SIM) MT6252 Chip configuration design notice(4 SIM) Not used but still need bypass Not used but still need bypass Not used but still need bypass Not used but still need bypass capacitors. capacitors. Power of SIM comes from 6302 Power of SIM comes from 6302 1.
Page 12 MT6252 Chip configuration design notice ( MT6252 Chip configuration design notice (SRCLKENAI SRCLKENAI) ) 1. Please remember 1. Please remember to enable internal Pull down to enable internal Pull down when this pin is used as 26MHz clock when this pin is used as 26MHz clock...
Page 14 EMI voltage 1.8V 1.8V 1.8V 1.MT6252 support 78MHz and 104MHz QPI mode Serial Flash. 1.MT6252 support 78MHz and 104MHz QPI mode Serial Flash. 2.The power domain 2.The power domain of Serial flash is same as internal stacked of Serial flash is same as internal stacked PSRAM.So PSRAM.So , please use...
Page 15 MT6252 Chip memory configuration design notice MT6252 Chip memory configuration design notice U1006 / EN25S64 EN25S64 64M 1.8v EON Contact: Bull Tang Serial Flash Serial Flash bull1975@gmail.com 13502888931 6252 6252 6252 6252 (must be 1.8V) (must be 1.8V) t b 1 8V) t b 1 8V) Please connect the pins according to following table.
Page 16 MT6252 Memory Layout design notice MT6252 Memory Layout design notice MT6252 MT6252 Serial Flash Serial Flash Memory should be placed as close to MT6252 as possible. Memory should be placed as close to MT6252 as possible. Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 17 Their pins are fully compatible but pin locations are slightly shifted. Their pins are fully compatible but pin locations are slightly shifted. Please overlap the pins for SMT compatible. Please overlap the pins for SMT compatible. Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 18 The traces of memory should not be crossed by other traces or power. The traces of memory should not be crossed by other traces or power. (Nice to have) (Nice to have) Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 19 There should be a ground plane beneath the Serial Flash and QPI traces of There should be a ground plane beneath the Serial Flash and QPI traces of MT6252 (Ni MT6252 (Ni MT6252. (Nice to have) MT6252. (Nice to have) Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 21 Content Content Content ▪ MT6252 Introduction MT6252 Introduction – General description – Block diagram Block diagram – LDO list ▪ ▪ Comparison Comparison ▪ Function Description ▪ Reference design ▪ Appendix ppe d Copyright © MediaTek Inc. All rights reserved...
Page 22 MT6252 Introduction MT6252 Introduction – – General description General description ▪ The MT6252 is built-in high performance power management IC. ▪ Highly integrated functions fulfill all power requirement in handset system system – LDO • Analog LDO Digital LDO Digital LDO •...
Page 24 Far-end bypass cap VSIM 1.8/3.0 Far-end bypass cap 1 3/1 5/1 8/2 5 1.3/1.5/1.8/2.5 VSIM2 Far-end bypass cap 2.8/3.0/3.3 1.3/1.5/1.8/2.5/ VIBR Far-end bypass cap 2.8/3.0/3.3 100 F 1K + 100uF VRTC Backup battery (可依需求修改) Copyright © MediaTek Inc. All rights reserved...
Page 25 Content Content Content Content ▪ MT6252 Introduction MT6252 Introduction ▪ Comparison ▪ Function Description – Power on timing – Driver ▪ Reference design ▪ ▪ Appendix Appendix Copyright © MediaTek Inc. All rights reserved...
Page 26 ▪ Note 2 : PWM should set higher to prevent LCM from flickering in VBAT PWM f VBAT. PWM frequency > 20kHz is recommended 20kH i prevent both LCM flickering and audible noise. Copyright © MediaTek Inc. All rights reserved.
Page 27 When ISINK control by When ISINK control by When ISINK control by Register mode, It could be Register mode, It could be PWM dimming PWM dimming by PWM3 by PWM3 controlled independently controlled independently Copyright © MediaTek Inc. All rights reserved...
Page 28 ISINK0 current (mA) ISINK0 current (mA) RG_ISINKX_MODE ISINKX PWM MODE SEL 1 : Register control mode (see the RG_ISINK0_EN to turn-on) 0 : PWM mode (controlled by PWM3) 0 : PWM mode, (controlled by PWM3) Copyright © MediaTek Inc. All rights reserved...
Page 30 8 steps in total. The minimal current should be no less than 60mA at <111> step. RG_KPLED_SEL[2:0] KPLED current KPLED enable mode select KPLED enable mode select RG KPLED MODE RG_KPLED_MODE pwm mode, controlled by hardware PWM1 output signal Register control mode (see the KPLED_EN to turn-on) Copyright © MediaTek Inc. All rights reserved...
Page 31 Content Content Content Content ▪ MT6252 Introduction MT6252 Introduction ▪ Comparison ▪ Function Description ▪ Reference design – Schematic ▪ Appendix Copyright © MediaTek Inc. All rights reserved...
Page 32 Please reserve 1k resistor on phone PCB to protect PWRKEY no matter if PWRKEY connect to any I/O connector or not. Please reserve 1k resistor on phone PCB to protect BAT ON phone PCB to protect BAT_ON pin if BAT_ON is used to detect battery. Copyright © MediaTek Inc. All rights reserved...
Page 33 2. Zener diode end of connector cable. on phone. MT6252 has lower VBAT voltage rating. (Max. 4.3V.) Some protection should reserve to prevent the damage by voltage surge. •Design notice in Phone side: •Design notice in Phone side: 1.
Page 34 ▪ Ir<100uA @Vr=4.2V, Ta=25°C, Using 5.1V zener will introduce some leakage when VBAT = 4 2V Large Ir introduce some leakage when VBAT = 4.2V. Large Ir current will introduce more leakage current. Copyright © MediaTek Inc. All rights reserved...
Page 35 (长电科技) E mail: E-mail: cyz@cj elec com cyz@cj-elec.com Bull Tang 3 Prisemi PZ3D4V2H SOD323 11.5 500mW Mobile:13502888931 Email: bull1975@gmail.com 4 Prisemi PZ5D4V2H SOD523 4.85 500mW Mike_Wang 5 Vishay MMSZ4689-V SOD123 886-911313660 500mW mike.wang@Vishay.com Copyright © MediaTek Inc. All rights reserved...
Page 36 VBAT Input Filter VBAT Input Filter VBAT Input Filter ▪ All bypass cap. should be as close to MT6252 IC as possible ▪ Recommend reserve 0 ohm between VBAT pin & VBAT_RF, VBAT_ANALOG for analog LDO quality. analog LDO quality.
Page 37: Reference Design
Reference design Reference design - - Schematic Schematic Bypass Capacitor Bypass Capacitor ▪ At least 1 cap larger than 1uF on power trace VRF, VCAMA, VIO larger than 2uF Copyright © MediaTek Inc. All rights reserved...
Page 38 Reference design Reference design - - Schematic Schematic Bypass Capacitor for AVDD and VDD Bypass Capacitor for AVDD and VDD ▪ Reserve 0 ohm resistor for audio quality. Copyright © MediaTek Inc. All rights reserved...
Page 40 4.2V 4.2V comparator 160mV/R 160mV/R 160mV/R 24mV/R 20mV/R 20mV/R Pre_ charge 4.3V 4.3V 4.35V Battery OVP Watchdog timer 50 minutes Pre-charge safety timer P-MOSFET +SD P-MOSFET +SD BJT+ N-MOSFET Passed element Pre-charge/CC overlap Copyright © MediaTek Inc. All rights reserved.
Page 41 Power rating > 30V 4mil ISENSE Current sense Resistor R211 R213 J201 40mil 4mil VBAT VBAT BAT_TY PE AUX_IN4 R215 BC-4565-M-03-01-LF MLV200 TVS200 **Latest schematic please refer to reference design to reference design. Copyright © MediaTek Inc. All rights reserved.
Page 42 On semi TSOP6 886 2 23761153 886-2-23761153 886-987-265-997 Mag Cheng SC-74(SOT- SC 74(SOT mag cheng@nxp com mag.cheng@nxp.com PBSS5350D PBSS5350D 457) "+886-987-49186 +886-2-8170-9076 (Direct) Bull Tang SOT23 SOT23- 13502888931 Presemi PT236T30E2 6L(TSOP6) bull1975@gmail.com Copyright © MediaTek Inc. All rights reserved...
Page 43 BJT Power Dissipation and Charge Current BJT Power Dissipation and Charge Current ▪ Charger BJT selection Charger BJT selection – Max. charger voltage 10V – Max. battery charge current (0.72C for Li-ion 900mAHr) – Max. power dissipation of external BJT (1W),Duty=8/(8+1) di i l BJT (1W) D t 8/(8 1)
Page 44: Pulse Charging
Support low cost linear and Nokia adaptor charger(9.3V) – Meet 2010 China charger standard(12V OVP) – CC mode current control – Constant current pre-charging – Charger OVP and battery OVP – Pre-charge/CC safety timer – Watchdog timer Copyright © MediaTek Inc. All rights reserved.
Page 45 Design Notice – – Charge Current Setting Charge Current Setting Charge Current Setting Charge Current Setting MT6223 MT6235 MT6253 MT6252 Sense Resistor 0.2 Ohm 0.2 Ohm 0.2 Ohm Pre Charge Pre-Charge 62 5 62.5 62.5 62.5 87.5 Copyright © MediaTek Inc. All rights reserved.
Page 46 KAL_TRUE /* enable checking charging voltage while charging */ /* enable checking charging voltage while charging */ This should be TRUE. This should be TRUE. This should be TRUE. This should be TRUE. Copyright © MediaTek Inc. All rights reserved.
Page 47 Modify Chr_parameter.c , 6500000 10500000,/*VCHARGER_HIGH*/ Step 2 .HW OVP Please contact MTK to modify HW OVP for SW patch (default is 7V) ▪ BJT power dissipation. ▪ BJT Power Dissipation and Charge Current page Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 48: Pins Description
Charge passed element control pin BATSNS Battery voltage sense pin ISENSE ISENSE Current sense pin BATON Battery detection pin. If this pin is large than 2 5V ill di 2.5V will disable charging. Copyright © MediaTek Inc. All rights reserved.
Page 49 Charger detect, the detection threshold voltage is 4.3V at charge off state. ▪ Charger over voltage protection HW default is disable SW can customize disable, SW can customize. (Default is 7.5V) MT6252 MT6252 Copyright © MediaTek Inc. All rights reserved.
Page 50 Charger Detection Charger Detection Charger Detection Charger Detection VCDT HV VTH (valid if VCDT HV EN=1) CHRDET CHRDET VCDT_LV_VTH (always valid) Copyright © MediaTek Inc. All rights reserved.
Page 51 9.025 9.97 9.975 10.5 11.02 ▪ Other, adding below circuitry to increase a OVP path . VCHG – BATON toggle threshold is 2.5V. D202 BAT_Temp R230 R230 BATON VCHG_1_Diode 6.8K BAT54CXV3T1 R231 5.1K Copyright © MediaTek Inc. All rights reserved.
Page 52 If Q1 goes into saturation, look up the characteristic table to get the t i ti t bl t t th relationship between I and I ▪ Build in 256 steps CSDAC for current driving control. Copyright © MediaTek Inc. All rights reserved.
Page 53 Charge current =β *I_CSDEC – I CSDEC ( I_CSDEC (maximum)=14.8mA. ) 14 8 A – I_CSDEC selection • 1 LSB =55uA. Current step = 55uA*200(β )=11mA ▪ DC Current Gain(β) must be 100~300 at Ic=0.5A Copyright © MediaTek Inc. All rights reserved.
Page 54 Vbat_off > 3.4V 1. Complete msg detected rate = V_PRE2FAST_THRES 6 times Fast (CC) 2. Wait 90 seconds charge Top-off state charge state Vbat_off > 4.05V & not in talking mode V FAST2TOPOFF THRES V_FAST2TOPOFF_THRES Copyright © MediaTek Inc. All rights reserved.
Page 55 Pulse Charge Pulse Charge Charging Curve Pulse Charge Pulse Charge Charging Curve Charging Curve Charging Curve Precharge No charge state state 100mA Charger plug in Charger plug in Charging time CC mode 2hr 5min state 450 A 450mA Full state 32min Top off mode Top-off mode...
Page 56 BJT (DC Current Gain) will effect current step and accurate accurate – Smaller “DC Current Gain” get more accurate. – Too small “DC Current Gain” to charge up zero voltage battery. Vbat <1V, CSDEC will limit at 4 step(0.23mA). • Copyright © MediaTek Inc. All rights reserved.
Page 57 – VDS>30V (Depend on application) – RDS (ON) <10 ohm @ID = 10 mA, VGS = 2.5 V ▪ C200 (VCHG input cap) – If want to support VCHG up to 30V, please change CAP to 1uF/50V. Copyright © MediaTek Inc. All rights reserved.
Page 58 The trace from Rsense to battery connector should not share with The trace from Rsense to battery connector should not share with other VBAT traces. ▪ ISENSE/BATSNS should be routed as differential traces which are away from noisy signals. Copyright © MediaTek Inc. All rights reserved.
Page 61 Engineer mode range Engineer mode range 0 ~ 255 0 ~ 255 0 ~ 255 Amp Type ClassAB/D ClassD ClassAB 0~21 (Class-AB) SPK AMP gain range (dB) 12/18dB 0~22.5dB 6~27 (Class-D) gain step size 1.5dB Copyright © MediaTek Inc. All rights reserved...
Page 62 Audio Signal schematic and layout : ▪ The signal of Audio block should shielding by GND ▪ C218 GND net should connect to C3(AGND28_AFE) pad first then direct through Via to Main GND. Copyright © MediaTek Inc. All rights reserved...
Page 63 Audio Power schematic and layout : ▪ C225 GND side should connect to AGND28_AFE first then short to main GND and close to ball C9 C225 C / 1000 / nF / 0402 Copyright © MediaTek Inc. All rights reserved...
Page 64 BB located in Shielding case Shielding case 1.5K BLM15BB750SN1 100n MICP0 Microphone ADC_USB HOOK DETECTION 100p 100n HEADSET EarPhone MICN0 BLM15BB750SN1 near BB located in Shielding case 100p XMP3_L 1.5K MP3_OUTL XMP3_R MP3_OUTR 接在一起後落系統大地 EINT_HEADSET Copyright © MediaTek Inc. All rights reserved...
Page 65 ● connect EINT to MP3 OUT for cost effective solution ● connect EINT to MP3_OUT for cost effective solution ● connect to L channel to avoid POP noise when use internal SPK Amp Copyright © MediaTek Inc. All rights reserved...
Page 66 •Example for EINT status if from High (plug out) to (plug in) kal bool kal_bool aux state = LEVEL aux_state = LEVEL_HIGH; HIGH; void AUX_EINT_HISR(void) ilm_struct *aux_ilm; if (aux_state == LEVEL_LOW) #ifdef AUX_DEBUG dbg_print(" Interrupt: Plugout \n\r"); #endif Copyright © MediaTek Inc. All rights reserved...
Page 67 THD+N=1%, VDD=3.6V RL = 8Ω 500mW ▪ Although MT6252 class-AB power output is 0.85W at 8 Ω , because congenital power source limitation is 4.2V from VBAT , but compare with other discrete amplifiers , MT6252 equal but compare with other discrete amplifiers , MT6252 equal other amplifier in performance.
Page 68 1500 BLM18KG221SN1 0 05 2200 BLM18KG221SN1 0.05 2200 Murata BLM18KG331SN1 0.08 1700 BLM18SG221TN1 0.04 2500 BLM18SG331TN1 0.07 1500 BLM18EG221SN1 0.05 2000 MPZ1608S221A 0.05 2200 MPZ1608S331A MPZ1608S331A 0 08 0.08 1700 1700 MPZ1608Y221B 1500 Copyright © MediaTek Inc. All rights reserved...
Page 69 (external amp) R1(Note1) – should be “2 analog switches” between VB OP/ON and between VB_OP/ON and LSPK_OP/ON R1(Note1) – Note1: The R1+Ron of the Analog analog switch should equal to switch 12ohm Class-D Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 71 Microphone application circuit note Microphone application circuit note Microphone application circuit note Microphone application circuit note ▪ Layout consideration-Normal Layout consideration Normal 1. R302, R303, R304, R307, C311, 1. R302, R303, R304, R307, C311, C301 and C312 should be put mode close to the BB chip –...
Page 72 Microphone application circuit note Microphone application circuit note Microphone application circuit note Microphone application circuit note ▪ ▪ Layout consideration Headset Layout consideration-Headset C326 C332 R311 R310 C326, C332, R311, R310 mode should be put close to BB MICBIASP The GND of C333 and C334 Should be routed Should be routed should connect together and...
Page 73 Placement and routing Example Placement and routing Example Placement and routing Example Placement and routing Example AU_OUT0_P/N MP3_OUTL/R AU_MIC_BIAS MICP1/N1 MICP0/N0 MICP0/N0 AU_VCM cap should be as close as to the BB chip The GND of AU_VCM should be connected to pin C3 first, and then connect to the main GND by single via by single via...
Page 74 Layout rule Layout rule Layout rule Layout rule ▪ The AU VCM cap should be put The AU_VCM cap should be put close to the BB chip close to the BB chip, the trace should be as short as possible –...
Page 75 2 2 in in 1 application circuit 2 2 - - in in- - 1 application circuit 1 application circuit 1 application circuit ▪ 2 resistor 12Ω are used to 2 resistor 12Ω are used to construct the equivalent 32Ω load 32Ω...
Page 77 Parallel Image Sensor Interface Parallel Image Sensor Interface BB Chip (Pin definition) Camera side CMVREF VSYNC CMHREF HSYNC CMPCLK PCLK CMMCLK MCLK SIOD SIOD SIOC CMRST CMRST RESETB RESETB CMPDN PWDN CMDAT0~CMDAT7 DATA0 ~ DATA7 Copyright © MediaTek Inc. All rights reserved.
Page 78 Serial Image Sensor Interface Serial Image Sensor Interface BB Chip (Pin definition) Camera side MCLK Master Clock SPI Data Output SPI Clock Output I2C Data Output I2C Data Output I2C Clock Output CAMRST Reset CMPDN PWDN Copyright © MediaTek Inc. All rights reserved.
Page 81 Current can meet sensor requirement or not. For Parallel VCAMD Imax = 100mA Sensor : EMI filter cap. max. loading is 30pf For Serial sensor : EMI filter cap. max. loading is 30pf Copyright © MediaTek Inc. All rights reserved.
Page 82 Layout 5: Layout 5: Layout 3: Layout 3: Layout 4: Layout 4: Camera Digital Power Camera Digital Power Control Group Control Group Data Group Trace Data Group Trace Trace Trace Trace Trace Trace Trace Copyright © MediaTek Inc. All rights reserved.
Page 83 The sensor module’s power supplies( inductors , beads , resistors , capacitors) should be resistors , capacitors) should be placed as close as possible to the connect Copyright © MediaTek Inc. All rights reserved.
Page 84 Do not route signal traces under crystals, oscillators, clock synthesizers, magnetic devices. Route all traces over continuous planes Keep all signals clear of the core logic set. Copyright © MediaTek Inc. All rights reserved.
Page 85 2.Don’t routing the trace to cross EMIF input and output. (L1 & L2) 3.Reduce the routing trace on top layer. 4.Don’t routing the unrelated signal on L2 pad. (GND signal is OK) (GND signal is OK) Copyright © MediaTek Inc. All rights reserved.
Page 86: Single Camera
Image sensor pixel clock input Image sensor pixel clock input I2C clock output I2C data input/output Control CMRST Image sensor reset signal output CMPDN Image sensor power down signal output CMFLASH Image sensor Flash signal output Copyright © MediaTek Inc. All rights reserved.
Page 87 Max. TL0 (BB ball to Image Sensor 4,800 mils Connect) Max. (Trace length) − 500mil ≤ (Trace length) ≤ Max. Length matching (Trace length) Remark Data Group shall be routed surround with ground plan Copyright © MediaTek Inc. All rights reserved.
Page 88 4,500 mils (PCLK length − 500-mil) ≤ DQ length ≤ Length matching for Data-to- PCLK (PCLK length + 500-mil) Each clock shall be routed surround with ground plan (high priority) Remark [MCLK , PCLK] Copyright © MediaTek Inc. All rights reserved.
Page 89 Break-out/Break-in area (under the W ≥ 3-mil S ≥ 3-mil W ≥ 3 mil, S ≥ 3 mil. BGA package area) Max. TL0 6000 mils Remark Control Group shall be routed surround with ground plan Copyright © MediaTek Inc. All rights reserved.
Page 90: Dual Camera
Image sensor pixel clock input Image sensor pixel clock input I2C clock output I2C data input/output Control CMRST Image sensor reset signal output CMPDN Image sensor power down signal output CMFLASH Image sensor Flash signal output Copyright © MediaTek Inc. All rights reserved.
Page 91 Max. TL1 (Branch points to Sub 1,500 mils Image Sensor Connect) Max. (Trace length) − 500mil ≤ (Trace length) ≤ Max. Length matching(TL0+TL1) (Trace length) Remark Data Group shall be routed surround with ground plan Copyright © MediaTek Inc. All rights reserved.
Page 92 Image Sensor Connect) (PCLK length − 500-mil) ≤ DQ length ≤ Length matching for Data-to- PCLK(TL0+TL1) (PCLK length + 500-mil) Each clock shall be routed surround with ground plan (high priority) Remark [MCLK, PCLK] Copyright © MediaTek Inc. All rights reserved.
Page 93 Image Sensor Connect) Max. TL1 (Branch points to Sub 2,000 mils Image Sensor Connect) Remark Remark Control Group shall be routed surround with ground plan Control Group shall be routed surround with ground plan Copyright © MediaTek Inc. All rights reserved.
Page 94: Serial Camera
Signal Name Description Image sensor SPI data output Image sensor SPI CLK output Clock MCLK Image sensor master clock output I2C clock output Control I2C data input/output CMRST Image sensor reset signal output Copyright © MediaTek Inc. All rights reserved.
Page 95 W ≥ 3-mil, S ≥ 3-mil. BGA package area) Max. TL0 (BB ball to Image Sensor 6,000 mils Connect) Length matching in PCB 100 mils. Remark SPI Group shall be routed surround with ground plan Copyright © MediaTek Inc. All rights reserved.
Page 96 Damping resistor (R Optional, 0 or 22 Ω (Near the Image Sensor). Max. (TL0 + TL1) 6,000 mils Each clock shall be routed surround with ground plan (high priority) Remark [MCLK CSK] [MCLK, CSK] Copyright © MediaTek Inc. All rights reserved.
Page 97 Break-out/Break-in area (under the W ≥ 3-mil S ≥ 3-mil W ≥ 3 mil, S ≥ 3 mil. BGA package area) Max. TL0 6000 mils Remark Control Group shall be routed surround with ground plan Copyright © MediaTek Inc. All rights reserved.
Page 98 Route microstrip over unbroken ground or power plane. Main trace patterns (Analog Power) W ≥ 12-mil, S = 4-mil with GND trace. Analog power must be routed surround with ground plan Remark De-couple cap shall connect to main ground directly. Copyright © MediaTek Inc. All rights reserved.
Page 99 Main trace patterns (Digital Power) W ≥ 12-mil, S = 4-mil with GND trace. Digital power shall be routed surround with ground plan. Remark De-couple cap shall connect to main ground directly. (Must) Copyright © MediaTek Inc. All rights reserved.
Page 102 Connector with Card Detection Pin Connector with Card Detection Pin Reserve external PU resistors for DAT1/2/3 & MCINS in connector side Reserve ESD protection device on CMD/CLK/DAT/MCINS with Cap < 15pF VIO must always be on for hot plug detection TVS01 TVS2 TVS3 TVS4...
Page 103 Connector without Card Detection Pin Connector without Card Detection Pin - - Use DAT3 for hot Use DAT3 for hot Use DAT3 for hot plug detection Use DAT3 for hot- - plug detection plug detection plug detection Reserve external PU resistors for DAT1/2 in connector side Reserve ESD protection device on CMD/CLK/DAT/MCINS with Cap <...
Page 104 Better T Better T- - card Compatibility card Compatibility An external LDO for T-card (and MT6252 VDD33_MSDC) is suggested Output voltage: 3V3 Output current: >= 200mA LDO output rising time form 0 to 3V3 <= 50uS R1642 TF Card VBAT...
Page 105 MT6252 Example Circuit MT6252 Example Circuit Reserve external PU resistors for DAT1/2/3 in connector side Reserve ESD protection device on CMD/CLK/DAT with Cap < 15pF R1642 TF Card R1643 MCDA1 NC/R/47K/ohm/0402 R1644 J301 J301 MCDA3 MCDA3 MCDA2 NC/R/47K/ohm/0402 DAT2 MCDA3...
Page 106: Layout Guidelines
Layout Guidelines Layout Guidelines DAT, CMD, CLK 一起走若無法全部一起走，優先順序為: ((DAT + CLK) + CMD) CLK 左右要包GND，避免受到干擾 DAT, CMD, CLK 線長最大誤差控制在1000mil以內 (預估time difference在 160pS以內) 2011/1/17...
Page 108 (6252 only support 1.8V 1.8v I/O) – Support Parallel-4 LCM backlight controller ▪ Dual display feature is supported – Parallel 8/9 (main) + Parallel 8/9 (sub) – Parallel 8/9 (main) + SPI (sub) Copyright © MediaTek Inc. All rights reserved 2011/1/17...
Page 109: Parallel Interface
LED_K4 LEDK4 BLC_EN BLC_EN ▪ Touch Panel Touch Panel TP_XL TP_YD TP_XR – Connect to dedicated 4-wire R-type TP pin t t d di t d 4 TP i TP YU TP_YU Copyright © MediaTek Inc. All rights reserved 2011/1/17...
Page 110 BLC_EN BLC_EN Touch Panel TP_XL TP_YD TP_XR Note 1 : Check the correct data pins from LCM spec Note 1 : Check the correct data pins from LCM spec. TP YU TP_YU Copyright © MediaTek Inc. All rights reserved 2011/1/17...
Page 111: Serial Interface
AA17 AA17 LSDI (EA6) IOVCC LSCK (EA3) AA14 LED_A LEDA LED_K1 LEDK1 LRSTB RESET LED_K2 LEDK2 LSDA LSCE0B LSDI LSCE0B LSCK FMARK / LRSTB RESET LCD TE LCD_TE LPTE LPTE FMARK_Fsync F_Sync Copyright © MediaTek Inc. All rights reserved 2011/1/17...
Page 112 LCM Design Note LCM Design Note – – Dual LCM Dual LCM Dual LCM Dual LCM ▪ Dual LCM mode LPCE0B LPCE0B Parallel Parallel LCM 1 6252 6252 LPCE1B LSCE0B Parallel Serial LCM 2 Copyright © MediaTek Inc. All rights reserved 2011/1/17...
Page 113 Supporting 1.8V I/O LCM Supporting 1.8V I/O LCM Vendor Survey Vendor Survey On‐going 2.8v/1.8v 2 8 /1 8 Vendor compatible Vendor＇s feedback LCM Percentage • 华南地区产品超过一半的OEM型号能兼容2.8V/1.8V • 华东、华北地区客户的产品绝大部分都可以兼容2.8/1.8V。 • 之前较早时期的显示模组能够同时兼容之前较早时期的显示模组，能够同时兼容2.8V/1.8V的比例的比例会少一些 • 标准品超过90%会做2.8V/1.8V的IOVCC兼容(仅在某款产品是 1 Truly > 90% 在依据某一客户具体要求而开的标准品中才会出现仅仅支持 2.8V的情况) • • OEM型号，则看客户的要求，之前部分客户的主板只能提...
Page 114 This LCM has only “One Power Pins” (no separated VCI and IOVCC power pins) – Supply voltage allows 3V only which means IO level can’t support 1.8V VDD, = 3V typical Non-separate power pin Only one pin Separate power pin Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 115 MTK LCM IO Level Trend ▪ MTK recommend LCM connection d LCM Data bus Data bus Baseband Baseband VMEM 2.8V 1.8V 2.8V LCD Driver LCD Driver LCD Driver LCD Driver VCI=2.8V IOVCC=1.8V VCI=IOVCC=2.8V Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 117 Outline Outline Outline Outline ▪ Reference design Reference design ▪ META tools ▪ Key RF components ▪ ▪ Modify BPI and timing for MT6252 Modify BPI and timing for MT6252 Copyright © MediaTek Inc. All rights reserved. 2008/06...
Page 119 Quad Quad band Schematic Quad Quad- - band Schematic band Schematic band Schematic MT6252 RF part R SAW Rx SAWs TXM RF7170 X’TAL X’TAL Copyright © MediaTek Inc. All rights reserved. 2008/06...
Page 121 •Select PA type in the scroll 4. Other settings : •Select GMSK and/or EPSK mode •AFC type is Crystal 5. Select instrument : •Select CMU or 8960 •De-select Reset CMU200 De-select Reset CMU200 6. Start calibration Copyright © MediaTek Inc. All rights reserved. 2008/06...
Page 122 4. Other settings : •Select GMSK and/or EPSK mode •AFC type is Crystal 5. Select instrument : •Select CMU or 8960 •De-select Reset CMU200 De-select Reset CMU200 6. Select FHC 7. Start calibration Copyright © MediaTek Inc. All rights reserved. 2008/06...
Page 123 Calibration File and Initial Files Calibration File and Initial Files Calibration file (traditional calibration) MT6252.CFG Initial file (traditional calibration) MT6252.ini Copyright © MediaTek Inc. All rights reserved. 2008/06...
Page 125 – Characteristics: Insertion loss/Attenuation/Isolation – System Performance: Under normal and extreme conditions System Performance: Under normal and extreme conditions RMS and peak phase error/Frequency error/ORFS/Switching transient • Sensitivity/Blocking • Spurious emission • Copyright © MediaTek Inc. All rights reserved. 2008/06...
Page 126 PinOut PinOut of MT6252 (Same as MT6253) of MT6252 (Same as MT6253) HBTx LBTx RX(HB) RX(LB) Diplexer RX Diplexer RX Diplexer RX Diplexer RX Please turn on SWAP HB LB HB LB EGSM GSM850 EGSM GSM850 function for diplexer function for diplexer...
Page 127 1 in 4 out 1.8x1.4 t 1 8 1 4 MT6253 MT6253 schedule with engineers 1800/1900 No products, checking develop 850/900 Hitachi Media 1 in 4 out 1.8x1.4 MT6253 schedule with engineers 1800/1900 Copyright © MediaTek Inc. All rights reserved. 2008/06...
Page 128 •Note : Th t The target is these RF external components should be the same as 6253, but this t i th ld b th 6253 b t thi qualify schedule is TBD Copyright © MediaTek Inc. All rights reserved. 2008/06...
Page 129 Approved ▪ Note: Don’t use MT6139/MT6140’s, AD6548 Crystal for MT6252. ▪ Note : The target is these RF external components should be the same as 6253, but this qualify schedule is TBD Copyright © MediaTek Inc. All rights reserved. 2008/06...
Page 135 ⇒ L2 RF trace, ⇒ L2 RF trace, (strip line, Ref. GND plane: L1 or L3) ⇒ control line ⇒ Power line ⇒ Bottom layer RF trace BOTTOM (Microstrip line, Ref. GND plane: L3) (L4) Copyright © MediaTek Inc. All rights reserved. 2008/06...
Page 137 1. Crystal place as close as possible to MT6252 PIN XTAL (G23) Crystal 2. Crystal and its trace directly refer to global ground , keep out L1&L2 ground 3. Crystal ground pin directly connect to global ground , do not connect to...
Page 138 4. PIN XTAL_GND (H22) is directly connected to global ground 5. PIN FREF (J22) should be shielded in inner layer, and its via should keep far away from Pin XTAL(G23) and trace Copyright © MediaTek Inc. All rights reserved. 2008/06...
Page 141 GND keep at least larger than 4 time of differential pair distance, r>4xd 9 Avoid GND split under MT6252 especially for L2 9. Avoid GND split under MT6252 , especially for L2 Copyright © MediaTek Inc. All rights reserved. 2008/06...
Page 142 10. AVDD28_RF1 (C17) & AVDD28_RF2 (E21&E22) bypass cap. place as close as possible to MT6252 ibl t MT6252 11. GND of AVDD28_RF1 (C17) & AVDD28_RF2 (E21 & E22) decoupling cap is directly connected to global ground 12. Place AVDD28_TCXO (H20) bypass cap. as close as...
Page 143 GND protection. Avoid power trace or other trace routing parallel with clock and data other trace routing parallel with clock and data. 15. Place memory as close as possible to MT6252 Copyright © MediaTek Inc. All rights reserved. 2008/06...
Page 145 L1_custom_rf .h file ▪ PA control logic and schematic of RF module ▪ Due the BPI amount of MT6252 is less than MT6253, it is necessary to modify “Vlogic” pin to BPI_BUS 1 ▪ Defunded function of BPI Copyright © MediaTek Inc. All rights reserved.
Page 146 PT3 (31 Qb) Dummy Dummy TX mode Return to idle • • • • Idle Idle TRSW, Band SW, PA EN Idle • BSI CLK=26MHz TX EN • Send CW2 first in ST0 TX FS PT2B APCMID APCOFF APCCON APCDACCON Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 147 • • • CW1: SX N divider CW96: RX gain CW2: mode=000, mode = 010 TRX=10 • CW57: Set AFC value PR1 (40 Qb) PR2 (33 Qb) PR3 (6 Qb) Dummy Dummy Return to idle • • • Idle TRSW, Band SW, PA EN Idle RX EN RX FS Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 151 Example for GSM PR1 Example for GSM PR1 Example for GSM_PR1 Example for GSM_PR1 Idle Binary: 0000 0000 0000 Hexadecimal: Transform PDATA_GSM_PR1 PDATA_IDLE Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 152 Example for GSM PR2 Example for GSM PR2 Example for GSM_PR2 Example for GSM_PR2 TRSW, Band SW Binary: 0000 0000 0010 Hexadecimal: Transform PDATA_GSM_PR2 Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 153 Example for GSM PR3 Example for GSM PR3 Example for GSM_PR3 Example for GSM_PR3 Return to Idle Binary: 0000 0000 0000 Hexadecimal: Transform PDATA_GSM_PR3 PDATA_IDLE Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 154 Example for GSM PT1 Example for GSM PT1 Example for GSM_PT1 Example for GSM_PT1 Idle Binary: 0000 0000 0000 Hexadecimal: Transform PDATA_GSM_PT1 PDATA_IDLE Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 155 Example for GSM PT2 Example for GSM PT2 Example for GSM_PT2 Example for GSM_PT2 Idle Binary: 0000 0000 0000 Hexadecimal: Transform PDATA_GSM_PT2 PDATA_IDLE Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 156 Example for GSM PT2B Example for GSM PT2B Example for GSM_PT2B Example for GSM_PT2B PT2B TRSW BANDSW_DCS PAEN on PAEN on Binary: 0000 0001 0010 Hexadecimal: Transform PDATA_GSM_PT2B 0x12 Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 157 Example for GSM PT3 Example for GSM PT3 Example for GSM_PT3 Example for GSM_PT3 Return to Idle Binary: 0000 0000 0000 Hexadecimal: Transform PDATA_GSM_PT3 PDATA_IDLE Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 158 Example for DCS PR1 Example for DCS PR1 Example for DCS_PR1 Example for DCS_PR1 Idle Binary: 0000 0000 0000 Hexadecimal: Transform PDATA_DCS_PR1 PDATA_IDLE Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 159 Example for DCS PR2 Example for DCS PR2 Example for DCS_PR2 Example for DCS_PR2 TRSW, Band SW Binary: 0000 0000 0011 Hexadecimal: Transform PDATA_DCS_PR2 Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 160 Example for DCS PR3 Example for DCS PR3 Example for DCS_PR3 Example for DCS_PR3 Return to Idle Binary: 0000 0000 0000 Hexadecimal: Transform PDATA_DCS_PR3 PDATA_IDLE Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 161 Example for DCS PT1 Example for DCS PT1 Example for DCS_PT1 Example for DCS_PT1 Idle Binary: 0010 0000 0000 Hexadecimal: Transform PDATA_DCS_PT1 PDATA_IDLE Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 162 Example for DCS PT2 Example for DCS PT2 Example for DCS_PT2 Example for DCS_PT2 Idle Binary: 0000 0000 0000 Hexadecimal: Transform PDATA_DCS_PT2 PDATA_IDLE Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 163 Example for DCS PT2B Example for DCS PT2B Example for DCS_PT2B Example for DCS_PT2B PT2B TRSW BANDSW_DCS PAEN on PAEN on Binary: 0000 0001 0011 Hexadecimal: Transform PDATA_DCS_PT2B 0x13 Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 164 Example for DCS PT3 Example for DCS PT3 Example for DCS_PT3 Example for DCS_PT3 Return to Idle Binary: 0000 0000 0000 Hexadecimal: Transform PDATA_DCS_PT3 PDATA_IDLE Copyright © MediaTek Inc. All rights reserved. 2011/1/17...
Page 165 The difference between APC off and PT3 is 26QB – Due the transceiver architecture deference, SR timing have to be modified. ▪ – BPI is expressed by hexadecimal, but edited by binary Copyright © MediaTek Inc. All rights reserved. 2011/1/17...

MEDIATEK MT6252 Design Manual

Quick Links

Related Manuals for MEDIATEK MT6252

Summary of Contents for MEDIATEK MT6252