MEDIATEK MT6236 Instruction Manual

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MT6236 Design Notice V0.2

2010/10

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Summary of Contents for MEDIATEK MT6236

Page 2: Revision History
3. Add FM De-Sense Layout Guide Issue Case Study Issue Case Study 1. Add Issue Case Study - 1 : MSDC IOT issue 2. Add Issue Case Study - 2 : EINT 7~9 MUX issue Copyright © MediaTek Inc. All rights reserved.
Page 3 Outline Outline ▪ MT6236 Features Overview & Package ▪ Major hardware difference between MT6236 & MT6235 ▪ Design Notice – – Pulse Charging – Bluetooth – – Audio/Speech – GPIO Selection – ADC/TP ADC/TP – External Memory Interface – Camera –...
Page 4 SBC encoder capability with Bluetooth A2DP SBC encoder capability with Bluetooth A2DP function ▪ Package size: 12.5x12.5 mm ,382 balls ▪ Advanced DSP acoustic functionality TFBGA with 0.5 mm pitch – AEC and noise reduction Copyright © MediaTek Inc. All rights reserved.
Page 5 MT6236 Package MT6236 Package Ball Ball Total Stand Mold Substrate Package Body Size Ball Pitch Count Width Thickness Thickness Thickness A (Max.) TFBGA TFBGA 0.27~ 0.16~ 12.5 12.5 0.65 0.26 Copyright © MediaTek Inc. All rights reserved. 0.37 0.26...
Page 6 Major HW difference between MT6236 & MT6235 Refer to section of Function MT6235 MT6236 MT6236 Design Notice 13x13mm 12.5x12.5mm Package Package Package Package TFBGA/362 b ll TFBGA/362 ball TFBGA/382 b ll TFBGA/382 ball GPIO pins 75 GPIOs 67 GPIOs GPIO selection (Power domain &...
Page 7 Major HW difference between MT6236 & MT6235 Refer to section of Refer to section of Function MT6235 MT6236 MT6236 Design Notice General Fold-back current limit Need near-end & far-end Need only far-end (besides bypass cap bypass cap VCORE/VM/VRF/VCAMA) Vout & Imax Vout &...
Page 9 Content Content Content ▪ MT6236 Introduction MT6236 Introduction – General description – Block diagram Block diagram – Buck/Boost/LDO list ▪ ▪ Comparison Comparison ▪ Function Description ▪ Reference design ▪ Appendix ppe d Copyright © MediaTek Inc. All rights reserved...
Page 10 MT6236 Introduction MT6236 Introduction – – General description General description ▪ The MT6236 is built-in high performance power management IC. ▪ Highly integrated functions fulfill all power requirement in handset system system – Buck converter – LDO Analog LDO •...
Page 11: Block Diagram
MT6236 Introduction MT6236 Introduction – – Block Diagram Block Diagram Current Sink *5 Backup Battery Module DC-DC Vcore1 1.2(0.9_1.3V)/350mA (For Vcore) Base Band Processor Boost Controller DC-DC Vm 1.8V/300 mA 1. Back Light (For Vmem) Essential LDOs VIO_2.8V/100mA Flash VA_2.8V/125mA Memory VRTC_2.8V/2mA...
Page 12 Far-end bypass cap 1.3/1.5/1.8/2.5/2.8/3.0/3.3 Far-end bypass cap VUSB Far-end bypass cap VSIM 1.8/3.0 Far-end bypass cap 1.3/1.5/1.8/2.5 VSIM2 Far-end bypass cap 2.8/3.0 1.3/1.5/1.8/2.5/2.8/3.0/3.3 Far-end bypass cap VIBR 1.3/1.5/1.8/2.5/2.8/3.0/3.3 Far-end bypass cap VRTC 0.1uF Backup battery Copyright © MediaTek Inc. All rights reserved...
Page 13 Content Content Content Content ▪ MT6236 Introduction MT6236 Introduction ▪ Comparison ▪ Function Description ▪ ▪ Reference design Reference design ▪ Appendix Copyright © MediaTek Inc. All rights reserved...
Page 14 Protection Limit Vout I_max Vout I_max 1.2/0.9 1 2/0 9 1.2/0.9 VCORE (Buck + LDO Buck (DC/DC) Mode) Converter x (LDO mode) Vout I max Vout I max VTCXO Analog VCAMA 1.5/1.8/2.5/2.8 1.5/1.8/2.5/2.8 Copyright © MediaTek Inc. All rights reserved...
Page 15 VRTC 1.5/1.2 0.02 BAT_BACKUP Boost 20mA/21V LED KP LED_KP 150mA (8 steps) 150mA (8 steps) 150mA 150mA VIBRATOR 250mA x (LDO mode) Driver 5 x (24mA, 0.25V), Sharing Current Sink (Individual Current/Enable control) Copyright © MediaTek Inc. All rights reserved...
Page 16 Charger type Linear charger Pulse chager Maximum Input Voltage Voltage Maximum Charging Programmable Voltage Charger 4.35 CC Mode 160mV/Rsense 160mV/Rsense Pre-Charge Mode 100mA 50mA/100mA Battery Detection V(NTC Pin) V(NTC Pin) Watchdog Timer SIM_LS Copyright © MediaTek Inc. All rights reserved...
Page 17 Content Content Content Content ▪ MT6236 Introduction MT6236 Introduction ▪ Comparison ▪ Function Description – Power on timing – Buck – Boost – Driver – Audio AMP ▪ Reference design ▪ Appendix Copyright © MediaTek Inc. All rights reserved...
Page 18 Function Description Function Description - - Power On/OFF Timing Control Power On/OFF Timing Control Power On/OFF Timing Control Power On/OFF Timing Control Charger Plug-in Press PWRKEY Copyright © MediaTek Inc. All rights reserved...
Page 19 LDO mode for lower cost CORE requirement. – VCORE (Buck/LDO: 350mA/300mA) – (Buck/LDO: 300mA/200mA) (Buck/LDO: 300mA/200mA) ▪ Buck mode: VCORE_FB/VM_FB connect to the output capacitor. ▪ LDO mode: VCORE_FB/VM_FB connect to VBAT. Copyright © MediaTek Inc. All rights reserved...
Page 20 Function Description - - Boost Controller Boost Controller Boost Controller Boost Controller ▪ LCM backlight LED: – Boost Controller for Serial mode LED (4~6) Use external NMOS to boost the voltage to higher level. • Copyright © MediaTek Inc. All rights reserved...
Page 23 Function Description Function Description – – Current sink for backlight Current sink for backlight Current sink for backlight Current sink for backlight Backlight Copyright © MediaTek Inc. All rights reserved...
Page 26 Content Content Content Content ▪ MT6236 Introduction MT6236 Introduction ▪ Comparison ▪ Function Description ▪ Reference design – Schematic ▪ Appendix Copyright © MediaTek Inc. All rights reserved...
Page 27: Typical Application
4~6 series LEDs for BL Driver Driver Current sink Current sink 100mA 100mA Max 5 parallel LEDs for BL Max. 5 parallel LEDs for BL 150mA KP_LED KEYPAD Audio Class D 0.9W at 4.2V Single Channel Amplifier Copyright © MediaTek Inc. All rights reserved...
Page 28: Reference Design
Please reserve 1k resistor on phone PCB to protect PWRKEY no matter if PWRKEY connect to any I/O connector or not. Please reserve 1k resistor on phone PCB to protect BAT ON pin if PCB to protect BAT_ON pin if BAT_ON is used to detect battery. Copyright © MediaTek Inc. All rights reserved...
Page 29 IC Protection: VBAT IC Protection: VBAT IC Protection: VBAT IC Protection: VBAT MT6236 has lower VBAT voltage rating. (Max. 4.3V.) Some protection should reserve to prevent the damage by voltage surge prevent the damage by voltage surge. •Design notice in Phone side: 1.
Page 30 ▪ Ir<100uA @Vr=4.2V, Ta=25°C, Using 5.1V zener will introduce some leakage when VBAT = 4 2V Large Ir introduce some leakage when VBAT = 4.2V. Large Ir current will introduce more leakage current. Copyright © MediaTek Inc. All rights reserved...
Page 31 – 150mW zener has similar current sink capability, can only release part of the external pulse energy. t f th – 500mW zener can share more than 90% of external energy. Bypass surge energy with external capacitor and zener diode. MT6236 Copyright © MediaTek Inc. All rights reserved...
Page 32 4 P i 4 Prisemi PZ5D4V2H PZ5D4V2H SOD523 SOD523 4 85 4.85 500 W 500mW Email: ken.ou@prisemi.com Mike_Wang 5 Vishay MMSZ4689-V SOD123 886-911313660 500mW mike.wang@Vishay.com 陳富榮Sam 138-12888205 500mW Crownpo CDZ55C5V1SM 0805 10.2 Email: sam@sh-selmag.com Copyright © MediaTek Inc. All rights reserved...
Page 33 . For thermal dissipation concern, SOD-123 and SOD-323 are fist choice and then SOD-523. ▪ For safety operation area, please notice the steady state power rerating and should exposed pad to a large copper. SOD-123/ SOD-323 SOD-323 SOD-123 Copyright © MediaTek Inc. All rights reserved...
Page 34 VBAT input should reserve enough filter to prevent interference to RF performance VBAT input should reserve enough filter to prevent interference to RF performance. ▪ All bypass cap. should be as close to MT6236 IC as possible ▪ Bead selection: Rated Current > 1000mA, DCR < 0.10ohm...
Page 35 Reference design Reference design - - Schematic Schematic Bypass Capacitor: Bypass Capacitor: Vcore Vcore and VM and VM ▪ Reserve enough bypass capacitors both at Vcore and VM to obtain good system stability. Copyright © MediaTek Inc. All rights reserved...
Page 36 Reference design - - Schematic Schematic Bypass Capacitor for AVDD and VDD Bypass Capacitor for AVDD and VDD ▪ Reserve 0 ohm resistor for audio quality. ▪ Reserve 1uF for I/O power input. Copyright © MediaTek Inc. All rights reserved...
Page 37 All th t All the traces from IC to 2 IC t 2 stage filter should not exposed to prevent filt interference to RF performance. ▪ Bead selection: Rated Current > 1200mA, DCR < 0.10ohm Copyright © MediaTek Inc. All rights reserved...
Page 38 CL190Y G CL190Y G ISINK0 ISINK0 ISINK1 ISINK1 ISINK1 ISINK2 ISINK2 ISINK3 ISINK3 ISINK4 ISINK4 • Width and length of trace of ISINK0~4 should be consist between IC and LCM • voltage table Copyright © MediaTek Inc. All rights reserved...
Page 39 Boost Controller For Serial Backlight LCM Boost Controller For Serial Backlight LCM Boost Controller For Serial Backlight LCM ▪ Reserve L212 to prevent interference to FM performance. ▪ Bead selection: Impedance> 600 ohm@100MHz Copyright © MediaTek Inc. All rights reserved...
Page 41: Pulse Charging
Support low cost linear and Nokia adaptor charger(9.3V) – Meet 2010 China charger standard(12V OVP) – CC mode current control – Constant current pre-charging – Charger OVP and battery OVP – Pre-charge/CC safety timer – Watchdog timer Copyright © MediaTek Inc. All rights reserved.
Page 42 Pre_ charge 4 3V 4.3V 4 3V 4.3V 4 35V 4.35V B tt Battery OVP Watchdog timer 50 minutes Pre-charge safety timer timer P-MOSFET +SD P-MOSFET +SD BJT+ N-MOSFET Passed element Pre-charge/CC overlap overlap Copyright © MediaTek Inc. All rights reserved.
Page 43 Design Notice – – Charge Current Setting Charge Current Setting Charge Current Setting Charge Current Setting MT6318 MT6223 MT6235 MT6236 Sense Resistor 0.2 Ohm 0.2 Ohm 0.2 Ohm 0.1 Ohm 0.2 Ohm Pre-Charge 62.5 62.5 62.5 62.5 62.5 Copyright © MediaTek Inc. All rights reserved.
Page 44 4mil ISENSE Current sense Resistor R211 R213 J201 40mil 4mil VBAT VBAT BAT_TY PE AUX_IN4 R215 BC-4565-M-03-01-LF MLV200 TVS200 **Latest schematic please refer to reference design **Latest schematic please refer to reference design. Copyright © MediaTek Inc. All rights reserved.
Page 45: Pins Description
VDRV Charge passed element control pin BATSNS BATSNS B tt Battery voltage sense pin ISENSE Current sense pin BATON Battery detection pin. If this pin is large than 2.5V will disable charging. Copyright © MediaTek Inc. All rights reserved.
Page 46 Charger detect, the detection threshold voltage is 4.3V at charge off state. ▪ Charger over voltage VCHG protection HW default is disable SW can customize disable, SW can customize. (Default is 7.5V) MT6236 Copyright © MediaTek Inc. All rights reserved.
Page 47 Charger Detection Charger Detection Charger Detection Charger Detection VCDT HV VTH (valid if VCDT HV EN=1) CHRDET CHRDET VCDT_LV_VTH (always valid) Copyright © MediaTek Inc. All rights reserved.
Page 48 9.025 9.97 9.975 10.5 11.02 ▪ Other, adding below circuitry to increase a OVP path . VCHG – BATON toggle threshold is 2.5V. D202 BAT_Temp R230 R230 BATON VCHG_1_Diode 6.8K BAT54CXV3T1 R231 5.1K Copyright © MediaTek Inc. All rights reserved.
Page 49 If Q1 goes into saturation, look up the characteristic table to get the t i ti t bl t t th relationship between I and I ▪ Build in 256 steps CSDAC for current driving control. Copyright © MediaTek Inc. All rights reserved.
Page 50 Charge current =β *I_CSDEC – I CSDEC ( I_CSDEC (maximum)=14.8mA. ) 14 8 A – I_CSDEC selection 1 LSB =55uA. Current step = 55uA*200(β )=11mA • ▪ DC Current Gain(β) must be 100~300 at Ic=0.5A Copyright © MediaTek Inc. All rights reserved.
Page 51 CS_VTH =>PCHR_AUTO PCHR AUTO (A t (Auto mode) – CS_VTH =>DAC_EN ▪ ▪ Programmable soft start Programmable soft start – CSDAC_STP – CSDAC_DLY CS_VTH CS DET CS_DET DAC-1 DAC++ CSDAC_STP CSDAC DLY CSDAC_DLY Copyright © MediaTek Inc. All rights reserved.
Page 52 Interrupt Interrupt Interrupt Interrupt Charger watch chrwdt flag & chrwdt_flag & chrwdt_int_en Over voltage Charger detect protect (ovp) ( h d t) (chr_det) BAT_OV_DEG CHRDET interrupt interrupt Copyright © MediaTek Inc. All rights reserved.
Page 53 – Accumulate 6 times PMU CV status = 1 (VBAT >= VBAT_CV_VTH ) ▪ Charging complete – >CV after waiting 90secs or 30mins time out >CV after waiting 90secs or 30mins time out ▪ Pause: talking state Copyright © MediaTek Inc. All rights reserved.
Page 54 >4.05V and V_PROTECT_L ICHG < 120mA mode in talking OW_LI mode Vbat_off > 3.4V I_TOPOFF2FULL_THRES V_PRE2FAST_THRES Fast (CC) charge Top-off (CV) state charge state Vbat_off > 4.05V & not in talking mode V_FAST2TOPOFF_THRES Copyright © MediaTek Inc. All rights reserved.
Page 55 Vbat_off > 3.4V 1. Complete msg detected rate = V_PRE2FAST_THRES 6 times Fast (CC) 2. Wait 90 seconds charge Top-off state charge state Vbat_off > 4.05V & not in talking mode V FAST2TOPOFF THRES V_FAST2TOPOFF_THRES Copyright © MediaTek Inc. All rights reserved.
Page 56 Pulse Charge Pulse Charge Charging Curve Pulse Charge Pulse Charge Charging Curve Charging Curve Charging Curve Precharge No charge state state 100mA Charger plug in g p g Charging time CC mode 2hr 5min state 450 A 450mA 1hr 32min Re-Charging TOP-off mode state...
Page 57 BJT (DC Current Gain) will effect current step and accurate accurate – Smaller “DC Current Gain” get more accurate. – Too small “DC Current Gain” to charge up zero voltage battery. Vbat <1V, CSDEC will limit at 4 step(0.23mA). • Copyright © MediaTek Inc. All rights reserved.
Page 58 – VDS>30V (Depend on application) – RDS (ON) <10 ohm @ID = 10 mA, VGS = 2.5 V ▪ C200 (VCHG input cap) – If want to support VCHG up to 30V, please change CAP to 1uF/50V. Copyright © MediaTek Inc. All rights reserved.
Page 59 The trace from Rsense to battery connector should not share with The trace from Rsense to battery connector should not share with other VBAT traces. ▪ ISENSE/BATSNS should be routed as differential traces which are away from noisy signals. Copyright © MediaTek Inc. All rights reserved.
Page 61 - BT/WiFi Dual antenna : R903=1-2 For BT conductive performance testing - BT/WiFi Single antenna : R903=2-3 [Important !!] BT PA De-coupling Cap. - Must close to MT6236 IC BT RF Trace Keep 50 ohm impedance [Important !!] BT RF matching network and BPF...
Page 62 MT6236 BT Interface Design (1/2) MT6236 BT Interface Design (1/2) Since the MT6236 features a highly integrated Bluetooth transceiver Since the MT6236 features a highly integrated Bluetooth transceiver, no need external interface no need external interface to connect with Host .
Page 63 GPIO configure should also be careful to prevent unwanted leakage. GPIO configure should also be careful to prevent unwanted leakage. MT6236 CDMA MT6236 PTA interface MT6236 PTA interface. – MT6236 supports Two-wire and Proprietary One-wire protocol with proper configurations. MT6236 MT5921 Request BT_PRI GPIO15 or 64 Signal GPIO...
Page 64 L3 of PCB. RF2G_N (Ball D17) : Layer 1 Don’t connect with other GND on L1 and L2. Layer 2 Layer 3 RF2G_N (Ball D17) : Directly connect to L3 GND plane GND plane. Copyright © MediaTek Inc. All rights reserved.
Page 65 For other decoupling cap. should be place as close to chip as possible. RF trace. Kept the star-connection for VBT. 26MHz Clock : The clock trace keep as short as possible. MUST If using co-clock with RF, the clock trace MUST shielded by GND planes. Copyright © MediaTek Inc. All rights reserved.
Page 66 MT6236 BT External Clock Sharing MT6236 BT External Clock Sharing MT6236 BT has two options for system clock source MT6236 BT has two options for system clock source. – The one is for one-pin crystal input – The other is for external clock input...
Page 67 Transceiver trace routing rule – Have VCXO power good decouple and clean ground. ▪ Using MTK recommended OG Xtal d d OG Xt l ▪ Reserve BT X’tal footprint for backup. 26MHz to BT Ground Ground Copyright © MediaTek Inc. All rights reserved.
Page 68 Reserve enough distance between the antenna, ground and the shielding case. ▪ Ground blue screw holes, and don’t ground screw holes. Good Feed point screw hole locations Shielding case > 3 mm screw hole > 3 mm locations Copyright © MediaTek Inc. All rights reserved.
Page 70 (2) USB2.0 High Speed : PASS without R389, R390 (R389, R390 will impact USB2.0 test, please remove R389, R390 during USB testing) UTXD1 R389 J1606 USB_DP USB_DM USB_PWR VUSB R390 Micro USB conn URXD1 <3pF <3pF Copyright © MediaTek Inc. All rights reserved.
Page 71 General HS eye diagram is shown as below The output swing is General HS eye diagram is shown as below. The output swing is differential 0.4V. Bad eye diagram will lead to certification fail or signal integrity problem. Copyright © MediaTek Inc. All rights reserved...
Page 72 Design Notice – – USB (3/10) USB (3/10) ● USB / UART share-pad ▪ MT6236 implement USB_DP/DM & UART1 TX/RX share-pad , power domain = AVDD33 USB (3V3) AVDD33_USB (3V3) – Advantage : Don’t need to add analog switch to switch USB and UART1 path while using MicroUSB connector.
Page 73 USB t t h t t < 10mil 10 il Test points Failure to maintain parallelism put on trace of USB2.0 data lines Ground or Power plane Don’t cross Avoid creating stubs plane splits Copyright © MediaTek Inc. All rights reserved...
Page 74 (for example: ESD issue) please keep the stub as short as unavoidable (for example: ESD issue), please keep the stub as short as possible. Avoid creating stubs if possible Proper way to connect resistors or varistors Copyright © MediaTek Inc. All rights reserved...
Page 75 DP/DM 90 ohm Place close to IC TVS on DP/DM < 3pF for diff differential ti l USB 2.0 high speed Put 1uF capacitor(C240/C249) for USB PHY power source for USB PHY power source Copyright © MediaTek Inc. All rights reserved.
Page 76 Disable USB 2.0 High Speed Support at make file USB2.0_HS_SUPPORT = FALSE # TRUE, FALSE # True to enable USB High Speed The loading for USB 1.1 full speed should follow Universal Serial Bus Specification 7.1.2, <50pF Copyright © MediaTek Inc. All rights reserved...
Page 77 To pass dead battery pre-connect current on USB ECN, have to larger the 0.2 ohm Rsense on charger to reduce pre-charge current larger the 0.2 ohm Rsense on charger to reduce pre charge current under 100mA. Copyright © MediaTek Inc. All rights reserved.
Page 78 HS mode but d h k bl HS d b t f il fail transmission due to too much CRC error. ▪ Can’t implement auto switch HS/FS mode at de ice side device side. Copyright © MediaTek Inc. All rights reserved...
Page 79 ▪ Mediatek strongly suggest customer use USB connectors compliance with Mini USB Micro USB standard. – Mediatek provide USB 2.0 high speed signal quality test service if using Mini USB Micro USB connector. – Will checked by qualified USB cables.
Page 81 Design Notice – – Audio (1/9) Audio (1/9) ● A di Bl Audio Block diagram : k di Class-D Speaker only When Voice data through earphone output Audio DAC replace Audio DAC replace Voice DAC Copyright © MediaTek Inc. All rights reserved...
Page 82 Design Notice Design Notice – – Audio (2/9) Audio (2/9) ● A di Si Audio Signal schematic and layout : ▪ The signal of Audio block should shielding by GND Copyright © MediaTek Inc. All rights reserved...
Page 83 Audio Power schematic and layout : ▪ C255 and C261 GND side should connect to AVSS28_AFE first then short to GND ▪ C255, C261, C266 should close to ball K2, T4 and J4 Copyright © MediaTek Inc. All rights reserved...
Page 84 Not plug-in ot p ug EINT1 through Audio Jack (pin 3-5 connection) to R317 to GND. pull low ● Step 2 : earphone (Audio Jack pin 3-5 dis-connected) Plug-in EINT 1 pull high Copyright © MediaTek Inc. All rights reserved...
Page 85 •Example for EINT status if from High (plug out) to (plug in) kal bool kal_bool aux state = LEVEL aux_state = LEVEL_HIGH; HIGH; void AUX_EINT_HISR(void) ilm_struct *aux_ilm; if (aux_state == LEVEL_LOW) #ifdef AUX_DEBUG dbg_print(" Interrupt: Plugout \n\r"); #endif Copyright © MediaTek Inc. All rights reserved...
Page 86 THD+N=1%, VDD=3.6V RL = 8Ω 500mW ▪ Although MT6236 class-D power output is 0.85W at 8 Ω , because congenital power source limitation is 4.2V from VBAT , but compare with other discrete amplifiers , MT6236 equal but compare with other discrete amplifiers , MT6236 equal other amplifier in performance.
Page 87 Design Notice – – Audio (7/9) Audio (7/9) ● ● Internal Class-D Audio Amplifier : Internal Class-D Audio Amplifier : ▪ C206, C208 and DVSS43_SPK need to connect to GND by single point by single point Copyright © MediaTek Inc. All rights reserved...
Page 88 ● Internal Class-D Audio Amplifier : Internal Class-D Audio Amplifier : ▪ The placement of L209 and L210 should be closed to MT6236 ▪ The trace width of SPK_P and SPK_N should be greater than 25 mil ▪ The Net of SPK_P and SPK_N should be shielded by GND ▪...
Page 89 : ▪ When use the external audio amp for stereo application, place the amp close to speaker amp close to speaker. ▪ Bead300 and Bead301 should be close to external audio amp Copyright © MediaTek Inc. All rights reserved...
Page 90 4. GND of T305 and T306 should ESD9X5.0ST5G be connected together and then to the GND then to the GND R307 5. GND of R307should connect to the main GND by a single via Copyright © MediaTek Inc. All rights reserved.
Page 91 R311 100p 1.5K headset should connect C332 100n MICP1 MIC_HP together and then to the main C333 C334 GND by single via C327 should be put close to R314 ADC3 ACC ADC3_ACC microphone Copyright © MediaTek Inc. All rights reserved.
Page 92 Connect the GND of these MT6268 caps to the main GND MT6236 VREF (Bandgap instead of the ground at and other d th output) th t the top / bottom layer / b tt projects afterwards Copyright © MediaTek Inc. All rights reserved.
Page 93 (MT6236 build-in or external amp) R1(Note1) – should be “2 analog switches” between VB OP/ON and between VB_OP/ON and LSPK_OP/ON R1(Note1) – Note1: The R1+Ron of the Analog analog switch should equal to switch 12ohm Class-D Copyright © MediaTek Inc. All rights reserved.
Page 95 GPIO [65:67] VSIM2 3. Please choose suitable GPIO for peripheral IC : ▪ Please choose GPIOs with matched direction, pull-up/pull-down, data inversion, data output, gpio mode after reset state for peripheral IC application Copyright © MediaTek Inc. All rights reserved.
Page 96 For Mode 0/1, please connect DVDD_MC2 (ball C14) to VIO (ball B5) For Mode 2 please connect DVDD MC2 to external LDO For Mode 2, please connect DVDD_MC2 to external LDO For Mode 3, please connect DVDD_MC2 to VMC (ball E8) Copyright © MediaTek Inc. All rights reserved.
Page 97 TCTIRQ2 TCTIRQ2 DVDD CAM DVDD_CAM 1 8V/2 8V 1.8V/2.8V 2 4 6 8 10 12 14 16 2,4,6,8,10,12,14,16 ● Generally connect to VCAMA or VCAMD (should Copyright © MediaTek Inc. All rights reserved. same with Camera device IO power domain)
Page 98 IRDA_TXD GPIO55 IRDA_TXD PWM3 TDMA_FS DVDD28 2.8V 4,8,12,16 IRDA_RXD GPIO56 IRDA_RXD PWM4 UCTS1 DVDD28 2.8V 4,8,12,16 IRDA_PDN GPIO57 IRDA_PDN PWM5 URTS1 DVDD28 2.8V 4,8,12,16 ● Be careful the reset state of GPIO [56:57] Copyright © MediaTek Inc. All rights reserved.
Page 99 MC1INS MC1INS DVDD PCM DVDD_PCM 1 8V/2 8V 1.8V/2.8V 2 4 6 8 10 12 14 16 2,4,6,8,10,12,14,16 DAISYNC GPIO51 DAISYNC MC1DA1 NCE1B DVDD_PCM 1.8V/2.8V 2,4,6,8,10,12,14,16 ● Generally connect to VIO (ball B5) Copyright © MediaTek Inc. All rights reserved.
Page 100 These pins will automatically pull down when set in GPIO input mode These pins will automatically pull down when set in GPIO input mode. The pull down is disabled when these pins are in GPIO output mode. Copyright © MediaTek Inc. All rights reserved.
Page 101 (2) For MIPI sensor please set CSI2 EN=1 (this share-pad will change to mode 1) (2) For MIPI sensor, please set CSI2_EN 1 (this share pad will change to mode 1) (refer to mcu\custom\drv\image_sensor\MT9P012_MIPI\image_sensor_MT9P012_MIPI.c) Copyright © MediaTek Inc. All rights reserved.
Page 102: Gpio Selection
In above example : GPIO0 will be GPIO0 will be in input mode in input mode GPIO1 will be in input mode GPIO2 will be in output mode GPIO3 will be High in output mode Copyright © MediaTek Inc. All rights reserved.
Page 104 AUXADC_2 Internal use (CHRIN) N.A. (Internal) AUXADC_3 Internal use (BATTEMP) N.A. (Internal) AUXADC_4 External ADC channel AUXADC_5 External ADC channel AUXADC 6 AUXADC_6 External ADC channel l ADC h AUXADC_7 External ADC channel Copyright © MediaTek Inc. All rights reserved.
Page 105: Touch Panel
For RF desense issue, replace 0ohm with adequate beads. RF d ith d ▪ For ESD issue, mount adequate varistors. ▪ Otherwise, these components can be removed in later versions to save BOM cost. Copyright © MediaTek Inc. All rights reserved.
Page 107 ECAS_B CAS# ERAS_B RAS# DQM0 LDQM DQM1 UDQM DQS0 DQS0 LDQS LDQS DQS1 UDQS EWAIT RDY, WAIT WATCHDOG RST# Remark 3 Copyright © MediaTek Inc. All rights reserved. 2010/10/22 P_CRE, P_MODE (next page) Copyright © MediaTek Inc. All rights reserved.
Page 108 External Memory Interface (2/2) Remark 2: Remark 2: (1) EC_CLK & EC_CLK_B should be differential trace (2) The connection of EC_CLK & EC_CLK_FB should be close to memory Remark 3: Connect P_CRE/P_MODE to GND to GND Copyright © MediaTek Inc. All rights reserved.
Page 110 (2). Config VCAMD=1V5 and connect to Camera DVDD (3) Add (3). Add external LDO (250mA, PSRR=VCAMA) for Camera AVDD l LDO (2 0 A PSRR VCAMA) f AVDD (4). Add bead (600@100M) on above three camera power source Copyright © MediaTek Inc. All rights reserved.
Page 111 DVDD_CAM (pin Y19) ,Camera DOVDD and Camera AF power Config VCAMD=1V5 and connect to Camera DVDD For MIPI sensor, EMI filt EMI filter cap. max. loading is 3pf l di i 3 f Copyright © MediaTek Inc. All rights reserved.
Page 112 Design Notice – – Camera (3/18) Camera (3/18) ● ● Camera Reference Circuit (2/4): Camera Reference Circuit (2/4): Config VCAMA=2V8 and connect to DVDD_CAM (pin Y19) ,Camera DOVDD and Camera AF power MIPI Camera interface power Copyright © MediaTek Inc. All rights reserved.
Page 113 Design Notice Design Notice – – Camera (4/18) Camera (4/18) ● ● Camera Reference Circuit (3/4): Camera Reference Circuit (3/4): CAMA / CAMD Source Copyright © MediaTek Inc. All rights reserved.
Page 115 Layout 5: Layout 5: Layout 3: Layout 3: Layout 4: Layout 4: Camera Digital Power Camera Digital Power Control Group Trace Control Group Trace Data Group Trace Data Group Trace Trace Trace Trace Trace Copyright © MediaTek Inc. All rights reserved.
Page 116 The sensor module’s power s pplies( ind ctors beads resistors supplies( inductors , beads , resistors , capacitors) should be placed as close as possible to the connect Copyright © MediaTek Inc. All rights reserved.
Page 117 PCLK Image sensor pixel clock input Image sensor pixel clock input I2C clock output I2C d I2C data input/output Control CMRST Image sensor reset signal output CMPDN Image sensor power down signal output Copyright © MediaTek Inc. All rights reserved.
Page 118 4 800 mils 4,800 mils Connect) Max. (Trace length) − 500mil ≤ (Trace length) ≤ Max. Length matching (Trace length) Suggest data group should avoid clock or noisy power in Remark Remark upper/lower layer Copyright © MediaTek Inc. All rights reserved.
Page 119 Max. (TL0 + TL1) 4,500 mils (PCLK length − 500-mil) ≤ DQ length ≤ Length matching for Data-to- PCLK (PCLK length + 500-mil) Remark Each clock shall be routed surround with ground plan Copyright © MediaTek Inc. All rights reserved.
Page 120 W ≥ 3-mil S ≥ 3-mil W ≥ 3 mil, S ≥ 3 mil. BGA package area) Max. TL0 6000 mils Suggest control group should avoid clock or noisy power in Remark Remark upper/lower layer Copyright © MediaTek Inc. All rights reserved.
Page 121 MIPI CSI: 3 inches. Length matching in PCB Pair to pair (within one connector): 100 mils. Route the differential pair straight and symmetrically on the same Remark layer with equal trace width and space. Copyright © MediaTek Inc. All rights reserved.
Page 122 Image sensor pixel clock input Image sensor pixel clock input I2C clock output I2C data input/output Control CMRST Image sensor reset signal output CMPDN Image sensor power down signal output CMFLASH Image sensor Flash signal output Copyright © MediaTek Inc. All rights reserved.
Page 123 Max. (Trace length) − 500mil ≤ (Trace length) ≤ Max. Length matching(TL0+TL1) (Trace length) Suggest data group should avoid clock or noisy power in Suggest data group should avoid clock or noisy power in Remark upper/lower layer Copyright © MediaTek Inc. All rights reserved.
Page 124 (PCLK length − 500-mil) ≤ DQ length ≤ Length matching for Data-to- PCLK(TL0+TL1) (PCLK length + 500-mil) Remark E h l k h ll b Each clock shall be routed surround with ground plan d ith Copyright © MediaTek Inc. All rights reserved.
Page 125 6 000 mils 6,000 mils Image Sensor Connect) Max. TL1 (Branch points to Sub 2,000 mils Image Sensor Connect) Suggest control group should avoid clock or noisy power in upper/lower Remark layer layer Copyright © MediaTek Inc. All rights reserved.
Page 126 Main trace patterns (Analog Power) W ≥ 12-mil, S = 4-mil with GND trace. W ≥ 12 mil, S 4 mil with GND trace. Remark Analog power shall be routed surround with ground plan Copyright © MediaTek Inc. All rights reserved.
Page 127 Reference plane Route microstrip over unbroken ground or power plane. Main trace patterns (Digital Power) W ≥ 12-mil, S = 4-mil with GND trace. Remark Digital power shall be routed surround with ground plan Copyright © MediaTek Inc. All rights reserved.
Page 129 FM de- - sense (1/2) sense (1/2) ● ● LCM backlight causes 1MHz de-sense LCM backlight causes 1MHz de sense Adding a 600ohm bead here can remove 1MHz-spacing de-sense Period =1MHz Period 1MHz Copyright © MediaTek Inc. All rights reserved.
Page 130 Design Notice Design Notice – – FM de FM de- - sense (2/2) sense (2/2) ● ● Keypad connector is a de-sense path Keypad connector is a de sense path Copyright © MediaTek Inc. All rights reserved.
Page 131 – GND shielding has to accompany with enough GND vias ▪ FM 32k FM_32k trace must be enclosed well with GND shielding trace must be enclosed well with GND shielding Copyright © MediaTek Inc. All rights reserved...
Page 132 LWRB (write strobe signal) and LPA0(address output) – Reserve 2012 size 4 channel EMI filter array (LC type) for LCM data 2012 i l EMI filt (LC t LCM d t bus and close to LCM connector if necessary Copyright © MediaTek Inc. All rights reserved...
Page 133 – Keep LCM FPC as short as possible; Well GND shielding FPC is appreciated – VCO inductor of FM chip has to well GND shielding VCO inductor of FM chip has to well GND shielding Copyright © MediaTek Inc. All rights reserved...
Page 135 Tool version that supports MT6236 development Tool version that supports MT6236 development Tool Support version ATE Tool (including SN WRT Tool) After 10.28 META Tool (including META_DLL) After v6.1028.0 META_APP_DLL Tool After v6.1028.0 MultiportDownload Tool After v3.1028.00 FlashTool After FlashTool v3.1028.00...
Page 137 Memory card, SDIO Memory card, SDIO ex: throughput issue SIM, touch panel Performance risk UART, SPI, I2C, I2S, PCM Performance risk JTAG, debug, test mode, GPIOs, key matrix, Performance risk Performance risk reset Copyright © MediaTek Inc. All rights reserved.
Page 138 Layout Notice (1/ Layout Notice (1/5 5 ) ) 0 PCB layer : MT6236 support 6 layer PCB layout 0. PCB layer : MT6236 support 6 layer PCB layout. 1. Power trace : (1) VCORE VM VRF VIBR VCAMA (1) VCORE, VM, VRF, VIBR, VCAMA...
Page 139 (7) For VRF_S : far-end sense trace, please connect it to 6140'S R611 (Near C649) VRF S f t it t 6140'S R611 (N C649) (8) For VCAMA_S : near-end sense trace, please connect it to C222 Copyright © MediaTek Inc. All rights reserved.
Page 140 [2]Avoid the crossover with power traces) BDLAIP/BDLAIN, BDLAQP/BDLAQN BDLAIP/BDLAIN, BDLAQP/BDLAQN : Differential line ; the same trace length : Differential line ; the same trace length APC, AFC SYSCLK(26MHz) Copyright © MediaTek Inc. All rights reserved.
Page 141 CMMCLK CMPCLK DAICLK SIMCLK : No need to protect those traces by GND but please CMMCLK, CMPCLK, DAICLK, SIMCLK : No need to protect those traces by GND, but please keep 8mil distance with other traces Copyright © MediaTek Inc. All rights reserved.
Page 142 “MTK_USB_Application_Notes” to get more information 6. Reset related trace : (Common rule [1]Please keep 8mil distance with other traces [2]Please keep 50mil distance with shielding case and PCB edge. RESETB , SYSRST_B WATCHDOG LRSTB SIMRST Copyright © MediaTek Inc. All rights reserved.
Page 144 Issue Case Study - - 1 1 Issue date : 2010/08/26 [Issue description] MSDC IOT issue : MT6236 cannot detect MSDC after some bad quality MSDC card plug-in [Root cause] [Root cause] 1. SD2.0 spec define “MSDC controller + PCB trace + card” total capacitor loading < 40pF.
Page 145 CLKM3 URXD2 GPIO45 URXD2 UCTS3 D2 TID2 PWM3 GPIO59 PWM3 URXD2 ARM7_JTCK AA16 KROW7 GPIO16 KROW7 EDIDAT URXD3 URXD3 GPIO39 URXD3 UCTS2 D2_TID4 PWM5 GPIO61 PWM5 URXD3 ARM7_JTMS IRDA_RXD GPIO56 IRDA_RXD PWM4 UCTS1 Copyright © MediaTek Inc. All rights reserved.
Page 147 Memory PCB layout characteristics in the following Memory PCB layout characteristics in the following order: 1. Placement 1. Placement 2. Ground/Power plane 3. Suggested routing order (Signal layout) 4. Other general layout considerations Copyright © MediaTek Inc. All rights reserved...
Page 149 Note: Swap the corresponding DQSx ,DMx and DQx at the same time. – Different bits (DQx) in the same data byte could also be swapped if needed – Different bits (DQx) in the same data byte could also be swapped if needed. Copyright © MediaTek Inc. All rights reserved...
Page 150 GND plane, and there is a power plane (memory power domain VMEM) under the GND plane if possible. e.g. 6 layers(MT6236 reference stack up)- 1st layer : memory traces 2nd layer: memory traces (strongly recommended -...
Page 151 Note: All power trace bypass capacitors (de-cap) must be placed as close to the memory or BB power pins as possible, and all capacitor's GND should have the shortest and widest trace to the GND plane. Copyright © MediaTek Inc. All rights reserved...
Page 152 L2): one via per one Vm ball or one de cap if possible buried via(L2-L5): more is better (at least 3 via for BB Vm balls) Please refer to the reference phone layout as below L2~L5 L1~L2 Copyright © MediaTek Inc. All rights reserved...
Page 154 There are a power plane under memory Interface traces Interface traces Interface traces Interface traces The impedance reduce to half The impedance reduce to half When added power plane When added power plane Copyright © MediaTek Inc. All rights reserved...
Page 155 Added a small Only power trace Only power trace plane under BB plane under BB power plane power plane chip and DRAM chip and DRAM under BB chip under BB chip Must Not good Copyright © MediaTek Inc. All rights reserved...
Page 158 GND via from Vm capacitors near capacitor GND capacitor GND baseband chip d hi pad(L1) to GND plane(L3) Vm via from capacitor Vm pad(L1) to Vm plane(L7) plane plane plane Copyright © MediaTek Inc. All rights reserved...
Page 159 Vm via) ▪ Please notice that the via quantity between Vm plane to Vm balls, must follow the Vm balls, must follow the basic rule at least as above pages. Copyright © MediaTek Inc. All rights reserved...
Page 160 Vm PDN: L1 LC L6 trace L2 trace vias L7 V L7 Vm plane Vm trace(L2) (L2) to Vm ▪ Please notice that the decoupling plane(L7) capacitor from Vm trace to Vm plane is needed needed. Copyright © MediaTek Inc. All rights reserved...
Page 161 Add power source Add power source decoupling cap, and also decoupling cap, and also decoupling cap, and also decoupling cap, and also cap near baseband cap near baseband cap near baseband cap near baseband Copyright © MediaTek Inc. All rights reserved...
Page 162 Therefore, we must lower the PDN impedance (from Vm source to BB/MCP Vm balls) as possible by following layout rule. That will let system become more robust. ill l t Copyright © MediaTek Inc. All rights reserved...
Page 163 Power/GND plane Data group Clock group Command/Address/Control gro ps Command/Address/Control groups – Because signal integrity (SI) is highly related to solid ground and power plane, data groups are operating at twice the clock frequency. Copyright © MediaTek Inc. All rights reserved...
Page 164 D[8:15] is aligned to DQS[1]. So, D[0:7] must be routed in a group with DQS[0], and D[8:15] must be routed in a group with DQS[1] and D[8:15] must be routed in a group with DQS[1]. Copyright © MediaTek Inc. All rights reserved...
Page 165 | DQSx - Clock trace length | < 200 mil – To reduce the crosstalk on DQSx , GND shielding is required. t lk GND hi ldi GND Via required on entire GND shield DQS0 Copyright © MediaTek Inc. All rights reserved...
Page 166 (Max. trace length – 50 mil) < Trace length < (Max. trace length), |DQS - Clock trace length| < 200 mil |DQS - Clock trace length| < 200 mil Differential clock pair GND Via required on entire GND shield Copyright © MediaTek Inc. All rights reserved...
Page 167 – Every trace must have solid power and ground plane near the entire route. – Within CMD/ADR group: |Max. (CMD/ADR trace length) – Min. (CMD/ADR trace length)| < 600 mil length)| < 600 mil as possible as possible Copyright © MediaTek Inc. All rights reserved...
Page 168 – On the ground plane, do not block the ground return currents, as shown in the left figure shown in the left figure. Ground plane Ground plane Vias Vias Vias Bad current return path Good current return path Copyright © MediaTek Inc. All rights reserved...
Page 169 90 turn. By making two 45 turns or an arc, it reduces reflections on the signals with impedance discontinuities minimized. – Avoid creating unnecessary stubs on data lines, if a stub is unavoidable, please keep the stub as short as possible. stub Copyright © MediaTek Inc. All rights reserved...
Page 170 – If two adjacent layers are signal layers, please avoid routing signal trace in Overlap method as the following picture. th d th f ll Overlap Interleave (O) – Please check if the power via quantity( power plane to power pins) is optimized. Copyright © MediaTek Inc. All rights reserved...
Page 171 Appendix : Appendix : MT5921 Application Note for MT6236 MT5921 Application Note for MT6236 MT5921 Application Note for MT6236 MT5921 Application Note for MT6236 Copyright © MediaTek Inc. All rights reserved.
Page 173 1. 1. Signal Connection between MT5921 and MT6236 Signal Connection between MT5921 and MT6236 2. MT5921 NFI Bus Multi IO Usage 3. 3. MT5921 Power Supply Plan for MT6236 Platform MT5921 Power Supply Plan for MT6236 Platform 4. 4. MT5921 with BT Single Antenna Design...
Page 174 Connection between MT5921 and MT6236 (1/5) Connection between MT5921 and MT6236 (1/5) Group 1 Group 1 MT6236 Pin MT6236 Pin MT5921 Pin MT5921 Pin Group 2 Group 2 Group 3 Group 3 Copyright © MediaTek Inc. All rights reserved.
Page 175 Connection between MT5921 and MT6236 (2/5) Connection between MT5921 and MT6236 (2/5) – Group 1 : NFI interface (NLD0~7) – MT5921 shares NFI bus with NAND/LCM module so WiFi , NAND and LCM must have the same bus voltage domain LCM must have the same bus voltage domain.
Page 176 LPCE1B – Group 2-2: MT5921 interrupt signal MT5921 pin name MT6236 pin name Description MUST connect WIFI EINT to MT6236 EINT0 !! Because EINT0 power domain = DVDD_NFI EINT1 6 power domain = DVDD28 EINT1~6 power domain = DVDD28 INT_N EINT0 Only EINT0 meets MT5921 requirement.
Page 177 Connection between MT5921 and MT6236 (4/5) Connection between MT5921 and MT6236 (4/5) – Group 3-1 : BT PTA connection MT5921 pin name MT6236 pin name Description WiFi BT co-existence signal BT PRI BT_PRI bt2 ifi 0(GPIO64) bt2wifi_0(GPIO64) – Goup3-2 : MT5921 32K digital slow clock signal –...
Page 178 Connection between MT5921 and MT6236 (5/5) Connection between MT5921 and MT6236 (5/5) – Goup3-3 : MT5921 RST_N and WIFI_EN signal – RST N(+2.8V voltage domain) : WiFi power-on reset signal – WIFI_EN (+2.8V voltage domain) : WiFi external LDO(2.8V and 1.8V) control signal .
Page 179 MT5921 NFI Bus Multi IO Usage ( MT5921 NFI Bus Multi IO Usage (CoB CoB) ) – MT5921 supports +1.8V and +2.8V NFI bus – MT5921 NFI bus level selection depends on MT5921 VCCMIO power input. Copyright © MediaTek Inc. All rights reserved.
Page 180 MT5921 NFI Bus Multi IO Usage (Module) MT5921 NFI Bus Multi IO Usage (Module) – MT5921 supports +1.8V and +2.8V NFI bus – MT5921 NFI bus level selection depends on MT5921 VCCMIO power input. Copyright © MediaTek Inc. All rights reserved.
Page 181 MT5921 Power Supply at MT6236 Platform (1/4) MT5921 Power Supply at MT6236 Platform (1/4) pp y pp y – Power-on sequence: – VDD18 power supply should be turned on first before DVDD28 power supply in order to avoid DVDD28 peak current.
Page 182 – MT5921 +2.8V/+1.8V power supply plan at MT6236 platform: – Solution A : – Share MT6236 PMU VMEM and VIO power ports with other devices. – Solution B : – Use dedicated external +2.8V/+1.8V LDO component.
Page 183 MT5921 Power Supply at MT6236 Platform (3/4) MT5921 Power Supply at MT6236 Platform (3/4) pp y pp y – Note for power plan A : – Due to power sharing method, MT5921 +1.8V may cause some current leakage during system power on period After system completed power on leakage during system power-on period.
Page 184 MT5921 Power Supply at MT6236 Platform (4/4) MT5921 Power Supply at MT6236 Platform (4/4) pp y pp y – MT5921 external PA power supply plan at MT6236 platform: – Use MT5921 RADIO_EN pin to control WiFi PA LDO. Copyright © MediaTek Inc. All rights reserved.
Page 185 MT5921 GPIO0 and GPIO1 hardware pin to control custom-mode SPDT to switch RF path between MT5921 and MT6236. – Customers must use specific SW setting and HW component for single antenna design for single antenna design. ( Please ask PM to release SW/HW...
Page 186 – *Switch is special 50 ohm terminated component. – *Switch logic table: MT5921 MT5921 ANT Path GPIO0 GPIO1 Switch to WiFi High S it h t BT Switch to BT Hi h High Copyright © MediaTek Inc. All rights reserved.
Page 187 < -12dB antenna return loss 12dB 2.4~2.5GHz frequency . – Highly recommend using PIFA antenna Other type antenna is not suitable and design. may cause single antenna performance may cause single antenna performance degradation. Copyright © MediaTek Inc. All rights reserved.
Page 188 Please don’t apply single antenna SW on dual antenna HW design. It may cause 30~40mA current leakage due to MT5921 GPIO signal shortage to GND ! Wrong GPIO design Correct single antenna under single antenna SW GPIO design Copyright © MediaTek Inc. All rights reserved.
Page 191 4 weeks 加高電子 X2B040000L71HZ-U H.ELE 6 weeks 三和科技 CXC3X400000GJVRB0M Partron 3 weeks 璟德 BL1608-20B2450T 6~8 weeks 台灣村田 LDB182G4520C-110 Murata 4~6 weeks RX Balun 1608 美磊 LTU-1608-2G4S1-A6 MAG.LAYERS 4~6 weeks 華新 RFBLN1608060AM1T59 WALSIN 2~4 weeks Copyright © MediaTek Inc. All rights reserved.
Page 192 1: For different PA designs, check the PA biasing circuits and follow the reference design. Note RTC6665 pin-out is the same with SST PA but matching component value are Copyright © MediaTek Inc. All rights reserved. different, please contact with MTK for RTC6665 reference design.
Page 193 2: For MT5921, TRSW : TRSW_N signal table is as below: Note Note TX mode: {TRSW=1,TRSW_N=0} RX mode: {TRSW=0,TRSW_N=1} For different SPDT chips (Type 1 or 2) , check the signal connection to avoid logic conflict. Copyright © MediaTek Inc. All rights reserved.
Page 194 All module pin out is pin to pin !! All module pin out is pin to pin !! ( Module vendor could provide on ( Module vendor could provide on- - site SMD support ) site SMD support ) Copyright © MediaTek Inc. All rights reserved.
Page 195 ( Module vendor could provide on- - site SMD support ) ( Module vendor could provide on ( Module vendor could provide on- - site SMD support ) site SMD support ) site SMD support ) Copyright © MediaTek Inc. All rights reserved.
Page 196 1. 1. Signal Connection between MT5921 and MT6236 Signal Connection between MT5921 and MT6236 2. MT5921 NFI Bus Multi IO Usage 3. 3. MT5921 Power Supply Plan for MT6236 Platform MT5921 Power Supply Plan for MT6236 Platform 4. 4. MT5921 with BT ( MT6612/MT6616) Single Antenna Design...
Page 198 WIFI co and WIFI co- - existence existence MT5921 could use OSC MT5921 could use OSC or crystal as system clock or crystal as system clock source source Copyright © MediaTek Inc. All rights reserved.
Page 199 Use resistor to change PA Use resistor to change PA bias voltage bias voltage RF TX output matching RF TX output matching Capacitor could keep TX Capacitor could keep TX performance stable performance stable Copyright © MediaTek Inc. All rights reserved.

MEDIATEK MT6236 Instruction Manual

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