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AsahiKASEI AKM AKD4490R-A Manual

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The AKD4490R-A is an evaluation board for the AK4490R (Premium 32-bit 2ch stereo DAC) that
supports Network-Audios, USB-DAC, Car-Audio Systems. It integrates differential output low pass filters,
allowing quick evaluation with digital audio interface.
■
Ordering Guide
AKD4490R-A -- Evaluation Board for the AK4490R
 Low Pass Filters (LPF) for Pre-amplifier Outputs
 Digital Audio Interface (AK4118A)
 10-pin Header for Serial Control (AK4490R)
DIR
COAX In
Opt In
Note 1. Circuit schematics are attached at the end of this document.
<KM136100>
1. General Description
(A USB I/F board for
IBM-AT compatible computers and control software are
included in this package.
AK4118A
AK4490R
Figure 1. AKD4490R-A Block Diagram
AK4490R Evaluation Board Rev.0
)
2. Function
2nd Order LPF
- 1-
[AKD4490R-A]
AKD4490R-A
Lch
Rch
(Note
1)
2022/01

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Summary of Contents for AsahiKASEI AKM AKD4490R-A

  • Page 1 [AKD4490R-A] AKD4490R-A AK4490R Evaluation Board Rev.0 1. General Description The AKD4490R-A is an evaluation board for the AK4490R (Premium 32-bit 2ch stereo DAC) that supports Network-Audios, USB-DAC, Car-Audio Systems. It integrates differential output low pass filters, allowing quick evaluation with digital audio interface. ■...

  • Page 2: Board Appearance

    [AKD4490R-A] 3. Board Appearance ■ Appearance Diagram Figure 2. AKD4490R-A Outline View ■ Description (1) Connectors for Power Supply and GND (J501/J500/J100/J101/J512/J513/J504/J505/J502/J503/J510/J511/J200) (+15V, -15V, AVDD, TVDD, VDDL, VDDR, VREFHL, VREFHR, MVREFL(+15V), MVREFR(+15V), AVSS, DVSS, DIGEXT-3p3V) Connectors for power supply and the ground Power Supply Connections Refer to the “...
  • Page 3 [AKD4490R-A] (7) DIP Switches ( Main Board : SW101 / SW200 ) ( Sub Board (AKD4490R-A-SUB-48LQFP) : SW10 / SW11 ) Setting Switches for the AK4490R and the AK4118A. Upside is “H” (ON) and Downside is “L” (OFF). Settings Refer to “■ Jumper Pin and DIP Switch ”...

  • Page 4: Operation Sequence

    [AKD4490R-A] 4. Operation Sequence  Operation sequence 1). Power Supply Connections 2). Evaluation Mode 3). Jumper Pin and DIP Switch Settings 4). Power-up 5). Register control (Serial control) ■ Power Supply Connections Default Name Color Voltage Content Note Setting MVDD+ (Regulator), J501 +15V +10 to +15V...

  • Page 5: Evaluation Mode

    [AKD4490R-A] ■ Evaluation Mode (1) Evaluation with a DIR (COAX) < Default > The J106 (COAX) jack is used in this mode. The DIR (AK4118A) generates MCLK, BICK, LRCK and SDATA from the input data of the J106 (COAX) connector. Set the JP108 (RX-SEL) jumper pin to ‘Up’...
  • Page 6 [AKD4490R-A] (3) In the case that all interface clocks including the master clock are input externally. (JP223, JP224) Input all interface clocks including the master clock to the JP223 and JP224. The JP223 (EXT for MCLK) and the JP224 (EXT for BICK and SDATA and LRCK) jumper ports is used in this mode.
  • Page 7 [AKD4490R-A] ■ Jumper Pin and DIP Switch Settings (1) Jumper Pin Settings Table 3-1-1. Jumper Settings for power supply [ Main Board ] Default Name Content Setting AVDD pin input select REG(3.3V): The AVDD pin is supplied from the T100 regulator. JP100 AVDD REG(3.3V)
  • Page 8 [AKD4490R-A] Connection between Analog VSS pattern and Digital VSS pattern. CL100 Cut-Land Solder short: Connect Analog VSS pattern and Digital VSS pattern. open open: Detach Analog VSS pattern and Digital VSS pattern. Connection between Analog VSS pattern and Digital VSS pattern. CL101 Cut-Land Solder short: Connect Analog VSS pattern and Digital VSS pattern.
  • Page 9 [AKD4490R-A] Table 3-2-2. Jumper Settings for data & clock [ Sub Board : AKD4490R-A-SUB-48LQFP ] Default Name Content Setting AK4490R Input data select. H short: SSLOW input data is set to “Hight”. JP13 L short: SSLOW input data is set to “Low”. short open: WCK (Word clock) input data signal is supplied from 2-pin of JP13.
  • Page 10 [AKD4490R-A] (2) DIP Switch Setting Upside is ON (“H”), and Downside is OFF (“L”). AK4118A Settings : Main Board [SW101]: Setting of the AK4118A Name ON (“H”) OFF (“L”) Default DIF2 Audio I/F Format for AK4118A DIF1 Refer to Table 4-1-1. DIF0 OCKS1 Master Clock setting for AK4118A...
  • Page 11 [AKD4490R-A] [SW11]: Setting of the AK4490R Name ON (“H”) OFF (“L”) Default I2C-Bus Control mode 3-wire Serial Control mode I2C/INV Output Select: Refer to Table 4-3-1 (In Parallel Control Mode) TESTE Test Mode Normal Mode Table 4-3. SW11 Setting (AK4490R) SSLOW SLOW Mode...
  • Page 12 [AKD4490R-A] ■ Power-up Upside is ON (“H”), and Downside is OFF (“L”). [SW100] (PDN): DAC Reset control. It must be set to “H” during operation. After power-up, the AKD4490R-A must be reset once. To reset the AKD4490R-A, set the SW100 toggle switch to “L” and power down the AK4490R and the AK4118A.
  • Page 13 [AKD4490R-A] ■ Example of evaluation mode: (1) Normal Mode Sequence : fs=44.1kHz, MCLK=256fs, BICK=64fs, 24bit,Left Justified  Start up Setting 1: Jumpers and Dip-switches and Toggle-switches are default (Normal Mode) setting. Note. Main Board : SW101: OCKS1-0=”LL” (256fs), DIF2-0=”HLL” (24bit Left Justified) Sub Board(AK4490R): SW10: SMUTE=”L”, PSN=”L”, CAD1-0=”LL”, DEM0=”H”, LDOE=”L”...
  • Page 14 [AKD4490R-A] 001: 20bit, LSB justified 010: 24bit, MSB justified 011: 24 or 16bit, I2S compatible 100: 24bit, LSB justified 101: 32bit, LSB justified 110: 32bit, MSB justified 111: 32bit, I2S compatible Addr Register Name Control 2 DZFE DZFM DFS1 DFS0 DEM1 DEM0 SMUTE...
  • Page 15 [AKD4490R-A] ■ Serial Control Mode The AKD4490R-A (for the AK4490R) should be connected to a PC (IBM-AT compatible) via a USB control box (AKDUSBIF-B) included in this package. The USB control box is connected to a PC with a USB cable and the AKD4490R-A with a 10-pin flat cable.
  • Page 16 [AKD4490R-A] Set up the resistor parts. (Control Mode Setting) : For the AK4490R … Selected Position Control Mode settings. Serial SW10 (AK4490R) SW11 (AK4490R) Control Software Control ( No.7: PSN ) ( No.1 : I2C ) (Control I/F) Mode SW10 SW11 3-wire 9 10...
  • Page 17 [AKD4490R-A] Set up the jumper pins. JP10 = CSN short, JP11 = CCLK/SCL short, JP12 = CDTI/SDA short JP13 = L short, JP14 = open, JP15 = open JP14 JP15 SMUTE CCLK/SCL SD CDTI/SDA SLOW DZFL DZFR JP10 JP11 JP12 JP13 Figure 12.
  • Page 18 [AKD4490R-A] Control Software Manual ■ Evaluation Board and Control Software Settings ( for the AK4490R ) 1. Set up the evaluation board as needed, according to the previous terms. 2. Connect the evaluation board to a PC with USB cable. 3.
  • Page 19 [AKD4490R-A] ■ Operation Overview Register map is controlled by this control software. Frequently used buttons, such as the register initializing button “Write Default”, are located outside of the switching tab window. Refer to the “■ Dialog Box” section for details of each dialog box setting. 1.[Init Port]: Reset the USB port.
  • Page 20 [AKD4490R-A] ■ Tab Functions 1. [RegMap] Tab: Register Map This tab is for register read and write. Each bit on the register map is a push-button switch. Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red). Button Up indicates “0”...
  • Page 21 [AKD4490R-A] [Write] button: Data Write Dialog Select the [Write] button located on the right of the each corresponding address when changing two or more bits on the same address simultaneously. Click the [Write] button for the register pop-up dialog box shown below. When the checkbox next to the register is checked, the data will become “1”.
  • Page 22 [AKD4490R-A] 2. [ Script ] Tab : Script Function Figure 15. Window of [Script] [Refer] : Select a script file. The script written on the file will be executed automatically. [Repeat] : The selected script file will be executed once again. <KM136100>...

  • Page 23: Sequence Setting

    [AKD4490R-A] ■ Dialog Box 1. [Sequence]: Sequence Dialog Box Click the [Sequence] button in the main window for Sequence dialog box. Register sequence may be set and executed. Figure 16. [Sequence] Window ~ Sequence Setting ~ Set register sequence according to the following process. Select a command Use [Select] pull-down box to choose commands.
  • Page 24 [AKD4490R-A] 2. Input Sequence [Address]: Data Address [Data]: Write Data [Mask]: Mask This value “ANDed” with the write data becomes the input data. When Mask = 0x00, current setting is hold. When Mask = 0xFF, the 8bit data which is set in the [Data] box is written. When Mask = 0x0F, lower 4bit data which is set in the [Data] box is written.
  • Page 25 [AKD4490R-A] Revision History Date Manual Board Reason Page Contents (y/m/d) Revision Revision 22/01/01 KM136000 First Edition <KM136100> 2022/01 - 25-...

  • Page 26: Important Notice

    [AKD4490R-A] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products.

  • Page 27: Measurement Results

    [AKD4490R-A] 1. Measurement Results [Measurement condition]  Measurement unit : Audio Precision APX555 audio analyzer (APX555)  MCLK : 256fs (44.1 kHz), 256fs (96kHz), 128fs (192kHz)  BICK : 64fs  fs : 44.1kHz, 96kHz, 192kHz  Bit : 24bit ...
  • Page 28 [AKD4490R-A] [Plots] fs = 44.1 kHz AK4490R THD+N vs. Input Level AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 20-1. THD+N vs. Input Level AK4490R THD+N vs. Input Frequency AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 20-2.
  • Page 29 [AKD4490R-A] fs = 44.1 kHz AK4490R Linearity AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 20-3. Linearity AK4490R Frequency Response AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 20-4. Frequency Response <KM136100>...
  • Page 30 [AKD4490R-A] fs = 44.1 kHz AK4490R Crosstalk AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 20-5. Crosstalk AK4490R FFT (0dBFS Input) AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 20-6.
  • Page 31 [AKD4490R-A] fs = 44.1 kHz AK4490R FFT ( -60dBFS Input) AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 20-7. FFT (-60dBFS Input) AK4490R FFT ( No Signal Input) AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 20-8.
  • Page 32 [AKD4490R-A] fs = 96kHz AK4490R THD+N vs. Input Level AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=96kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 21-1. THD+N vs. Input Level AK4490R THD+N vs. Input Frequency AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=96kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 21-2.
  • Page 33 [AKD4490R-A] fs = 96kHz AK4490R Linearity AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=96kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 21-3. Linearity AK4490R Frequency Response AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=96kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 21-4. Frequency Response <KM136100>...
  • Page 34 [AKD4490R-A] fs = 96kHz AK4490R Crosstalk AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=96kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 21-5. Crosstalk AK4490R FFT (0dBFS Input) AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=96kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 21-6. FFT (0dBFS Input) <KM136100>...
  • Page 35 [AKD4490R-A] fs = 96kHz AK4490R FFT ( -60dBFS Input) AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=96kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 21-7. FFT (-60dBFS Input) AK4490R FFT ( No Signal Input) AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=96kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 21-8.
  • Page 36 [AKD4490R-A] fs = 192kHz AK4490R THD+N vs. Input Level AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 22-1. THD+N vs. Input Level AK4490R THD+N vs. Input Frequency AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 22-2.
  • Page 37 [AKD4490R-A] fs = 192kHz AK4490R Linearity AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 22-3. Linearity AK4490R Frequency Response AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 22-4. Frequency Response <KM136100>...
  • Page 38 [AKD4490R-A] fs = 192kHz AK4490R Crosstalk AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 22-5. Crosstalk AK4490R FFT (0dBFS Input) AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 22-6. FFT (0dBFS Input) <KM136100>...
  • Page 39 [AKD4490R-A] fs = 192kHz AK4490R FFT ( -60dBFS Input) AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 22-7. FFT (-60dBFS Input) AK4490R FFT ( No Signal Input) AVDD=3.3V, TVDD=3.3V, DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz DAC1 Ch1 : Lch, Ch2 : Rch Figure 22-8.
  • Page 40 92pin_1 VSSL VSSR VSSL VSSR SW 11 VSSL C101 10u(A) C102 10u(A) VSSR C103 0.1u C104 0.1u VSSL VSSR DVSS C105 10u(A) C106 10u(A) VCOML VCOMR VREFLL VREFLR VREFLL VREFLR VREFLL VREFLR R113 C107 C108 C109 C110 R114 220u(A) 0.1u 0.1u 220u(A) U100...
  • Page 41 CL100 Cut Land AVSS DVSS CL101 Cut Land AVSS DVSS AVSS AVSS AVSS AVSS AVSS AVSS PM-1 (23pin) L100 47u(L) PORT104 PM-1 (23pin) PM-1 (23pin) 92pin_3 C103 C102 DVSS 10u(A) AK449x Sub Board 0.1u(F) C107 10u(A) VSSL VSSR AVSS AVSS C106 0.1u JP108...
  • Page 42 AK4191 Digital-IC Block J200 TP200 DIGEXT-3p3V DTVDD1 MVDD+ T200 JP211 JP221 TVDD1-DIG0 BA033CC0T EXT(3.3V) JP210 MCLK-DIR R200 MCLK-DIR0 MCLK-1 DIGVDD1 DIGVDD1-3p3V REG(3.3V) PORT200 REG(3.3V) For TVDD1 REG(1.8V) JP222 EXT-DIGDATA BICK BICK-DIR R201 T201 BICK-DIR0 BICK-1 C200 TVDD1 SDATA SDATA-DIR R202 AK4490/AK4493/AK4497-DSD_EXT MCLK SDTO-DIR0...
  • Page 43 C308 C300 100u(A) R308 R312 R300 (short) MVDDL2+ AOUTLP C304 C309 R304 open U300A R324 (short) AVSS AVSS AVSS OPA1612 R316 MVDDL2- R317 J300 XLOUT AVSS AVSS C310 C301 100u(A) R309 R313 R301 (short) MVDDL2+ AOUTLN C305 C311 R305 open U300B R325 (short)
  • Page 44 J504 VREFHL MVDD+ JP501 VREFHL VREFHL Q500 MVDD+ JP509 BCP 56 MVREFL MVREFL MVREF J502 R500 R501 C505 R503 100u(A) MVREFL(+15V) 3.83k C503 C501 0.1u(A) 0.1u(A) D500 J510 J511 AVSS DVSS U500 R502 JP500 VSS-SEL1 JP520 VSS-SEL2 Q501 SB1188 CSC AVSS DVSS AD817A/AD...
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