Polaroid FLM 3701 - 37" LCD TV Service Manual page 19

6. TFP403
functional block diagram
3.3 V
Internal 50-
Termination
Rx2+
Rx2-
Rx1+
Rx1-
Rx0+
Rx0-
RxC+
RxC-
TERMINAL
I/O I/O
NAME NO.
AGND 79 GND
AV DD 82,85,88, V DD
91
CAP 67 V DD
CTL[2:1] 41,40 DO
DE 46 DO
DFO 1
DGND 5,39,68 GND
DV DD 6,38 V DD
HSYNC 48 DO
OCK_INV 100
Channel 2
+
Latch
_
Channel 1
+
Latch
_
Channel 0
+
Latch
_
+
PLL
_
Terminal Functions
Analog ground? Ground reference and current return for analog circuitry
Analog V DD ? Power supply for analog circuitry. Nominally 3.3 V
Bypass capacitor? 4.7 F tantalum and 0.01 F ceramic connected to ground. This capacitor is optional for
the TFP403, but is required for the TFP501.
General-purpose control signals? Used for user defined control. In normal mode CTL1 is not powered down
via PDO.
Output data enable? Used to indicate time of active video display versus nonactive display or blank time.
During blank, only HSYNC, VSYNC, and CTL1-2 are transmitted. During times of active display, or nonblank,
only pixel data, QE[23:0] and QO[23:0], is transmitted.
High : Active display time
Low: Blank time
DI Output clock data format? Controls the output clock (ODCK) format for either TFT or DSTN panel support. For
TFT support ODCK clock runs continuously. For DSTN support ODCK only clocks when DE is high; otherwise
ODCK is held low when DE is low.
High : DSTN support/ODCK held low when DE = low
Low: TFT support/ODCK runs continuously.
Digital ground? Ground reference and current return for digital core
Digital V DD ? Power supply for digital core. Nominally 3.3 V
Horizontal sync output
DI ODCK polarity? Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals
(HSYNC, VSYNC, DE, CTL1-2 ) are latched
Normal mode:
High : Latches output data on rising ODCK edge
Low : Latches output data on falling ODCK edge
3.3 V
1.8 V
Regulator
CH2(0-9)
Data Recovery
CH1(0-9)
TMDS
and
Decoder
Synchronization
CH0(0-9)
DESCRIPTION DESCRIPTION
16
3.3 V
RED(0-7)
QE(0-23)
CTL3
QO(0-23)
CTL2
ODCK
DE
GRN(0-7)
Panel
SCDT
CTL1
Interface
CTL2
BLUE(0-7)
CTL1
VSYNC
VSYNC
HSYNC
HSYNC