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Multiplexer
i)
Function and EXF codes select DSC 0 to receive.
2)
Multiplexer selects DSC 0 to receive.
3)
When DSC 0 detects a sync word, the word is recognized by the cyclic
encoder/ decoder circuit.
The 12th bit of the sync word enables a gate which
allows DSC 0 to receive data and enables a 3-bit response to the transmitting
data set.
The 3-bit response clears the Sync Word Not Acknowledged bit at
the transmitting DSC.
The 12-bit sync word is not loaded into the A/D
register.
4)
The first word of the data block follows the sync word.
The A/ D register
assembles this data word; the 12th bit of this word enables an A/D-1/0
register transfer.
Data words are received and assembled at a rate of 300
use c per word.
5)
When the 1/0 register is loaded, the Full and Receive status bit in the DSC
0 portion of the status-all word sets.
6)
The next time the computer requests status-all, it detects the
11
1
11
{Full and
Receive) in the DSC 0 status-all word.
7)
The computer recognizes this "1" and selects DSC 0 {select code S520).
8)
The computer inputs the 12-bit data word from DSC 0.
9)
Thereupon, the computer services the remaining DSC' s if they require
service.
10)
The computer continues to sample status-all until it detects another
11
1
11
in
the status - all word.
11)
When the 12th bit of the second data word is loaded into the A/ D register,
the A/D register transfers this word to the 1/0 register.
This sets the Full
and Receive status-all bit and the process is repeated.
Controller DSC 0
Controller 0 continues to receive and assemble data words at 300 usec/word until the
computer has accepted the entire data block.
Words in the 1/0 register must be
transferred to the computer or the next A/D - 1/0 transfer will terminate the receive
operation.
Rev. A
3-13
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