Control Data Corporation 6000 Series Reference Manual page 24

Controller DSC 0
1) When the 12-bit sync word is transmitted, the 12th serial bit enables an
I/O register -A/D register transfer. This transfers the first data word to
the A/ D register.
2) Step 1 (Figure 3-5) transfers the first data word to the A/D register. This
enables the following:
a) With the I/O register empty, the Empty and Transmit status-all bit
again becomes a
11
1
11
and DSC 0 can accept another word.
b) The data w9rd in the A/ D register is sent to the cyclic encoder and
transmitted bit by bit. It requires approximately 300
µsec
to transmit
each 12 - bit word.
SAMPLE
STATUS
ALL
STATUS-ALL WORD
DSC 3 DSC 2 DSC I DSC 0
~
r-"----.
,,..-A--..
r-"---...
I
! !
I
! !
I
!
:1rg
\
A MAXIMUM MULTIPLEXER CYCLE IS
SHOWN AT THE LEFT. THIS CYCLE
MUST BE COMPLETED IN 250 µ.SEC.
IF ONE OF THE 3 STATUS -ALL BITS
IS A
"1':
THE MULTIPLEXER WILL
SERVICE THE RESPECTIVE DSC's
BEFORE CONTINUING TO SAMPLE
STATUS-ALL.
FULL A"D RECEIVE BIT
:::::
'.~:
""'"" "'
Figure 3-5. Multiplexer Cycle
3) When the 12th data bit is transmitted, an I/O-A/D transfer brings the next
data word to the A/D register. The transmit operation continues in this
manner for the entire data block.
4) During the serial transfer of the last word in the data block the last word is
in the A/D register, but the I/O register does not contain a new data word.
Transferring the 12th bit of the last data word from A/D, enables the DSC
to gate out the cyclic code. Upon completion of the code transmission, the
transmit function terminates.
Rev. A
3-11