IBM PowerPC 750CL Tsi109 User Manual
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IBM PowerPC 750CL Tsi109 User Manual

IBM PowerPC 750CL Tsi109 User Manual

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PowerPC 750CL Tsi109 Evaluation Board
User's Manual
A15-6006-03
May 04, 2007

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Summary of Contents for IBM PowerPC 750CL Tsi109

  • Page 1 Title Page PowerPC 750CL Tsi109 Evaluation Board User’s Manual A15-6006-03 May 04, 2007...
  • Page 2 Without limiting the generality of the foregoing, any performance data contained in this document was determined in a specific or controlled environment and not submitted to any formal IBM test. Therefore, the results obtained in other operating environments may vary significantly. Under no circumstances will IBM be liable for any damages whatsoever arising out of or resulting from any use of the document or the information contained herein.

  • Page 3: Table Of Contents

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Contents Figures ............. . 7 Tables .
  • Page 4 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Reset Switch - SW2 ............. 31 Processor PLL Setting DIP Switch - S2 .
  • Page 5 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Board Reset ..............67 750 HRESET .
  • Page 6 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Contents TOC.fm Page 6 of 92 May 04, 2007...

  • Page 7: Figures

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Figures Figure 2-1. PPC750CL Tsi109 Evaluation Board Architecture ..............15 Figure 2-2. Board Clocking Block Diagram ....................18 Figure 2-3. Memory Connection to Host Local Port ................. 19 Figure 2-4. PCI/X bus ..........................20 Figure 2-5.
  • Page 8 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Figure 9-7. J9 – Tsi109 JTAG Connector Pin Assignment ...............59 Figure 9-8. PCI/X Connector Pin Assignment (Top view) .................60 Figure 9-9. J18 – CPLD JTAG Connector Pin Assignment ..............63 Figure 9-10. ATX Power Connector Pin Assignment ..................64 Figure 9-11.

  • Page 9: Tables

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Tables Table 2-1. 750CL Signals Not Supported by Tsi109 ................16 Table 2-2. Serial Management Interface PHY Address ................21 Table 2-3. C Addresses ........................22 Table 2-4. Worst Case Power Requirement Per Rail ................23 Table 3-1.
  • Page 10 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 12-1. PPC750CL Tsi109 Bill of Material ..................75 Tables LOT.fm Page 10 of 92 May 04, 2007...

  • Page 11: About This Book

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board About This Book This book provides information on hardware implementation of the PPC750CL Tsi109 evaluation platform, as well as hardware setting options available to users. Who Should Use This Book This book is intended for readers with a basic technical background in electronics and software. The reader should be familiar with the following: •...
  • Page 12 User’s Manual PowerPC 750CL Tsi109 Evaluation Board About This Book Preface.fm Page 12 of 92 May 04, 2007...

  • Page 13: Overview

    PCI/X bus, and other system peripherals). Warning: IBM is not responsible for use of the circuit designs on this board or use of the design of the board itself in any other applications. Any functional, reliability, or safety issues resulting from the use of any part of this board design, including copying the board, are the responsibility of the user.
  • Page 14 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Overview Overview.fm Page 14 of 92 May 04, 2007...

  • Page 15: Board Design

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 2. Board Design Figure 2-1 Illustrates the architecture of the evaluation board. Subsequent topics within this section provide more information about each functional block. Figure 2-1. PPC750CL Tsi109 Evaluation Board Architecture DDR2-400 DIMM (240 pin)

  • Page 16: Processor

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 2.1 Processor 2.1.1 60X Bus The 750CL 60x bus connects seamlessly to the Tsi109. The processor bus interface is set at 1.8V. The following 60x bus signals are not supported by the Tsi109 and are pulled appropriately: Table 2-1.

  • Page 17: Power-Up Options

    The Tsi109 has several power-up options; some are system specific while others are application specific (for more information, see the Tsi109 User Manual). The PowerPC 750CL Tsi109 Evaluation Board sets the power-up options with either jumper blocks or soldered down pull-up/pull-down resistors. The list of available power-up options is provided in Section 8 on page 45.

  • Page 18: Board Clocking

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 2.3 Board Clocking Figure 2-2. Board Clocking Block Diagram SD_CLK[0:5] 160MHz differential SSTL_18 DDR2-400 DIMM (240 pin) DDR2-400 DIMM (240 pin) FEEDBACK LOOP E_REF125 Gigabit 25MHz (3.3V) 200MHz Ethernet PB_CLK0 Dual PHY Tsi109...

  • Page 19: Ddr2 Dimm (Memory Module) Connectors

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 2.4 DDR2 DIMM (Memory Module) Connectors The board incorporates two 240-pin DIMM connectors and the appropriate termination circuit. The following memory configurations are supported: • 1 or 2 registered DIMM at DDR2-400 speed •...

  • Page 20: Pci/X Bus

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board • Big FLASH on CS1 • SRAM on CS2 • NVRAM on CS3 The chip select assignment can be modified through jumper blocks for the Small FLASH, SRAM, and Big FLASH (for information on jumper configurations, see Section 8 on page 45).

  • Page 21: Ethernet

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Three PCI/X slots are available on the board. The slot closest to the Tsi109 is designed to meet 133MHz PCI-X timing. The first slot is isolated from the other slots by a FET bus switch. The FET switch reduces the load and the stub length seen from the Tsi109.

  • Page 22: Seep And Real Time Clock

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 2.9 SEEP and Real Time Clock One Serial EEPROM (SEEP) is connected on the Tsi109 I C chain. The device (24LC16) from Microchip is used to store configuration information for the Tsi109. The SEEP is accessed during power up. If it is blank, the Tsi109 uses its default configuration settings.

  • Page 23: Power Rating Per Rail

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 2.10.1 Power Rating Per Rail The power requirement is calculated from “worst case” figures from component datasheets; the real figures are lower. DDR2 power is based on 512M registered modules. 2000mA/rank is an average between Operating Burst Write current and Burst Refresh Current.

  • Page 24: Power Modules

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Figure 2-6. Power Sequencing May ramp up at same time Core_VDD (1.15V) for 750CL PC_VDD (3.3V) PB_VDD (1.8V) for Tsi108 and 750CL IOs VDD (1.2V) SD_VDD (1.8V) 2.10.3 Power Modules The first power module to ramp up on the board is the Austin MicroLynx that supplies 5A to the SD_VDD(1.8V) rail.

  • Page 25: Fan Tachometer

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Figure 2-7. Power Supply Block Diagram 1.8V@5A SD_VDD 5V_ATX Austin MicroLynx Power Module. Vout Adjustable 0.75Vdc to 3.3Vdc Output; ATX pwr good 5A Output Current ON/OFF 108 core_VDD 5V_ATX 1.2V@3A Enable Vout Texas Instr. PTH04070W module 3-A, 3.3/5-V Input, adjustable switching...
  • Page 26 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Board Design Board_design.fm Page 26 of 92 May 04, 2007...

  • Page 27: Memory Map

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 3. Memory Map Table 3-1 provides a summary of the address space usage as seen from the processor bus. For more information about address space usage relating to the processor registers, see the PPC750CL Microprocessor User’s Manual.
  • Page 28 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Memory Map Memory_map.fm Page 28 of 92 May 04, 2007...

  • Page 29: Reset And Interrupts

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 4. Reset and Interrupts Figure 4-1. Board-level Resets Pushbutton FLASH Board reset Gigabit Ethernet PHYs PCI Slots Tsi109 Voltage Power Supervisor OCN_RST supply CPLD Board PCI_RST reset PB_RST JTAG Header Hreset 750CL Sreset...

  • Page 30: Figure 4-2. Board Interrupts

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Figure 4-2. Board Interrupts PCI Slots Tsi109 750CL PCI_INTA PCI_INTB PCI_INTC PCI_INTD PB_INT0 PB_INT1 PB_INT2 Real Time INT1 INT0 Clock Interrupt to the processor is generated by the Tsi109. The Tsi109 Interrupt Controller maps the PCI/X and real-time clock interrupts to the INT, MCP, and SMI pins of the PPC750CL Tsi109.

  • Page 31: Switches

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 5. Switches Figure 5-1. Switch Locations 5.1 Power Switch - SW1 SW1 is a tactile push-button switch. Push once to power up the board; push again to power down. 5.2 Reset Switch - SW2 SW2 is a tactile push-button switch.

  • Page 32: Tsi109 Pll Setting Dip Switch - S1

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 5-1. S2 Settings Switch No Signal Default Setting Set up value Description No signal ON = 0 OFF = 1 No signal PLL_CFG4 PLL_CFG3 PLL_CFG2 ON = 0 OFF = 1 PLL_CFG1...
  • Page 33 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 5-2. S1 Settings (Continued) Switch No Signal Default Setting Set up value Description CD_PB_SEL [2:0]: processor bus clock ratio (resulting frequency) CD_PB_SEL0 000: Bypass 001: Reserved 010: 5.5x (183.33MHz) ON = 0...
  • Page 34 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Switches Switches.fm Page 34 of 92 May 04, 2007...

  • Page 35: Fuses, Regulator And Fan

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 6. Fuses, Regulator and Fan 6.1 Fuses Each of the four voltages provided at the ATX power connector — +5V, +3.3V, +12V, and -12V — are fused at the connector. The fuses are socketed and can be replaced easily if needed.

  • Page 36: Ppc750Cl Regulator

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 6.2 PPC750CL Regulator The PPC750CL core voltage regulator is adjustable. The default value is set at 1.15V. If needed the voltage can the adjusted up or down with resistors that are soldered on-board. If an adjustment is desired, the resistors must be replaced.

  • Page 37: Figure 6-3. R486 Location (Bottom View)

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Figure 6-3. R486 Location (Bottom View) R486 R427 Fuses.fm Fuses, Regulator and Fan Page 37 of 92 May 04, 2007...

  • Page 38: Processor Heatsink And Fan

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 6.3 Processor Heatsink and Fan Figure 6-4. Heatsink and Fan Assembly Thermal dissipation for the processor is handled by a heatsink with an integrated fan. The unit is mounted over the processor (see Figure 6-4). With the fan running, it has a thermal coefficient of 1.2C/W. The fan power plug connects to J5.

  • Page 39: Displays

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 7. Displays Figure 7-1. LED Location GPIO Links Speed Link Status PCI/X Setup Power and Reset Status 7.1 Power and Reset Status LED (D26) D26 indicates the status of the power supply and the state of the power-up reset signal.

  • Page 40: Pci/X Setup Status

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 7.2 PCI/X Setup Status The four LEDs indicate the PCI/X bus configuration status as detected by the PCIX capability detection circuit. There should be only one LED on. Figure 7-2. PCI/X Setup Status LED Location Table 7-2.

  • Page 41: Ethernet Link Status

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 7-3. Ethernet Link Speed Status LED Location Name Color Description Green ON: Indicates a 10Mb/S link speed for Ethernet port A Yellow ON: Indicates data is received on Ethernet port A 100M...

  • Page 42: Gpio

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 7-4. Ethernet Link Status LED Location Color Description Full Duplex Indication, Port A. Green ON: Indicates that the Ethernet link operates in full duplex mode. Link quality indication, Port A ON: Link established and quality is good Yellow OFF: link not established, or quality is not good.

  • Page 43: Gpio Led

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 7-5. GPIO LED Location Color Description ON: GPIO15 is low. Green OFF: GPIO15 is high Displays.fm Displays Page 43 of 92 May 04, 2007...
  • Page 44 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Displays Displays.fm Page 44 of 92 May 04, 2007...

  • Page 45: Jumpers

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 8. Jumpers Figure 8-1. Jumper Location 8.1 J1 – Tsi109 Power-up Configuration Figure 8-2. J1 Jumper Block Pin Assignment Jumpers.fm Jumpers Page 45 of 92 May 04, 2007...

  • Page 46: J11 - Pci/X Bus Fet Switch Control

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board There are four power-up configuration options programmable by shunt jumpers. The jumper block located at location J1 is designed to set a pull-up or a pull-down level to the Host Local Port address signals. Pin 1 is marked by a white dot.

  • Page 47: J14 - Small Flash Chip Select

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 8.3 J14 – Small FLASH Chip Select Figure 8-4. J14 Pin Assignment Tsi109’s HLP chip selects (HLP CS) device assignment is set with shunt jumpers (for more information, see Section 2.5 on page 19). The Small FLASH chip select assignment is set on jumper block J14. On power-up, the Tsi109 maps processor bus address 0xFFF00000 to HLP chip select 0 (CS0).

  • Page 48: J16 - Force Power Supply On

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Section 8.1 on page 45), or by setting Tsi109 internal registers using the Serial EEPROM. If setting the Big FLASH on HLP CS0, the Tsi109 power option must be set to 32-bit wide, latched mode.

  • Page 49: J17 - Sram Cs

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 8.6 J17 – SRAM CS Figure 8-7. J17 Location Tsi109’s HLP chip selects (HLP CS) device assignment is set with shunt jumpers (for more information, see Section 2.5 on page 19). The SRAM chip select assignment is set on jumper block J17. Table 8-6 indicates possible shunt jumper positions.

  • Page 50: J20 - Pcixcap Override

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Note: PCI/X status LEDs are latched (see Section 7.2 on page 40). A board reset is required to update the PCI/X status LEDs. 8.8 J20 – PCIXCAP Override Figure 8-9. J20 Pin Assignment J20 is used to set PCI/X signal PCIXCAP.

  • Page 51: Table 8-9. Cpu Heatsink Fan Detection Override

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Power supply to the board is gated by the CPU heatsink fan tachometer (for more information, see Section 2.10.4 on page 25). Remove the shunt jumper at J21 to disable the fan tachometer detection circuit.
  • Page 52 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Jumpers Jumpers.fm Page 52 of 92 May 04, 2007...

  • Page 53: Connectors

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 9. Connectors Figure 9-1. Connector Location 9.1 J2 – Tsi109 GPIO Figure 9-2. J2 – Pin Assignment Connectors.fm Connectors Page 53 of 92 May 04, 2007...

  • Page 54: J3, J4 - Ddr2 Memory Module Connectors

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Tsi109’s General Purpose Inputs/Outputs (GPIO) are available on a 2x8 connector located at J2. Users can connect an oscilloscope or a logic analyzer to J2 to detect a change of level on GPIO pins.

  • Page 55: Table 9-2. Memory Module Connector Signal Assignment

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board The Tsi109 Memory Controller point-to-point signal assignment is described in Table 9-2. Table 9-2. Memory Module Connector Signal Assignment SD_CLK3 SD_CLK0 Tsi109 clocks SD_CLK4 SD_CLK1 SD_CLK5 SD_CLK2 SD_ODT2 SD_ODT0 Tsi109 On Die Termination...

  • Page 56: Table 9-3. 240-Pin Ddr2 Dimm Pin Assignment (J3 And J4)

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 9-3. 240-Pin DDR2 DIMM Pin Assignment (J3 and J4) Connectors Connectors.fm Page 56 of 92 May 04, 2007...

  • Page 57: J5 - Fan

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 9.3 J5 – Fan Figure 9-4. J5 Pin Assignment The CPU heatsink fan connects on J5. The connector provides power to the fan. Table 9-4. J5 – Heatsink Fan Connector Signal Assignment Pin number...

  • Page 58: J7 - Cpu Jtag Debugger Connector

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 9-5 describes the signal assignments for Serial Ports 0 and 1. Table 9-5. J6 – Dual DB9 RS-232 Serial Port Signal Assignment Pin number Description Upper and Lower No connection RX (input)

  • Page 59: J9 - Tsi109 Jtag Pin Assignment

    PowerPC 750CL Tsi109 Evaluation Board J7 is used to connect a JTAG based debugger to the processor. It is pin compatible with IBM’s RISCWatch. Other debuggers use the same pin out. Pin one is indicated by a white dot on the PCB.

  • Page 60: J10, J12, J13 - Pci/X Connector

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Tsi109’s JTAG port is available on connector J9. Table 9-7. J9 – Tsi109 JTAG Connector Signal Assignment Pin number Description TRST Ground 3.3V Ground Ground Ground 9.7 J10, J12, J13 – PCI/X Connector Figure 9-8.
  • Page 61 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 9-8. PCI/X Connector Pin Description (Continued) Signal Signal Reserved +3.3V (I/O) PRSNT2 Reserved Connector key (for 3.3V PCI-X) Connector key (for 3.3V PCI-X) Connector key (for 3.3V PCI-X) Connector key (for 3.3V PCI-X)
  • Page 62 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 9-8. PCI/X Connector Pin Description (Continued) Signal Signal AD12 AD11 AD10 M66EN C/BE0 +3.3V +3.3V +3.3V (I/O) +3.3V (I/O) ACK64 REQ64 Connector Key (64-bit Spacer) Connector Key (64-bit Spacer) Connector Key (64-bit Spacer)

  • Page 63: J18 - Cpld Jtag

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 9-8. PCI/X Connector Pin Description (Continued) Signal Signal AD44 AD43 AD42 AD41 +3.3V(I/O) AD40 AD39 AD38 AD37 +3.3V(I/O) AD36 AD35 AD34 AD33 AD32 Reserved Reserved Reserved Reserved 9.8 J18 – CPLD JTAG Figure 9-9.

  • Page 64: J22 - Atx Power

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 9.9 J22 – ATX Power Figure 9-10. ATX Power Connector Pin Assignment The ATX power connector provides power to the board and plug-in PCI/X cards. All pins are used except for -5V. Use a standard ATX power supply to power up the board.

  • Page 65: U2 - Rj45 Connector

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 9.10 U2 – RJ45 Connector Figure 9-11. U2 – RJ45 Gigabit Ethernet Connector Pin Assignment Port A Port B Tsi109 PHY 1 Tsi109 PHY 0 U2 is an RJ45 with integrated magnetics designed for Gigabit Ethernet. Port B (right-hand side) is connected to Tsi109 Ethernet MAC 0.
  • Page 66 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Connectors Connectors.fm Page 66 of 92 May 04, 2007...

  • Page 67: Programmable Components

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 10. Programmable Components 10.1 CPLD The CPLD implements very simple combinatorial logic, such as the following four functions. 10.1.1 Board Reset Board reset passes through on-board voltage supervisor reset (includes push-button reset). 10.1.2 750 HRESET Provides the 750CL a 1.8V HRESET input with its source coming from the Tsi109 PB_RESET.

  • Page 68: Seep

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 10.3 SEEP The Serial EEPROM is connected to the I C chain of the Tsi109. It is installed in a DIP8 socket at U34. It can be removed and programmed in a device programmer. If the Tsi109 is used with its default power-up configuration, this device can be blank or not populated.

  • Page 69: Cpld Program

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 11. CPLD Program module 750CL_cpld ( OSC25_CPLD_CLK, /* Reset Control */ POR_RESETn, RISCW_HRESETn, PB_RESETn, BOARD_RESETn, MEMORY_RESETn, HRESET_750n, SRESET_750n, RISCWATCH_SRESETn, /* 750 Data Retry Control */ DRTRY_750n, /* PCI Mode Configuration Control I/O */...
  • Page 70 User’s Manual PowerPC 750CL Tsi109 Evaluation Board GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14, GPIO15 /* CPLD Clock implemented at this time */ input OSC25_CPLD_CLK; /* Reset I/O Directions */ input POR_RESETn,RISCW_HRESETn,PB_RESETn,RISCWATCH_SRESETn; output BOARD_RESETn; output MEMORY_RESETn; output HRESET_750n; output SRESET_750n;...
  • Page 71 User’s Manual PowerPC 750CL Tsi109 Evaluation Board /* General Purpose IO */ inout GPIO8, GPIO9, GPIO10, GPIO11; inout GPIO12, GPIO13, GPIO14, GPIO15; reg [3:0] LED_PCI; reg [15:0] HRESET_CNT; /*************************************************************************/ /* Reset Controller (all active low logic)*/ assign BOARD_RESETn = POR_RESETn;...
  • Page 72 User’s Manual PowerPC 750CL Tsi109 Evaluation Board input. assign SRESET_750n = (PB_RESETn & RISCWATCH_SRESETn); // 750 DRTRY LOGIC assign DRTRY_750n = (HRESET_750n & RISCWATCH_SRESETn); /*************************************************************************/ /* PCI Mode Configuration Controller */ /* Based on M66EN XCAPMSB XCAPLSB 0 1 1 PCI33...
  • Page 73 User’s Manual PowerPC 750CL Tsi109 Evaluation Board endmodule CPLD.fm CPLD Program Page 73 of 92 May 04, 2007...
  • Page 74 User’s Manual PowerPC 750CL Tsi109 Evaluation Board CPLD Program CPLD.fm Page 74 of 92 May 04, 2007...

  • Page 75: Bill Of Materials

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board 12. Bill of Materials This bill of material described in Table 12-1 represents the component list generated by the schematic tools utilized to design the evaluation board. Some components may have been substituted with compatible components from alternate manufacturers.
  • Page 76 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 12-1. PPC750CL Tsi109 Bill of Material (Continued) REFDES PART_NUMBER MANUFACTURER DESCRIPTION POPULATE C118,C119,C120, C121,C122,C123, C125,C126,C127, C128,C129,C130, C131,C132,C136, C137,C138,C139, C140,C141,C142, C143,C144,C146, C147,C148,C149, C150,C151,C152, C155,C158,C159, C160,C161,C162, C163,C164,C165, C166,C167,C168, C169,C170,C171, C172,C173,C184, C219,C220,C221, C222,C223,C225, C226,C227,C229, C230,C231,C232,...
  • Page 77 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 12-1. PPC750CL Tsi109 Bill of Material (Continued) REFDES PART_NUMBER MANUFACTURER DESCRIPTION POPULATE C482,C483,C486, C487,C488,C489, C503,C506,C513, C517,C520,C525, C526,C527,C528, C529,C530,C531, C532,C533,C536, C539,C540,C541, C542,C543,C544, C545,C546,C547 TAJC226K006R TANT SMT, 22UF, +/-10%, 6.3V, 6032-28 C6,C7,C264,C265 12106D107MAT2A AVX X5R CER SMT, 100UF, +/-20%, 6.3V, 1210...
  • Page 78 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 12-1. PPC750CL Tsi109 Bill of Material (Continued) REFDES PART_NUMBER MANUFACTURER DESCRIPTION POPULATE C28,C36,C37, 1206ZD106KAT2A AVX X5R CER SMT, 10UF, +/-10%, 10V, 1206 C58,C59,C62, C98,C109,C110, C113,C135,C153, C154,C156,C290, C404,C511,C549 C33,C300,C318, 12066D226KAT2A AVX X5R CER SMT, 22UF, +/-10%, 6.3V, 1206...
  • Page 79 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 12-1. PPC750CL Tsi109 Bill of Material (Continued) REFDES PART_NUMBER MANUFACTURER DESCRIPTION POPULATE C241,C242,C243, 0402YA180JAT2A AVX NP0 CER SMT, 18PF, +/-5%, 16V, 0402 C244,C245,C246, C247,C248,C249, C250,C251,C252, C253,C254,C255, C256,C257,C258, C259,C260,C261, C262 C274,C524 0603ZC473KAT2A AVX X7R CER SMT, 0.047UF, +/-10%, 10V, 0603...
  • Page 80 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 12-1. PPC750CL Tsi109 Bill of Material (Continued) REFDES PART_NUMBER MANUFACTURER DESCRIPTION POPULATE C408,C409,C410, C411,C412,C413, C414,C415,C416, C417,C418,C425, C426,C427,C433, C434,C435,C436, C437,C438,C444, C445,C446,C447, C448,C449,C450, C451,C452,C453, C454,C455,C459, C460,C461,C462, C463,C464,C465, C466,C470,C471, C472,C473,C474, C475,C478,C479, C480,C481 GRM1885C2A200 C522,C523 MURATA...
  • Page 81 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 12-1. PPC750CL Tsi109 Bill of Material (Continued) REFDES PART_NUMBER MANUFACTURER DESCRIPTION POPULATE MPZ2012S221AT0 SMT FERRITE BEAD, 330OHMS, 3A, 2012 BLM18AG601SN1 SMT FERRITE BEAD, 60OHMS, +/-25%, FB6,FB8,FB11, MURATA 0.2AMPS, 0603 FB13,FB14,FB15 BLM21PG300SN1 SMT FERRITE BEAD, 30OHMS, +/-25%,...
  • Page 82 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 12-1. PPC750CL Tsi109 Bill of Material (Continued) REFDES PART_NUMBER MANUFACTURER DESCRIPTION POPULATE R344,R345,R346, R347,R348,R349, R350,R351,R352, R353,R354,R355, R356,R357,R362, R392,R393,R395, R396,R398,R400, R422,R443,R445, R446,R459,R471, R472,R473,R474, R475,R476,R477, R478,R479,R480, R481,R482,R484 9C06031A0R00JL R7,R14,R15,R39, PHILIPS RES SMT, 0 OHM, 0.1W, 5%, 0603...
  • Page 83 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 12-1. PPC750CL Tsi109 Bill of Material (Continued) REFDES PART_NUMBER MANUFACTURER DESCRIPTION POPULATE R429,R430,R432 R20,R21,R22, ERJ-3GEYJ103V PANASONIC RES SMT, 10K OHM, 0.1W, 5%, 0603 R23,R26,R27, R29,R30,R36, R141,R142,R235, R236,R359,R435, R438,R439,R456, R467,R470 ERJ-3EKF1501V PANASONIC RES SMT, 1.50K OHM, 0.1W, 1%, 0603...
  • Page 84 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 12-1. PPC750CL Tsi109 Bill of Material (Continued) REFDES PART_NUMBER MANUFACTURER DESCRIPTION POPULATE R50,R70,R372, ERJ-3GEYJ242V PANASONIC RES SMT, 2.4K OHM, 0.1W, 5%, 0603 R374 R68,R75,R90, ERJ-3GEYJ202V PANASONIC RES SMT, 2K OHM, 0.1W, 5%, 0603...
  • Page 85 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 12-1. PPC750CL Tsi109 Bill of Material (Continued) REFDES PART_NUMBER MANUFACTURER DESCRIPTION POPULATE R233,R234,R239, R240,R241,R242, R367,R368,R369, R370,R373,R461, R462,R463,R464 R159,R160,R161, ERJ-2GEYJ470X PANASONIC RES SMT, 47 OHM, 0.1W, 5%, 0402 R162,R163,R164, R165,R166,R167, R168,R169,R170, R171,R172,R173, R174,R175,R176,...
  • Page 86 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 12-1. PPC750CL Tsi109 Bill of Material (Continued) REFDES PART_NUMBER MANUFACTURER DESCRIPTION POPULATE R312,R318,R319 R243,R363,R431 ERJ3GEYJ020V PANASONIC RES SMT, 2 OHM, 0.1W, 5%, 0603 R371 ERJ-3GEYJ822V PANASONIC RES SMT, 8.2K OHM, 0.1W, 5%, 0603...
  • Page 87 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 12-1. PPC750CL Tsi109 Bill of Material (Continued) REFDES PART_NUMBER MANUFACTURER DESCRIPTION POPULATE RS-232 TRANSCEIVER, 3.0V TO 5.5V, MAX3232CUE MAXIM TSSOP-16PIN AM29LV040B- 4MEGABIT FLASH, SOCKET FOOTPRINT 120JC K6X4008T1F- SAMSUNG 4MBIT SRAM VB70000 SN74LVC1G14DB...
  • Page 88 User’s Manual PowerPC 750CL Tsi109 Evaluation Board Table 12-1. PPC750CL Tsi109 Bill of Material (Continued) REFDES PART_NUMBER MANUFACTURER DESCRIPTION POPULATE ECS-.327-8-14 32.768KHZ TUNING FORK CRYSTAL ---- 1194 Bill of Materials BOM.fm Page 88 of 92 May 04, 2007...

  • Page 89: Index

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board ethernet speed Index ethernet speed LED Numerics 32-bit FLASH 60x bus fan connector pin 8-bit FLASH fan tachometer features FLASH force power supply fuses about this book ATX power GPIO big FLASH CS...
  • Page 90 User’s Manual PowerPC 750CL Tsi109 Evaluation Board memory S1 settings memory map S2 settings memory module SEEP small FLASH chip select SRAM SRAM CS NVRAM switches overview PCB design PCI M66EN PCIX PCIX bus PCIX LED PCIX setup PCIX switch...

  • Page 91: Revision Log

    User’s Manual PowerPC 750CL Tsi109 Evaluation Board Revision Log Revision Date Modifications 05/04/07 Updated version. 09/30/06 Preliminary version. 07/31/06 Preliminary version. Revlog.fm Revision Log Page 91 of 92 May 04, 2007...

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