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MiTAC Server Board ® S5573 Technical Service Guide An overview of product features, support specifications, function, and installation. Rev. 1.0 | Jan. 2025...
Disclaimer Information contained in this document is furnished by MITAC COMPUTING TECHNOLOGY CORPORATION and has been reviewed for accuracy and reliability prior to printing. MITAC assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale ®...
Document Revision History Table 1. Document and Reference Support Released Date Revision Document Update January 2024 Public release. https://www.mitaccomputing.com/...
Safety Information (Simplified Chinese) G Safety Information (Traditional Chinese) H Ecology Compliance Statements .....................K About This Document ......................9 ® 1. MiTAC Sever Board S5573 ....................10 ® 2. MiTAC Server Board Overview ..................11 2.1 Server System Family Overview 11 2.2 Server System Feature Set 12 ®...
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7.3.10 NVMe Configuration 72 7.3.11 Trusted Computing 73 7.3.12 CSM Configuration 74 7.3.13 Redfish Host Interface Settings 75 7.3.14 Tls Auth Configuration 76 7.3.15 iSCSI Configuration 80 7.3.16 IP4 Network Configuration 82 7.4 CPU Configuration 83 7.4.1 CPU Configuration 84 7.4.2 Power Management 86 7.5 Chipset 88 7.5.1 North Bridge Configuration 89 7.5.2 South Bridge Configuration 94 7.5.3 System Event Log 101 7.6 Server Management 106...
List of Figures ® Figure 1. MiTAC Server Board 10 Figure 2. System Views (Top) 11 Figure 3. Serverboard Features Layout 16 Figure 4. Server Board Architectural Block Diagram 17 Figure 5. Server Board Dimensions and Screw Hole Position 18 Figure 6.
• Dispose of used batteries according to the instructions of the manufacturer. Do not dispose of batteries with the general office waste. For recycling or proper disposal, use a public collection site or return them to MiTAC, your authorized MiTAC partner, or their agents. Caution: Risk of explosion if battery is replaced by an incorrect type.
• Mettez les batteries usagées au rebut en respectant les instructions du fabricant. Ne jetez pas les batteries dans le conteneur d'ordures ménagères du bureau. Pour un recyclage ou une élimination adaptés, allez dans une déchetterie publique ou retournez les batteries à MiTAC, à votre partenaire MiTAC agréé ou à l'un de ses agents.
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• Entsorgen Sie gebrauchte Batterien gemäß den Anweisungen des Herstellers. Entsorgen Sie Batterien nicht im Haushaltsmüll. Um Batterien zu recyceln oder ordnungsgemäß zu entsorgen, bringen Sie diese zu einer öffentlichen Sammelstelle oder geben Sie sie an MiTAC oder einen autorisierten MiTAC-Händler zurück.
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• Smaltire le pile usate attenendosi alle istruzioni del produttore. Non gettare le batterie insieme ai normali rifiuti domestici. Per il riciclo o il corretto smaltimento delle batterie utilizzare il sistema di raccolta pubblico o restituirle a MiTAC, al partner autorizzato MiTAC o a uno dei loro agenti. Attenzione: Sostituendo la batteria con una di tipo non appropriato esiste un rischio di esplosione.
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• Deseche las baterías usadas según las instrucciones del fabricante. No deseche las baterías junto con los residuos comunes de la oficina. Para enviarlas a un centro de reciclaje o desecharlas, utilice el sistema público de recolección o bien, envíelas a MiTAC, al socio autorizado de MiTAC o a sus agentes.
Regulatory Compliance Statements • FCC SDoC Statement (USA) This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
Ecology Compliance Statements MiTAC has a system in place to restrict the use of banned substances in accordance with world- wide product ecology regulatory requirements. Suppliers Declarations of Conformity to the banned substances must be obtained from all suppliers; and a RoHS and REACH Declaration of Compliance must be produced to illustrate compliance.
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Requirement Applies To: Description Server Board Disposal of batteries is regulated under REGULATION (EU) 2023/1542. For information about recycling of your device, please contact EU importer for further information. Server Board UN38.3 Battery Compliance (battery only, not whole bd/system. Available from battery vendor) Server Board California...
Sale samples may not come with any of the accessories listed above. If you have ordered a ® sales sample and you are missing any of the above items, please confirm and contact a MiTAC representative to assist in ordering additional accessories.
RAID 0/1/10/5 via Intel RSTe for increased performance and redundancy. ® Whether for building a reliable server infrastructure or upgrading an existing setup, the MiTAC S5573 Server Board offers the scalability, performance, and flexibility your business needs to thrive.
2. MiTAC Server Board Overview ® This chapter provides a general overview of the MiTAC ® Server Board S5573. More in-depth information can be found in the following chapters. Additional details specific to the server board can be found in the following sections.
2.2 Server System Feature Set ® The following table provides a high-level overview of the features supported by the MiTAC Server Board S5573. Table 2. S5573GMNR-HE Server Board Feature Specifications Q'ty / Socket Type (1) LGA1700 Supported CPU Series Intel Xeon E-2400...
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90%, non-condensing at 35° C Humidity RoHS RoHS 6/6 Compliant Operating System OS supported list Please refer to our AVL support lists. Motherboard (1) S5573 Motherboard Manual (1) Quick Installation Guide Package Contains I/O Shield (1) I/O Shield Cable SATA (2) SATA signal cables...
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Table 3. S5573GM3NR-2V-HE Server Board Feature Specifications Q'ty / Socket Type (1) LGA1700 Supported CPU Series Intel Xeon E-2400 Processor Thermal Design Power Max up to 95W (TDP) Wattage Chipset Intel C266 Supported DIMM Q'ty (4) DIMM slots DIMM Type / Speed DDR5 ECC UDIMM 4800 (1DPC) Memory Capacity...
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90%, non-condensing at 35° C Humidity RoHS RoHS 6/6 Compliant Operating System OS supported list Please refer to our AVL support lists. Motherboard (1) S5573 Motherboard Manual (1) Quick Installation Guide Package Contains I/O Shield (1) I/O Shield Cable SATA (2) SATA signal cables...
3. MiTAC Server Board Feature ® ® ® ® The MiTAC Server Board S5573 is developed around the integrated features of the Intel Xeon E-2400 series Processor and Aspeed AST2600* Server Management Processor (SMP). Figure 3. Serverboard Features Layout https://www.mitaccomputing.com/...
3.1 Server Board Architecture The following figure provides an overview of the server system architecture, showing the features and interconnections of the major subsystem components. Figure 4. Server Board Architectural Block Diagram https://www.mitaccomputing.com/...
3.2 Server Board Mechanical Drawings and Dimensions ® The following figure displays the dimensions and mechanical drawing of the MiTAC server board. Board Dimensions 244.86mm (Width) x 244.86mm (Depth) x 1.57mm (Height) Figure 5. Server Board Dimensions and Screw Hole Position...
3.3 Server Board Connector / Header Pin-out Definition This section identifies the location and pinout for most server board connectors and headers on the server board. Figure 6. Server Board Features Identification https://www.mitaccomputing.com/...
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Table 4. Jumper and Connector Connectors 1. COM Port Header (J_COM2) 18. CPU0 Fan Header (J_CPU_FAN) 2. IPMB Pin Header (J_IPMB) 19. System Fan Header (J_SYS_FAN_2) 3. SPI TPM Connector Pin-out (J_TPM) 20. System Fan Header ( J_SYS_FAN_1) 4. TPM connector 21.
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Table 6. COM Port Header (J_COM2) Signal Signal Ref. 1 10 KEY-PIN Table 7. IPMB Pin Header (J_IPMB) Signal Signal SPI Clock P3V3_AUX PLTRST Present Pin SPI MOSI IRQ_TPM_N SPI MISO 10 P3V3 Ref. 2 SPI Chip Select 11 GND Table 8.
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Table 11. SATA Connectors (J_SATA4, J_SATA5) Signal Ref. 8 Ref. 9 Table 12. SATA DOM Connectors (J_SATA6, J_SATA7) Signal Ref. 10 Ref. 11 Table 13. Mini SAS HD (J_SATA_0_3) Signal Signal A3 GND C3 GND B4 RXA0_DP D4 TXA0_DP B5 RXA0_DN D5 TXA0_DN A6 GND C6 GND...
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Table 14. Internal USB2.0 Header (J_USB2_FPIO1) Signal Signal P0_N P1_N P0_P P1_P Ref. 13 10 NC Table 15. System Fan Header (J_SYS_FAN_1, J_SYS_FAN_2, J_SYS_FAN_3, J_SYS_FAN_4, J_SYS_FAN_5) Signal P12V Ref. 16, 17, 19, TACH 20, 31 Table 16. CPU0 Fan Header (J_CPU_FAN) Signal P12V TACH...
3.4 Server Board LED ® The MiTAC Server Board S5573 includes several LEDs used to provide system status and diagnostic aids. Some LEDs are only viewable from the inside of the server chassis. This chapter identifies the internal LEDs on the server board.
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Table 38. Server Board LED Status Location Description Signal VCC3_AUX LED_CATERR CPU Error LED CAT_LED1 State Description No CPU Error CPU Error Signal VCC3_AUX BMC_HW_FAULT_N BMC Event IPMI_LED1 State Description No BMC event log Amber BMC event log Signal VCC3 HDD_ACT_LED_N HDD active iii.
3.5 Server Board Sensors ® The following figure provides the location of the sensors on the MiTAC Server Board. The following table provides a list of the sensors available. Figure 8. Server Board Sensor Identication Note: The blue dot indicates the sensor.
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Table 39. Temperature Sensor BIOS Temp Sensor Name Explanation P0_Temp_T Temperature of P0 P0_DTS_Margin_1 Temperature of P0 DTS_Margin_1 P0_MOSFET_1 Temperature of the P0_MOSFET_1Area PCH_T Temperature of PCH P0_CHA_DIM0_T Temperature of CPU0 Channel A DIMM0 P0_CHA_DIM1_T Temperature of CPU0 Channel A DIMM1 P0_CHB_DIM0_T Temperature of CPU0 Channel B DIMM0 P0_CHB_DIM1_T...
Note: MITAC MiTAC is not liable for damage as a result of operating an unsupported configuration. 4.1 Processor Installation Follow the steps below to install the processors and heat sinks. Please note that the illustrations are based on socket which may not look exactly like the motherboard you purchased. Therefore, the illustrations should be held for your reference only.
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4. Close the load plate. Figure 12. Close Processor Load Plate 5. Remove and save the ILM cover. Figure 13. Remove Processor ILM Cover Note: Please save and replace the flip CPU protection cap when returning for service. 6. Close the ILM lever and latch. Figure 14.
4.2 Heat Sink Installation After installing the processor, proceed to install the heat sink. The CPU heat sink will ensure that the processor do not overheat and continue to operate at maximum performance for as long as you own them. An overheated processor is dangerous to the motherboard. The processors will overheat within seconds, enter thermal protection, and shut down if heat sinks are not installed.
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Figure 18. CPU Heat Sink There are two types of thermal interface materials designed for use with the processor. The most common material comes as a small pad attached to the heat sink at the time of purchase. There should be a protective cover over the material. Take care not to touch this material.
5. System Memory This chapter describes the memory subsystem, supported memory types, and memory population rules. 5.1 Supported Memory ® MiTAC server board S5573 supports DDR5 UDIMMs with the following features: • 2 channels DDR5 • 2 DPC UDIMM ECC •...
5.2 Memory Subsystem Architecture The server board includes eight memory slots per processor as shown in the following figure. Figure 19. Server board DIMM Identification 5.3 Memory Population Product may not support all variations that the reference platform can support. Table 41. DIMM Configurations iMC0 Ch A Ch B...
5.4 Memory Module Replacement Required Tools and Supplies • Anti-static wrist strap and conductive workbench pad (recommended) • Replacement equivalent memory module Notes: Memory modules are not hot-swappable. Before replacing a faulty memory module in the system, power down the system and unplug the AC power source for at least 30 seconds, ensuring all power supply status LEDs and board LEDs are off.
6. PCI Express* (PCIe*) Support The Intel® Xeon® E-2400 processor provides up to 16 PCIe bus lanes that support the PCIe Express Base Specification, Revision 5.0. Figure 23. PCIe Subsystem Architecture Notes: ® The single processor configuration is required to support all onboard PCIe features. Intel link speed 4800 MT/s depends on the Intel ®...
6.1 PCIe Card Slot The server board includes 3 riser slots, identified in the following location, J_PCIE4, J_PCIE5 and J_PCIE6. PCIe 5.0 bus lanes for each riser slot is supported from CPU-0. Figure 24. PCIe Card Slot Location Notes: • Install add-on cards in a staggered arrangement rather than placing them directly next to each other.
6.2 Power Supply Connector The server board includes 2 power supply connectors. Note: Unplug the power supply before plugging the power cables to server board connectors. Figure 25. Power Connector Location Table 42. Power Connector (J_PWR1) Signal Signal P3V3 13 P3V3 P3V3 14 VCC12N 15 GND...
7. BIOS Setup 7.1 About the BIOS The BIOS is the basic input/output system, the firmware on the server board that enables your hardware to interface with your software. The BIOS determines what a computer can do without accessing programs from a disk. The BIOS contains all the code required to control the keyboard, display screen, disk drives, serial communications, and a number of miscellaneous functions.
Chipset section unless you are absolutely sure of what you are doing. The Chipset defaults have been carefully chosen either by MITAC or your system manufacturer for best performance and reliability. Even a seemingly small change to the Chipset setup options may cause the system to become unstable or unusable.
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Table 45. BIOS Setup Screen Map Top-Level Categories Second Level Screens Third Level Screens Main Screen Network Stack Configuration S5 RTC Wake Settings Serial Port Console Redirection Legacy Console Redirection Settings PCIe Device Configuration Option ROM Dispatch Policy USB Configuration Onboard Device Configuration Super IO Configuration Serial Port 1 / 2 Configuration...
7.2 Main In this section, you can alter general features such as the date and time. Note: The options listed below are for options that can directly be changed within the Main Setup screen. Figure 26. Main Screen Page BIOS Information It displays product name, BIOS version and build date and time.
7.3 Advanced This section facilitates configuring advanced BIOS options for your system. Figure 27. Adanced Screen Page Notes: This is a sample screenshot of the Advanced Menu. The HII network drivers displayed here depend on the card(s) you installed and the functions you enabled. Network Stack Configuration Network Stack Settings.
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Onboard Device Configuration Onboard Device and Function Configuration. Super IO Configuration System Super IO Chip Parameters. Hardware Health Configuration Hardware Health Configuration. PCI Subsystem Settings PCI, PCI-X and PCI Express Settings. NVMe Configuration NVMe Device Information. Trusted Computing Trusted Computing settings. CSM Configuration CSM Configuration, Enable/Disable Option ROM execution setting, etc.
7.3.1 Network Stack Configuration Figure 28. Network Stack Screen Page Network Stack Enable/Disable UEFI Network Stack. Enabled / Disabled Note: When Network Stack was set to [Enabled], the following item will appear. IPv4 PXE Support Enable/Disable IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available. Enabled / Disabled IPv4 HTTPs Support Enable/Disable IPv4 HTTPs boot support.
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IPv6 HTTPs Support Enable/Disable IPv6 HTTPs boot support. If disabled, IPv6 HTTPS boot support will not be available. Enabled / Disabled PXE boot wait time Wait time in seconds to press ESC key to abort the PXE boot. Use either +/- or numeric keys to set the value.
7.3.2 S5 RTC Wake Settings Figure 29. S5 RTC Wake Settings Screen Page Wake system from S5 Enable or disable System wake on alarm event. Select FixedTime, system will wake on the hr::min::sec specified. Select DynamicTime, system will wake on the current time + Increase minute(s).
7.3.3 Serial Port Console Redirection Figure 30. Serial Port Console Redirection COM1/COM2 Console Redirection Console redirection enable or disable. Enabled / Disabled Legacy Console Redirection Legacy Console Redirection Settings. Serial Port for Out-Of-Band Management/Windows Emergency Services (EMS) Console Redirection Console redirection enable or disable. Enabled / Disabled Console Redirection Settings The settings specify how the host computer (which the user is using) will exchange data.
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7.3.3.1 Legacy Console Redirection Settings Figure 31. Legacy Console Redirections Settings Screen Page Redirection COM Port Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages. COM1 Resolution On Legacy OS, the Number of Rows and Columns supported redirection. 80x24 / 80x25 Redirect After POST When Bootloader is selected, then Legacy Console Redirection is disabled before booting to...
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7.3.4.1 Option ROM Dispatch Policy Figure 33. Option ROM Dispatch Policy Screen Page LAN1 Option ROM Enable/Disable LAN Option ROM. Enabled / Disabled LAN2 Option ROM Enable/Disable LAN Option ROM. Enabled / Disabled LAN3 Option ROM Enable/Disable LAN Option ROM. Enabled / Disabled PCIE #1/#2/#3 Option ROM Enable or Disable Option ROM execution for selected Slot.
7.3.5 USB Configuration Figure 34. USB Configuration Screen Page Legacy USB Support Enables USB legacy support. AUTO option disables legacy support if no USB devices are connected. DISABLE option will keep USB devices available only for EFI applications. Enabled / Disabled / Auto XHCI Hand-off This is a workaround for OSes without XHCI hand-off support.
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USB transfer time-out The time-out value for Control, Bulk and Interrupt transfers. 1 sec / 5 sec / 10 sec / 20 sec Device reset time-out USB mass storage device Start Unit command time-out. 10 sec / 20 sec / 30 sec / 40 sec Device power-up delay Maximum time the device will take before it properly reports itself to the Host Controller.
7.3.7 Super IO Figure 36. Super IO Screen Page Serial Port 1/2 Configuration Set Parameters of Serial Port 1/2 (COMA) . https://www.mitaccomputing.com/...
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7.3.7.1 Serial Port 1 / 2 Configuration Figure 37. Onboard Device Configuration Screen Page Serial Port Enable or Disable Serial Port (COM). Enabled / Disabled Note: Serial Port has set to Enabled, the following items will be appear. Device Settings Device Settings parameters. IO=2F8h;...
7.3.8 Hardware Health Configuration Figure 38. Hardware Health Configuration Screen Page Fan Speed Control Fan Speed Control help. Manual / Full Speed Note: When Auto Fan Control is set to [Manual], PWM Minimal Duty Cycle item will appear. PWM Minimal Duty Cycle PWM Minimal Duty Cycle.
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Sensor Data Register Monitoring Sensor Data Register Monitoring information. https://www.mitaccomputing.com/...
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7.3.8.1 Sensor Data Register Monitoring When you enter the Sensor Data Register Monitoring submenu, you will see the following dialog window pop out. Please wait 8~10 seconds. Figure 39. Sensor Data Register Monitoring Screen Page 1 https://www.mitaccomputing.com/...
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7.3.9 PCI Subsystem Settings Figure 40. PCI Subsystem Settings Screen Page Above 4G Decoding Enables or Disables 64bit capable Devices to be decoded in Above 4G Address Space(Only if System supports 64 bit PCI Decoding). Enabled / Disabled SR-IOV Support If system has SR-IOV capable PCIe devices, this option Enables or Disables Single Root IO virtualization Support Enabled / Disabled PCI Express Settings...
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7.3.9.1 PCI Express Subsystem Figure 41. PCI Express Subsystem Screen Page Maximum Payload Set Maximum Payload of PCI Express Device or allow System BIOS to select the value. Auto / 128 Bytes / 256 Bytes / 512 Bytes / 1024 Bytes / 2048 Bytes / 4096 Bytes https://www.mitaccomputing.com/...
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7.3.10 NVMe Configuration Figure 42. NVMe Configuration Screen Page 1 It displays the information of the NVMe device you have installed. If no device is installed, it shows NO NVME Device found. https://www.mitaccomputing.com/...
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7.3.11 Trusted Computing Figure 43. Trusted Computing Screen Page Security Device Support Enables or disables BIOS support for security device. O.S. will not show Security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. Enabled / Disabled https://www.mitaccomputing.com/...
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7.3.14 Tls Auth Configuration Figure 46. T1s Auth Configuration Screen Page Server CA Configuration Press Enter to configure Server CA. Client Cert Configuration Press Enter to configure Client Cert. https://www.mitaccomputing.com/...
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7.3.14.1 Server CA Configuration Figure 47. Server CA Configuration Screen Page Enroll Cert Press Enter to enroll cert. Delete Cert Press Enter to delete cert. https://www.mitaccomputing.com/...
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7.3.14.1.1 Enroll Cert Figure 48. Enroll Cert Screen Page Enroll Cert Using File Enroll Cert Using File. Cert GUID Input digit character in 11111111-2222-3333-4444-1234567890ab format. Commit Changes and Exit Commit Changes and Exit. Discard Changes and Exit Discard Changes and Exit. https://www.mitaccomputing.com/...
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7.3.15.1 Host iSCSI Configuration Figure 51. Host iSCSI Configuration Screen Page Add an Attempt Add an attempt. Delete Attempts Use to delete one or more attempts. Change Attempt Order Use to change the order of attempts. Use arrow keys to select the attempt, then press plus or minus (+/-) keys to move the attempt up/down in the attempt order list.
7.4 CPU Configuration Figure 53. CPU Configuration Screen Page CPU Configuration CPU Configuration Parameters. Power Management Control Displays and provides option to change the power management control settings. https://www.mitaccomputing.com/...
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7.4.1 CPU Configuration Figure 54. CPU Configuration Screen Page Hardware Prefetcher To turn on/off the MLC Streamer Prefetcher. Enabled / Disabled Adjacent Cache Line Prefetch Enable/Disable Adjacent Cache Line Prefetch function. Enabled / Disabled Enable/Disable AVX function. Enabled / Disabled Intel Trusted Execution Technology Enable/Disable Intel Trusted Execution Technology function.
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7.4.2 Power Management Figure 55. Power Management Screen Page Intel(R) SpeedStep(tm) Allows more than two frequency ranges to be supported. Enabled / Disabled Intel(R) Speed Shift Technology Intel(R) Speed Shift Technology support function. Native Mode / Out of Band Mode / Disabled Turbo Mode Enable/Disable processor turbo mode.
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Enhanced C-States Enable/Disable C1E. When enabled, CPU will switch to minimum speed when all cores enter C-State. Enabled / Disabled C-State Auto Demotion C1 / Disabled C-State Un-demotion C1 / Disabled Package C-State Demotion Enabled / Disabled Package C-State Un-Demotion Enabled / Disabled Package C-State Limit Auto / C0 / C1 / C2 / C3 / C6 / C7 / C7S / CPU Default...
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7.5 Chipset Figure 56. Chipset Screen Page North Bridge North Bridge Parameters. South Bridge South Bridge Parameters. System Event Log System Event Main Screen. https://www.mitaccomputing.com/...
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7.5.1 North Bridge Configuration Figure 57. North Bridge Configuration Screen Page Memory Configuration Memory configuration parameters. DMI Configuration Control various DMI functions. PCI Express Configuration PCI Express Configuration parameters. VT-d Enable/Disable VT-d function. Enabled / Disabled https://www.mitaccomputing.com/...
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7.5.1.1 Memory Configuration Figure 58. Memory Configuration Screen Page Maximum Memory Frequency Maximum Memory Frequency Selections in MHz. Auto / 3600 / 4000 / 4400 /4800 ECC Support Enable/Disable ECC Support. Enabled / Disabled Max TOLUD Select he maximum value of TOLUD. Dynamic / 1 GB / 1 .25 GB / 1.5 GB / 1.75 GB / 2 GB / 2.25 GB / 2.5 GB / 2.75 GB / 3 GB / 3.25 GB / 3.5 GB https://www.mitaccomputing.com/...
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7.5.1.2 DMI Configuration Figure 59. DMI Configuration Screen Page DMI Max Link Speed Set DMI Speed Gen1/Gen2/Gen3/Gen4. Auto / Gen1 / Gen2 / Gen3 / Gen4 DMI ASPM Set the DMI ASPM Support. Auto / ASPM L0s / ASPM L1 / ASPM L0sL1 / Disabled https://www.mitaccomputing.com/...
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7.5.1.3 PCI Express Configuration Figure 60. PCI Express Configuration Screen Page PCI Express Root Port 1/2/3 Control the PCI Express Root Settings. https://www.mitaccomputing.com/...
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7.5.1.3.1 PCI Express Configuration Figure 61. PCI Express Root Port 1~3 Screen Page PCI Express Root Port 1/2/3 Control the PCI Express Root Port. Enabled / Disabled ASPM PCI Express Active State Power Management settings. Disabled / L0s / L1 / L0sL1 Enable/Disable Access Control Service.
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7.5.2 South Bridge Configuration Figure 62. South Bridge Configuration Screen Page PCH-IO Configuration PCH-IO parameters. Server ME Configuration Server ME configuration. Restore AC Power Loss Select Restore AC Power Loss Method. Power Off / Power On / Last State https://www.mitaccomputing.com/...
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7.5.2.1 PCH-IO Configuration Figure 63. PCH-IO Configuration Screen Page PCI Express Configuration PCIe Exress Configuration settings. SATA and RSTe Configuration SATA and RSTe Configuration settings. https://www.mitaccomputing.com/...
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7.5.2.1.1 PCI Express Configuration Figure 64. PCI Express Configuration DMI Link ASPM Control The control of Active State Power Managemnt of the DMI Link. Disabled / L1 / Auto Compliance Test mode Enable/Disable Compliance Test Mode. Enabled / Disabled PCI Express Root Port 1/3/4/5/9/21/25 PCI Express Root Port settings.
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7.5.2.1.1.1 PCI Express Root Port 1/3/4/5/9/21/25 Figure 65. PCI Express Root Port 1 PCI Express Root Port 1/2/3 Control the PCI Express Root Port. Enabled / Disabled ASPM PCI Express Active State Power Management settings. Disabled / L1 / Auto Enable/Disable Access Control Service.
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7.5.2.1.2 SATA and RSTe Configuration Figure 66. SATA and RSTe Configuration Screen Page 1 https://www.mitaccomputing.com/...
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Figure 67. SATA and RSTe Configuration Screen Page 2 SATA Controller Enable/Disable SATA Device. Enabled / Disabled SATA Mode Selection Determines how SATA controller(s) operate. AHCI / RAID Aggressize LPM Support Disable/Enable PCH to aggressively enter link power state. Enabled / Disabled SATA Port 0/1/2/3/4/5/6/7 Enabled / Disabled SATA Port 0/1/2/3/4/5/6/7 Hot Plug...
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7.5.2.2 Server ME Configuration Figure 68. Server ME Configuration Screen Page Read only. https://www.mitaccomputing.com/...
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7.5.3 System Event Log Figure 69. System Event Log Screen Page System Errors Enable/Disable System Error setup options. Enabled / Disabled WHEA Driver Support Enable/Disable Windows Hardware Error Architecture driver support. Enabled / Disabled WHEA FFM Logging Enable/Disable Windows Hardware Error Architecture FFM Logging. Enabled / Disabled WHEA/UEFI Record Format WHEA/UEFI Record FFM Error record format.
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PCH Error Enable Enable/Disable PCH Error Enabling. Enabled / Disabled PCIe Error Enabling Press <Enter> to view or change the PCIe Error Enabling options. https://www.mitaccomputing.com/...
7.6 Server Management Figure 72. Server Management Screen Page FRB-2 Timer Enable or Disable FRB-2 timer (POST timer) Disabled / Enabled Note: When FRB-2 Timer is set to [Enabled], the following items will be available. FRB-2 Timer timeout Enter value Between 3 to 6 min for FRB-2 Timer Expiration value. 3 minutes / 4 minutes / 5 minutes / 6 minutes / 12 minutes FBR-2 Timer Policy Configure how the system should respond if the FRB-2 Timer expires.
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OS Watchdog Timer If enabled, starts a BIOS timer which can only be shut off by management Software after the OS loads. Helps determine that the OS successfully loaded or follows the OS Boot Watchdog Timer policy. Disabled / Enabled Note: When OS Watchdog Timer is set to [Enabled], the following items will be available.
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7.6.1 System Event Log Figure 73. System Event Log Screen Page SEL Components Change this to enable or disable event logging for error/progress codes during boot. Enabled / Disabled Erase SEL Choose options for erasing SEL. No / Yes, on next reset / Yes, on every reset Log EFI Status Codes Disable the logging of EFI Status Codes or log only error code or only progress code or both.
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Figure 75. BMC Network Configuration Screen Page 2 Configure IPV4 support Management Port 1 Configuration Address Source Select the configure LAN channel parameters statically or dynamically (by BIOS or BMC). Unspecified option will not modify any BMC network parameters during BIOS phase. Unspecified / Static / DynamicBmcDhcp / DynamicBmcNonDhcp Management Port 2 Enable/Disable BMC Share NIC.
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Configuration Address Source Select the configure LAN channel parameters statically or dynamically (by BIOS or BMC). Unspecified option will not modify any BMC network parameters during BIOS phase. Unspecified / Static / DynamicBmcDhcp / DynamicBmcNonDhcp Management Port 2 IPV6 Support Enable or Disable LAN2 IPV6 Support.
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7.6.3 BMC User Settings Figure 76. BMC User Configuration Screen Page Add User Press Enter to Add a User. Delete User Press Enter to Delete a User. Change User Settings Press Enter to Change User Settings. https://www.mitaccomputing.com/...
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7.6.3.1 Add User Figure 77. Add User Screen Page User Name Enter BMC User Name. User Password Password must be between 8 and 20 characters. Password must contain characters from 3 of the following 4 categories: -Uppercase Characters (A-Z) -Lowercase Characters (a-z) -Digits (0-9) -Special Characters (non-alphanumeric characters) User Access...
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7.6.3.2 Delete User Figure 78. Delete User Screen Page User Name Enter BMC User Name. User Password Password must be between 8 and 20 characters. Password must contain characters from 3 of the following 4 categories: -Uppercase Characters (A-Z) -Lowercase Characters (a-z) -Digits (0-9) -Special Characters (non-alphanumeric characters) https://www.mitaccomputing.com/...
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7.6.3.3 Change User Setting Figure 79. Change User Configuration Screen Page User Name Enter BMC User Name. User Password Password must be between 8 and 20 characters. Password must contain characters from 3 of the following 4 categories: -Uppercase Characters (A-Z) -Lowercase Characters (a-z) -Digits (0-9) -Special Characters (non-alphanumeric characters)
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Channel No Enter BMC Channel Number. N/A / 1 / 8 User Privilege Limit Enter BMC User Privilege Limit for Selected Channel. None / User / Operator / Administrator https://www.mitaccomputing.com/...
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7.7 Security Figure 80. Security Screen Page Administrator Password Set Administrator Password. User Password Set User Password. Security Frozen Mode Enable or disable HDD security freeze lock. Disable to support secure erase function. Disabled / Enabled Secure Boot Customizable Secure Boot settings. https://www.mitaccomputing.com/...
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7.7.1 Secure Boot Figure 81. Secure Boot Configuration Screen Page Secure Boot Secure boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode. The mode change requires platform reset. Enabled / Disabled Secure Boot Mode Secure Boot mode options: Standard or Custom.
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Reset to Setup Mode Delete all Secure Boot key database from NVRAM. Deleting all variables will reset the System to Setup Mode. Press Yes to proceed No to cancel. Key Management Enables expert users to modify Secure Boot Policy variables without full authentication. https://www.mitaccomputing.com/...
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7.8 Boot Figure 82. Boot Screen Page Setup Prompt Timeout Number of seconds to wait for setup activation key. 65535 (0xFFFF) means indefinite waiting. Bootup NumLock State Select the keyboard NumLock state. Off / On Quiet Boot Enable or disable Quiet Boot option. Enabled / Disabled Wait for ‘ESC’...
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Boot Option Priorities Boot Option #1 Select the system boot order. Device Name / Disabled Delete Boot Option Remove an EFI boot option from the boot order. https://www.mitaccomputing.com/...
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7.8.1 Delete Boot Option Figure 83. Delete Boot Option Configuration Screen Page Delete Boot Option Remove an EFI boot option from the boot order. Device Name / Select one to Delete https://www.mitaccomputing.com/...
7.9 Save and Exit Figure 84. Save and Exit Screen Page Save Changes and Exit Exit system setup after saving the changes. Discard Changes and Exit Exit system setup without saving any changes. Save Changes and Reset Reset the system after saving the changes. Discard Changes and Reset Reset system setup without saving any changes.
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Restore Defaults Restore/Load Default values for all the setup options. Save as User Defaults Save the current settings as the user default settings. Restore User Defaults Restore the current settings as the user default settings. https://www.mitaccomputing.com/...
BIOS. There are no exceptions. MiTAC does not have a policy for replacing BIOS chips directly with end users. In no event will MiTAC be held responsible for damages done by the end user.
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Table 47. Standard Checkpoints SEC Phase Status Code Description 0x00 Not used Progress Codes SEC errors 0x01 Power on. Reset type detection (soft/hard). 0x02 AP initialization before microcode loading 0x03 North Bridge initialization before microcode loading 0x04 South Bridge initialization before microcode loading 0x05 OEM initialization before microcode loading 0x06...
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Status Code Description 0x32 CPU post-memory initialization is started 0x33 CPU post-memory initialization. Cache initialization 0x34 CPU post-memory initialization. Application Processor(s) (AP) initialization 0x35 CPU post-memory initialization. Boot Strap Processor (BSP) selection 0x36 CPU post-memory initialization. System Management Mode(SMM) initialization 0x37 Post-Memory North Bridge initialization is started 0x38...
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DXE Phase Status Code Description 0x60 DXE Core is started 0x61 NVRAM initialization 0x62 Installation of the South Bridge Runtime Services 0x63 CPU DXE initialization is started 0x64 CPU DXE initialization (CPU module specific) 0x65 CPU DXE initialization (CPU module specific) 0x66 CPU DXE initialization (CPU module specific) 0x67...
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Status Code Description 0xA0 IDE initialization is started 0xA1 IDE Reset 0xA2 IDE Detect 0xA3 IDE Enable 0xA4 SCSI initialization is started 0xA5 SCSI Reset 0xA6 SCSI Detect 0xA7 SCSI Enable 0xA8 Setup Verifying Password 0xA9 Start of Setup 0xAA Reserved for ASL (see ASL Status Codes section below) 0xAB Setup Input Wait...
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Table 48. ACPI/ASL Checkpoints Status Code Description 0x01 System is entering S1 sleep state 0x02 System is entering S2 sleep state 0x03 System is entering S3 sleep state 0x04 System is entering S4 sleep state 0x05 System is entering S5 sleep state 0x10 System is waking up from the S1 sleep state 0x20...
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BIOS recovery process is underway or there is risk of damage to the UEFI recovery bootloader that would prevent the recovery process itself from working. In no event shall MiTAC be liable for direct, indirect, incidental, special or consequential damages arising from the BIOS update or recovery.
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7. Remove the USB disk and reboot. Notes: If your system does not have video output or the POST code halts at “FF” on the right-lower portion of the screen, please contact a MiTAC representatives for RMA service. https://www.mitaccomputing.com/...
Appendix I. System Component Board This chapter provides specifications for system component boards besides the serverboard. This item include: • M5573-B502-2V module (for S5573GM3NR-2V-HE SKU) All other components in the system can only be serviced after the system has been powered off and AC power cords have been disconnected from the server system.
• A searchable knowledge base to search for product information throughout the support site 1. If a solution cannot be found at MiTAC support site, submit a service request via MiTAC online service center at https://www.mitaccomputing.com/EN/service-center. In addition, you can also view previous support requests. (Login required to access previous support requests) 2.
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Glossary Term Definition ACPI (Advanced Configuration and Power Interface) is a power management specification that allows the operating system to control the amount of power ACPI distributed to the computer’s devices. Devices not in use can be turned off, reducing unnecessary power expenditure. AGP (Accelerated Graphics Port) is a PCI-based interface which was designed specifically for demands of 3D graphics applications.
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ROM chip which can, unlike normal ROM, be updated. This allows you to EEPROM keep up with changes in the BIOS programs without having to buy a new chip. MiTAC BIOS updates can be found at https://www.mitaccomputing.com/ ESCD (Extended System Configuration Data) is a format for storing information ESCD about Plug-n-Play devices in the system BIOS.
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Term Definition IDE Interrupt is the hardware interrupt signal that goes to the IDE. IDE INT I/O (Input/Output) is the connection between your computer and another piece of hardware (mouse, keyboard, etc.) IRQ (Interrupt Request) is an electronic request that runs from a hardware device to the CPU.
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Term Definition RAM (Random Access Memory) technically refers to a type of memory where any byte can be accessed without touching the adjacent data and is often referred to the system’s main memory. This memory is available to any program running on the computer.
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