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NXP Semiconductors MWCT1014SF Series Reference Manual

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MWCT101xS Series Reference

Manual

Supports MWCT1014SFxxx, MWCT1015SFxxx, MWCT1016SFxxx

Document Number: MWCT101XSFRM

Rev. 3, 07/2019

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Summary of Contents for NXP Semiconductors MWCT1014SF Series

Page 1 MWCT101xS Series Reference Manual Supports MWCT1014SFxxx, MWCT1015SFxxx, MWCT1016SFxxx Document Number: MWCT101XSFRM Rev. 3, 07/2019...
Page 2 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 3: Table Of Contents
Feature comparison...............................56 Applications.................................. 58 Module functional categories............................58 2.7.1 Arm Cortex-M4F Core Modules........................59 2.7.2 System modules............................. 60 2.7.3 Memories and memory interfaces........................61 2.7.4 Power Management............................62 2.7.5 Clocking................................. 62 2.7.6 Analog modules............................. 62 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 4 Pinout diagrams................................77 Chapter 5 Security Overview Introduction...................................79 Device security................................79 5.2.1 Flash memory security........................... 79 5.2.2 Cryptographic Services Engine (CSEc) security features................80 5.2.3 Device Boot modes............................81 Security use case examples............................81 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 5 Buses, interconnects, and interfaces......................98 7.1.2 System Tick Timer............................98 7.1.3 Debug facilities.............................. 98 7.1.4 Caches................................99 7.1.5 Core privilege levels............................99 Nested Vectored Interrupt Controller (NVIC) Configuration..................100 7.2.1 Interrupt priority levels..........................100 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 6 LMEM Fault Address Register (MCM_LMFAR)..................126 8.3.12 LMEM Fault Attribute Register (MCM_LMFATR)..................127 8.3.13 LMEM Fault Data High Register (MCM_LMFDHR).................. 128 8.3.14 LMEM Fault Data Low Register (MCM_LMFDLR)..................128 Functional description..............................129 8.4.1 Interrupts................................ 129 Chapter 9 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 7 Global Pin Control High Register (PORTx_GPCHR)................... 175 10.6.4 Global Interrupt Control Low Register (PORTx_GICLR)................176 10.6.5 Global Interrupt Control High Register (PORTx_GICHR)................176 10.6.6 Interrupt Status Flag Register (PORTx_ISFR)....................177 10.6.7 Digital Filter Enable Register (PORTx_DFER).....................177 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 8 Functional description..............................193 11.4.1 General-purpose input............................193 11.4.2 General-purpose output..........................193 Chapter 12 Crossbar Switch Lite (AXBS-Lite) 12.1 Chip-specific AXBS-Lite information..........................195 12.1.1 Crossbar Switch master assignments......................195 12.1.2 Crossbar Switch slave assignments........................195 12.2 Introduction...................................196 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 9 Region Descriptor n, Word 1 (RGD1_WORD1 - RGD15_WORD1)............219 13.4.10 Region Descriptor n, Word 2 (RGD1_WORD2 - RGD15_WORD2)............220 13.4.11 Region Descriptor n, Word 3 (RGD1_WORD3 - RGD15_WORD3)............223 13.4.12 Region Descriptor Alternate Access Control 0 (RGDAAC0)............... 225 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 10 Chip-specific DMAMUX information......................... 285 15.1.1 Number of channels ............................285 15.1.2 DMA transfers via TRGMUX trigger......................285 15.2 Introduction...................................285 15.2.1 Overview................................ 286 15.2.2 Features................................286 15.2.3 Modes of operation............................287 15.3 Memory map/register definition........................... 287 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 11 DMA register descriptions..........................302 16.5 Functional description..............................351 16.5.1 eDMA basic data flow........................... 351 16.5.2 Fault reporting and handling.......................... 354 16.5.3 Channel preemption............................357 16.6 Initialization/application information........................... 357 16.6.1 eDMA initialization............................357 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 12 EWM low-power modes..........................417 18.2 Introduction...................................418 18.2.1 Features................................418 18.2.2 Modes of Operation............................419 18.2.3 Block Diagram............................... 419 18.3 EWM Signal Descriptions............................420 18.4 Memory Map/Register Definition..........................421 18.4.1 EWM register descriptions..........................421 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 13 Error Injection Channel Descriptor n, Word1 (EICHD0_WORD1 - EICHD1_WORD1)......440 19.4 Functional description..............................441 19.4.1 Error injection scenarios..........................441 Chapter 20 Error Reporting Module (ERM) 20.1 Chip-specific ERM information........................... 443 20.1.1 Sources of memory error events........................443 20.2 Introduction...................................443 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 14 21.3.1 WDOG register descriptions.......................... 456 21.4 Functional description..............................463 21.4.1 Clock source..............................463 21.4.2 Watchdog refresh mechanism........................464 21.4.3 Configuring the Watchdog..........................466 21.4.4 Using interrupts to delay resets........................467 21.4.5 Backup reset..............................467 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 15 CRC result complement..........................482 Chapter 23 Reset and Boot 23.1 Introduction...................................483 23.2 Reset....................................483 23.2.1 Power-on reset (POR)............................ 484 23.2.2 System reset sources............................484 23.2.3 MCU Resets..............................488 23.2.4 Reset pin ................................488 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 16 Internal clocking requirements............................. 512 25.4.1 Clock divider values after reset........................516 25.4.2 HSRUN mode clocking..........................516 25.4.3 VLPR mode clocking.............................516 25.4.4 VLPR/VLPS mode entry..........................516 25.5 Clock Gating................................. 517 25.6 Module clocks................................517 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 17 26.3.15 Fast IRC Divide Register (SCG_FIRCDIV)....................555 26.3.16 Fast IRC Configuration Register (SCG_FIRCCFG)..................556 26.3.17 System PLL Control Status Register (SCG_SPLLCSR)................557 26.3.18 System PLL Divide Register (SCG_SPLLDIV)....................559 26.3.19 System PLL Configuration Register (SCG_SPLLCFG)................560 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 18 27.6.13 PCC CRC Register (PCC_CRC)........................586 27.6.14 PCC PDB0 Register (PCC_PDB0)........................ 587 27.6.15 PCC LPIT Register (PCC_LPIT)........................589 27.6.16 PCC FTM0 Register (PCC_FTM0)....................... 590 27.6.17 PCC FTM1 Register (PCC_FTM1)....................... 592 27.6.18 PCC FTM2 Register (PCC_FTM2)....................... 593 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 19 Chapter 28 Memories and Memory Interfaces 28.1 Introduction...................................629 28.2 Flash Memory Controller and flash memory modules....................629 28.3 SRAM configuration..............................629 28.3.1 SRAM sizes..............................630 28.3.2 SRAM accessibility............................630 28.3.3 SRAM arbitration and priority control......................632 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 20 Chip Configuration and Boot............................658 30.4 MSCM Memory Map/Register Definition........................659 30.4.1 CPU Configuration Memory Map and Registers...................659 30.4.2 MSCM register descriptions.......................... 659 Chapter 31 Flash Memory Controller (FMC) 31.1 Chip-specific FMC information............................691 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 21 Customize MCU operations via FTFC_FOPT register..................709 32.1.9 Simultaneous operations on PFLASH read partitions .................. 710 32.2 Introduction...................................710 32.2.1 Features................................711 32.2.2 Block diagram..............................713 32.2.3 Glossary................................. 713 32.3 External signal description............................716 32.4 Memory map and registers............................716 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 22 Overview................................ 819 33.1.2 Memory size requirement ..........................819 33.1.3 QuadSPI register reset values........................819 33.1.4 Use case................................820 33.1.5 Supported read modes............................ 820 33.1.6 External memory options..........................821 33.1.7 Recommended software configuration......................821 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 23 Functional Description..............................885 33.7.1 Serial Flash Access Schemes......................... 885 33.7.2 Normal Mode..............................885 33.7.3 HyperRAM Support............................904 33.8 Initialization/Application Information.......................... 905 33.8.1 Power Up and Reset............................905 33.8.2 Available Status/Flag Information......................... 905 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 24 Compute Operation (CPO)..........................933 34.4.5 Peripheral Doze..............................934 34.5 Power mode transitions..............................935 34.6 Shutdown sequencing for power modes........................936 34.7 Power mode restrictions on flash memory programming.....................936 34.8 Module operation in available power modes........................ 936 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 25 Features..................................961 36.4 Modes of Operation..............................962 36.4.1 Full Performance Mode (FPM)........................962 36.4.2 Low Power Mode (LPM)..........................962 36.5 Low Voltage Detect (LVD) System..........................962 36.5.1 Low Voltage Reset (LVR) Operation......................963 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 26 37.11 ADC low-power modes..............................988 37.12 ADC Trigger Concept – Use Case..........................988 37.13 ADC calibration scheme............................... 990 Chapter 38 Analog-to-Digital Converter (ADC) 38.1 Chip-specific ADC information............................993 38.2 Introduction...................................993 38.2.1 Features................................993 38.2.2 Block diagram..............................994 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 27 38.4.20 ADC Plus-Side General Calibration Value Register 0 (CLP0)..............1022 38.4.21 ADC Plus-Side General Calibration Value Register X (CLPX)..............1023 38.4.22 ADC Plus-Side General Calibration Value Register 9 (CLP9)..............1024 38.4.23 ADC General Calibration Offset Value Register S (CLPS_OFS)..............1025 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 28 Instantiation information..........................1047 39.1.2 CMP input connections..........................1047 39.1.3 CMP external references..........................1048 39.1.4 External window/sample input........................1048 39.1.5 CMP trigger mode............................1049 39.1.6 Programming recommendation........................1049 39.2 Introduction...................................1050 39.3 Features..................................1051 39.3.1 CMP features..............................1051 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 29 39.10 Interrupts..................................1078 39.11 DMA support................................1078 39.12 DAC functional description............................1079 39.12.1 Digital-to-analog converter block diagram....................1079 39.12.2 DAC resets..............................1079 39.12.3 DAC clocks..............................1080 39.12.4 DAC interrupts............................... 1080 39.13 Trigger mode.................................1080 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 30 40.3.11 Channel n Delay 4 register (PDBx_CHnDLY4)....................1107 40.3.12 Channel n Delay 5 register (PDBx_CHnDLY5)....................1107 40.3.13 Channel n Delay 6 register (PDBx_CHnDLY6)....................1108 40.3.14 Channel n Delay 7 register (PDBx_CHnDLY7)....................1109 40.3.15 Pulse-Out n Enable register (PDBx_POEN)....................1109 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 31 FTM BDM and debug halt mode........................1126 41.2 Introduction...................................1127 41.2.1 Features................................1127 41.2.2 Modes of operation............................1128 41.2.3 Block Diagram............................... 1129 41.3 FTM signal descriptions............................... 1131 41.4 Memory map and register definition..........................1131 41.4.1 Memory map..............................1131 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 32 41.5.18 Fault Control..............................1246 41.5.19 Polarity Control..............................1250 41.5.20 Initialization..............................1251 41.5.21 Features Priority............................. 1251 41.5.22 External Trigger............................. 1252 41.5.23 Initialization Trigger............................1253 41.5.24 Capture Test Mode............................1255 41.5.25 DMA................................1256 41.5.26 Dual Edge Capture Mode..........................1257 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 33 LPIT input triggers ............................1296 42.1.4 LPIT/ADC Trigger............................1296 42.2 Introduction...................................1297 42.2.1 Overview................................ 1297 42.2.2 Block Diagram............................... 1299 42.3 Modes of operation............................... 1300 42.4 Memory Map and Registers............................1301 42.4.1 LPIT register descriptions..........................1301 42.5 Functional description..............................1317 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 34 LPTMR clocking............................1343 43.5.3 LPTMR prescaler/glitch filter........................1344 43.5.4 LPTMR counter............................. 1345 43.5.5 LPTMR compare............................1346 43.5.6 LPTMR interrupt............................1346 43.5.7 LPTMR hardware trigger..........................1346 Chapter 44 Real Time Clock (RTC) 44.1 Chip-specific RTC information............................ 1349 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 35 Chip-specific LPSPI information..........................1367 45.1.1 Instantiation Information..........................1367 45.2 Introduction...................................1368 45.2.1 Features................................1370 45.2.2 Block Diagram............................... 1370 45.2.3 Modes of operation............................1371 45.2.4 Signal Descriptions............................1371 45.2.5 Wiring options..............................1372 45.3 Memory Map and Registers............................1374 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 36 46.4.2 Master Mode..............................1455 46.4.3 Slave Mode..............................1461 46.4.4 Interrupts and DMA Requests........................1463 46.4.5 Peripheral Triggers............................1465 Chapter 47 Low Power Universal Asynchronous Receiver/Transmitter (LPUART) 47.1 Chip-specific LPUART information..........................1467 47.1.1 Instantiation Information..........................1467 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 37 Overview................................ 1515 48.2.2 Features................................1516 48.2.3 Block Diagram............................... 1516 48.2.4 Modes of operation............................1517 48.2.5 FlexIO Signal Descriptions..........................1517 48.3 Memory Map and Registers............................1518 48.3.1 FLEXIO register descriptions........................1518 48.4 Functional description..............................1542 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 38 49.1.7 Supported baud rate ............................1565 49.1.8 Requirements for entering FlexCAN modes: Freeze, Disable, Stop............. 1565 49.2 Introduction...................................1567 49.2.1 Overview................................ 1568 49.2.2 FlexCAN module features..........................1568 49.2.3 Modes of operation............................1570 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 39 49.5.10 Clock domains and restrictions........................1701 49.5.11 Modes of operation details..........................1705 49.5.12 Interrupts................................ 1708 49.5.13 Bus interface..............................1710 49.6 Initialization/application information........................... 1711 49.6.1 FlexCAN initialization sequence........................1711 Chapter 50 Debug 50.1 Introduction...................................1713 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 40 Block diagram..............................1727 51.2.2 Features................................1728 51.2.3 Modes of operation............................1728 51.3 External signal description............................1730 51.3.1 Test clock input (TCK)..........................1730 51.3.2 Test data input (TDI)............................1730 51.3.3 Test data output (TDO)..........................1730 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 41 Boundary scan register...........................1732 51.5 Functional description..............................1733 51.5.1 JTAGC reset configuration..........................1733 51.5.2 IEEE 1149.1-2001 (JTAG) TAP........................1733 51.5.3 TAP controller state machine.........................1733 51.5.4 JTAGC block instructions..........................1736 51.5.5 Boundary scan..............................1739 51.6 Initialization/application information........................... 1739 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 42 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 43: About This Manual
• Examples of these groupings are clocking, timers, and communication interfaces. • Each grouping includes chapters that provide a technical description of individual modules. 1.3 Module descriptions Each module chapter has two main parts: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 44: Example: Chip-Specific Information That Clarifies Content In The Same Chapter
The example below shows chip-specific information that clarifies general module information presented later in the chapter. In this case, the chip-specific register reset values supercede the reset values that appear in the register diagram. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 45: Example: Chip-Specific Information That Refers To A Different Chapter
1.3.2 Example: chip-specific information that refers to a different chapter The chip-specific information below refers to another chapter's chip-specific information. In this case, read both sets of chip-specific information before reading further in the chapter. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 46: Register Descriptions
• The page number on which each register is described • Register figures • Field-description tables • Associated text The register figures show the field structure using the conventions in the following figure. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 47: Conventions
WARNING Warning notices inform readers about actions that could result in unwanted consequences, especially those that may cause bodily injury. 1.5.2 Numbering systems The following suffixes identify different numbering systems: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 48: Typographic Notation
• An active-high signal is deasserted when low (0). • An active-low signal is deasserted when high (1). In some cases, deasserted signals are described as negated. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 49 • Consider undefined locations in memory to be reserved. Write 1 to clear: Refers to a register bitfield that must be written as 1 to be "cleared." MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 50 Conventions MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 51: Introduction
1. CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The device will need to switch to RUN mode (80 Mhz) to execute CSEc (Security) or EEPROM writes/erase MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 52: Feature Summary
2. This refers to region addressable by Arm CM4 Code bus and is used to cache code as well as data in this region. See WCT101x_memory_map.xlsx for more details on cacheability of different regions. 3. HSRUN mode (112 MHz) operation is not valid at 125 °C MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 53 48 MHz internal IRC (FIRC) with 1% max deviation across full temperature 8 MHz internal IRC (SIRC) with 3% maximum deviation across full temperature Phase-locked loop (PLL) Up to 320 MHz VCO Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 54 Low Power Serial peripheral interface (LPSPI0–LPSPI2) DMA support, 4 word FIFO support on all LPSPIs Low Power Inter-Integrated Circuit (LPI2C0-LPI2C1) Up to 2 LPI2C Standard SMBUS compatible I Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 55: Block Diagram
Arm Core MPU, which would concurrently monitor only core-initiated memory accesses. In this document, the term MPU refers to NXP’s system MPU. 2.4 Block diagram The following figure shows block diagram of the WCT101xS product series. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 56: Feature Comparison
All devices which share a common package are pin-to-pin compatible. NOTE Availability of peripherals depends on the pin availability in a particular package. For more information see IO Signal MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 57 512 KB block can be used as Data flash or Program flash. See chapter FTFC for details. 4 Only for Boundary Scan Register 5 See Dimensions for package drawing Figure 2-2. MWCT101xS product series comparison MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 58: Applications
• Cyclic Redundancy Check (CRC) Clocking • Multiple clock generation options available from internally- and externally- generated clocks • System oscillator to provide clock source for the MCU Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 59: Arm Cortex-M4F Core Modules
Floating point unit (FPU) A single-precision floating point unit (FPU) that is compliant to the IEEE Standard for Floating-Point Arithmetic (IEEE 754). Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 60: System Modules
System Memory protection unit (MPU) The system MPU provides memory protection and task isolation. It concurrently monitors all bus master transactions for the slave connections. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 61: Memories And Memory Interfaces
It supports SDR and HyperRAM modes up to 4 and 8 bidirectional data lines respectively. Flash memory controller Manages the interface between the device and the on-chip flash memory. SRAM Internal system RAM. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 62: Power Management
Module Description 12-bit analog-to-digital converters (ADC) 12-bit successive-approximation ADC Analog comparators (CMP) Compares two analog input voltages across the full range of the supply voltage. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 63: Timer Modules
• Configurable glitch filter or prescaler with 16-bit counter • 16-bit time or pulse counter with compare • Interrupt generated on Timer Compare • Hardware trigger generated on Timer Compare Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 64: Communication Interfaces
Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC block is communicated in serial format. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 65: Memory Map
The various flash memories and the flash memory registers are located at different base addresses as shown in the following figure. The base address for each is specified in the MWCT101xS_memory_map.xlsx file attached to this document. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 66: Peripheral Bridge (Aips-Lite) Memory Map
AIPS-Lite slots. Access to any address within an unimplemented or disabled peripheral bridge slot results in a transfer error termination. NOTE While trying to access memory map region of unavailable feature (See SIM_SDID[FEATURES]) with corresponding MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 67: Read-After-Write Sequence And Required Serialization Of Memory Operations
Processor Technical Reference Manual, Revision r0p1, at http:// arm.com ). However, disabling buffered writes is likely to degrade system performance much more than simply performing the required memory serialization for the situations that truly require it. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 68: Private Peripheral Bus (Ppb) Memory Map
A 32-bit write in the alias region has the same effect as a read- modify-write operation on the targeted bit in the bit-band region. Bit 0 of the value written to the alias region determines what value is written to the target bit: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 69 Do not use bit banding for w1c status bits. CAUTION The WCT product series and the software drivers support bit- banding, but Arm no longer promotes its usage. Therefore, we recommend that bit-banding should not be used. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 70 Aliased bit-band regions MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 71: Signal Multiplexing And Pin Assignment
Reference Manual. 4.2 Functional description The signal multiplexing architectural implementation is as shown in the following figure. GPIO Pad controls Functional Signal Padring Modules/ Multiplexing Peripherals Unit Figure 4-1. Signal Multiplexing MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 72: Pad Description
0: Enable internal pulldown resistor if pue is set 1: Enable internal pullup resistor if pue is set Enable input receiver Data coming out of the pad into the core MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 73: Default Pad State
Table 4-3. Default pad configurations Default Default pad function state PTA4 JTAG_TMS Weak pull-up enabled PTA5 RESET_b Weak pull-up enabled PTC4 JTAG_TCK Weak pull-down enabled PTC5 JTAG_TDI Weak pull-up enabled Others Disabled High impedance 0 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 74: Signal Multiplexing Sheet
• CR(Control Register): This field specifies the name of PCR corresponding to the Port field. On this device there are five PORT instances, namely, PTA, PTB, PTC, PTD and PTE. Each pad has a corresponding Control Register, referred to as PCR_PTXn MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 75 • The next columns specify the pin number in the supported packages for the device. • PCR: This field specifies the default PCR value for corresponding pad. Refer PORT_PCR for description of PCR fields. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 76: Input Muxing Table
• Source Signal: This field mentions the pad name. A ‘disable low’/’disable high’ specifies the signal behavior when none of the pads are driving the input path. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 77: Pinout Diagrams
Chapter 4 Signal Multiplexing and Pin Assignment 4.6 Pinout diagrams See IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual for pinout diagrams corresponding to available packages. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 78 Pinout diagrams MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 79: Security Overview
FSEC[SEC] field. The MCU, in turn, confirms the security request and limits access to flash memory resources. During reset, the flash memory module initializes the FSEC register using data read from the security byte of the flash memory configuration field. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 80 • If the debugger has switched to SWD mode, the FTFC_FCSESTAT[EDB] bit can be reset only through POR. • If the debugger remains in JTAG mode, the FTFC_FCSESTAT[EDB] bit is reset on pin_reset if correct debugger disconnection takes place or on POR. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 81: Cryptographic Services Engine (Csec) Security Features
Security use case examples 5.3.1 Secure boot: check bootloader for integrity and authenticity The following diagram illustrates a use case for detecting and preventing bootloader modification. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 82: Chain Of Trust: Check Flash Memory For Integrity And Authenticity
• Part-by-part checking of flash memory ensures each part's integrity and authenticity before executing it. Critical parts of flash memory (for example, MCU configuration/IRQ table) are checked and then executed as soon as possible. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 83: Secure Communication
This use case demonstrates how to prevent illegal messages sent by ECUs. • Random number generation and checking protect against replay attacks. • Encryption protects against eavesdropping. • Random number generation/checking and encryption ensure data integrity and authenticity. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 84: Component Protection
Figure 5-3. Secure communication 5.3.4 Component protection The replacement or modification of ECU <n> will change its unique ID and/or keys. This use case shows how both changes are detected. Figure 5-4. Component protection MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 85: Message-Authentication Example
3. Transfer data to CSEc memory (maximum 12 CAN messages of 8 bytes + 16-byte CMAC) 4. Trigger CSEc CMAC calculation/verification 5. CSEc triggers interrupt to core 6. Core reads processed message data MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 86: Steps Required Before Failure Analysis
Before returning a device to NXP for failure analysis, the user must run the CMD_DBG_CHAL CMD_DBG_AUTH commands and ensure that all user keys are deleted. This is a mandatory step to enable failure analysis at NXP. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 87: Security Programming Flow Example (Secure Boot)
4. CMD_BOOT_DEFINE to select the flavor of boot and size of data to validate in Pflash Then optionally reset the part to "auto calculate" and program the BOOT_MAC or the user loads the BOOT_MAC by external calculation. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 88 Security programming flow example (Secure Boot) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 89: Safety Overview
FMEDA, including source of failure rates, failure modes, and assumptions during the analysis The WCT101xS series is a SafeAssure™ solution. For more information regarding functional safety at NXP, visit http://www.nxp.com/safeassure. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 90: Wct101Xs Safety Concept
ASIL-B safety integrity level. In general, safety integrity is achieved by using and applying WCT101xS safety features as described in the Safety Manual. The following diagram provides an overview of integrated WCT101xS architecture and safety features. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 91: Cortex-M4 Structural Core Self Test (Scst)
In this document, the term MPU refers to NXP’s system MPU Feature Comparison. 2: See Memories and Memory Interfaces chapter in MWCT101x Series Reference Manual: On-chip SRAM sizes table for Device specific sizes Figure 6-2. WCT101xS safety block diagram MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 92: Ecc On Ram And Flash Memory
MCU system states during supply voltage variations. • Power-on reset (POR) • Low-voltage detection (LVD) References: • Functional description: in this Reference Manual, see Power Management • Power supply monitoring in safety concept: see Safety Manual chapter MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 93: Clock Monitoring
• manage the concurrent execution of software with different (lower) ASIL A hierarchical memory protection scheme, which includes the following, protects against interference: • System Memory Protection Unit (MPU) • Peripheral Bridge (AIPS-Lite) • Register protection MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 94 M4 core version in this family does not integrate the Arm Core MPU, which would concurrently monitor only core- initiated memory accesses. In this document, the term MPU refers to NXP’s system MPU. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 95: Crc
• UART modules: support UART and LIN communication References: • Functional description: in this Reference Manual, see SIM, LPSPI, LPI2C, FlexIO, LPUART • Diversity of system resources in safety concept: see Safety Manual MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 96 WCT101xS safety concept MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 97: Core Overview
Power management — Power management System/instruction/data Crossbar switch Crossbar switch bus module Debug IEEE 1149.1 JTAG Debug Serial Wire Debug (SWD) Arm Real-Time Trace Interface Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 98: Buses, Interconnects, And Interfaces
SysTick Calibration Value Register is always zero. • The NOREF bit in SysTick Calibration Value Register is always set, implying that CORE_CLK is the only available source of reference timing. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 99: Debug Facilities
WT space to NC. In order to change the state upwards a system reset is required. NOTE LMEM for the cache reset states. 7.1.5 Core privilege levels The Arm documentation uses different terms than this document to distinguish between privilege levels. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 100: Nested Vectored Interrupt Controller (Nvic) Configuration
This device supports 16 priority levels for interrupts. Therefore, in the NVIC each source in the IPR registers contains 4 bits. For example, the IPR0 diagram is shown below. IRQ3 IRQ2 IRQ1 IRQ0 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 101: Non-Maskable Interrupt
• NVICIPR14 bitfield starting location = 8 × (IRQ mod 4) + 4 = 20 Since the NVICIPR bitfields are 4-bit wide (16 priority levels), the NVICIPR14 bitfield range is 20-23 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 102: Asynchronous Wake-Up Interrupt Controller (Awic) Configuration
— AWIC wake-up sources 7.3.1 Wake-up sources Table 7-8. AWIC stop and VLPS wake-up sources Wake-up source Description Available system resets RESET pin, WDOG, JTAG Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 103: Fpu Configuration
Figure 7-4. FPU configuration Table 7-9. Reference links to related information Topic Related module Reference Full description Arm Cortex-M4 Technical Reference Manual - Floating-Point Unit Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 104: Jtag Controller Configuration
Table 7-10. Reference links to related information Topic Related module Reference Full description JTAGC JTAGC Signal multiplexing Port control See IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual for details. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 105: Miscellaneous Control Module (Mcm)
The Miscellaneous Control Module (MCM) provides miscellaneous control functions. NOTE Cache write buffer is not supported on WCT101xS. 8.2.1 Features The MCM includes the following feature: • Program-visible information on the platform configuration and revision MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 106: Memory Map/Register Descriptions
LMEM Fault Address Register (MCM_LMFAR) 0000_0000h 8.3.11/126 E008_0494 LMEM Fault Attribute Register (MCM_LMFATR) 0000_0000h 8.3.12/127 E008_04A0 LMEM Fault Data High Register (MCM_LMFDHR) 0000_0000h 8.3.13/128 E008_04A4 LMEM Fault Data Low Register (MCM_LMFDLR) 0000_0000h 8.3.14/128 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 107: Crossbar Switch (Axbs) Slave Configuration (Mcm_Plasc)
This read-only field is reserved and always has the value 0. Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 108 Memory map/register descriptions MCM_PLAMC field descriptions (continued) Field Description A bus master connection to AXBS input port n is absent A bus master connection to AXBS input port n is present MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 109: Core Platform Control Register (Mcm_Cpcr)
8.3.3 Core Platform Control Register (MCM_CPCR) CPCR defines the arbitration and protection schemes for the two system RAM arrays. Address: E008_0000h base + Ch offset = E008_000Ch SRAMLAP SRAMUAP Reserved Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 110 Fixed priority. Processor has highest, backdoor has lowest Fixed priority. Backdoor has highest, processor has lowest This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 111 This field indicates if AXBS is in a halted state. AXBS is not currently halted AXBS is currently halted AXBS Halt Request AXBS_HLT_REQ This field indicates if AXBS has received a halt request. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 112: Interrupt Status And Control Register (Mcm_Iscr)
Bits 15-8 are read-only indicator flags based on the processor’s FPSCR. Attempted writes to these fields are ignored. After the flags are set, they remain asserted until software clears the corresponding FPSCR field. Address: E008_0000h base + 10h offset = E008_0010h Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 113 This read-only field is reserved and always has the value 0. This field is reserved. Reserved 19–18 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 114 FPU. After this field is set, it remains set until software clears FPSCR[IOC]. No interrupt Interrupt occurred 7–5 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 115: Process Id Register (Mcm_Pid)
31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. M0_PID and M1_PID for MPU Drives the M0_PID and M1_PID values in the MPU. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 116: Compute Operation Control Register (Mcm_Cpo)
Compute operation entry has completed or compute operation exit has not completed. Compute Operation Request CPOREQ This field is auto-cleared by vector fetching if CPOWOI = 1. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 117: Local Memory Descriptor Register (Mcm_Lmdrn)
Privileged writes from other bus masters are ignored. Attempted user mode accesses or any access with a size other than 32 bits are terminated with an error. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 118 Memory map/register descriptions Address: E008_0000h base + 400h offset + (4d × i), where i=0d to 1d LMSZ Reset Reserved Reserved Reset * Notes: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 119 No Cache 0010 2-Way Set Associative 0100 4-Way Set Associative 19–17 LMEM Data Path Width. This field defines the width of the local memory. 000-001 Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 120: Local Memory Descriptor Register2 (Mcm_Lmdr2)
This section of the programming model is an array of 32-bit generic on-chip memory descriptor registers that provide static information on the attached memories as well as configurable controls (where appropriate). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 121 Privileged writes from other bus masters are ignored. Attempted user mode accesses or any access with a size other than 32 bits are terminated with an error. Address: E008_0000h base + 408h offset = E008_0408h LMSZ Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 122 This field provides an encoded value of the local memory size; a LMSZ = 0 indicates the memory is not present. 0100 4 KB LMEMn 23–20 Level 1 Cache Ways 0000 No Cache 0010 2-Way Set Associative 0100 4-Way Set Associative Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 123 This field is used for cache parity control functions. • CF1[3]-PCPFE = PC Parity Fault Enable • CF1[2]-Reserved • CF1[1]-PCPME = PC Parity Miss Enable • CF1[0]-Reserved Reserved This field is reserved. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 124: Lmem Parity And Ecc Control Register (Mcm_Lmpecr)
This field is reserved. Reserved This read-only field is reserved and always has the value 0. Enable RAM ECC Noncorrectable Reporting ERNCR Reporting disabled Reporting enabled 8.3.10 LMEM Parity and ECC Interrupt Register (MCM_LMPEIR) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 125 • PEIR[8] - 1-bit Error detected on SRAM_L ENCn = ECC Noncorrectable Error n • PEIR[7:2] - Reserved • PEIR[1] - Noncorrectable Error detected on SRAM_U • PEIR[0] - Noncorrectable Error detected on SRAM_L MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 126: Lmem Fault Address Register (Mcm_Lmfar)
Memory map/register descriptions 8.3.11 LMEM Fault Address Register (MCM_LMFAR) Address: E008_0000h base + 490h offset = E008_0490h EFADD Reset MCM_LMFAR field descriptions Field Description EFADD ECC Fault Address MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 127: Lmem Fault Attribute Register (Mcm_Lmfatr)
This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–8 Parity/ECC Fault Master Number PEFMST Parity/ECC Fault Write PEFW Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 128: Lmem Fault Data High Register (Mcm_Lmfdhr)
PEFDH Reset MCM_LMFDHR field descriptions Field Description PEFDH Parity or ECC Fault Data High 8.3.14 LMEM Fault Data Low Register (MCM_LMFDLR) Address: E008_0000h base + 4A4h offset = E008_04A4h PEFDL Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 129: Functional Description
ISCR[31:16] and ISCR[15:0]. 2. Search the result for asserted bits which indicate the exact interrupt sources. NOTE ECC and Parity interrupts are determined by LMPECR (interrupt enable) and LMPEIR (interrupt source). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 130 Functional description MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 131: System Integration Module (Sim)
• Flash memory and system RAM size configuration • FlexTimer clock channel and configuration • ADC trigger selection • LPO clock source selection • Flash memory configuration • System device identification (ID) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 132: Memory Map And Register Definition
Platform Clock Gating Control Register (PLATCGC) 0000_001Fh Flash Configuration Register 1 (FCFG1) description. Unique Identification Register High (UIDH) description. Unique Identification Register Mid-High (UIDMH) description. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 133 CHIPCTL 9.3.1.2.2 Function SIM_CHIPCTL contains the controls for selecting ADC COCO trigger, trace clock, clock out source, PDB back-to-back mode, and ADC interleave channel. NOTE Bits 31:16 are reset on POR. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 134 18-16 ADC_SUPPLY ADC_SUPPLY Internal supplies monitored on ADC0 internal channel 0 (configured by selecting ADC0_SC1n[ADCH] as 010101b) 000b - 5 V input VDD supply (VDD) Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 135 111b - Divide by 8 CLKOUT Select NOTE: The below sequence should be followed while CLKOUT configuration: CLKOUTSEL 1. Configure SIM_CHIPCTL[CLKOUTSEL] 2. Configure SIM_CHIPCTL[CLKOUTDIV] 3. Enable SIM_CHIPCTL[CLKOUTEN] Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 136 - PTB13 to ADC1_SE8 and ADC0_SE8 xx1xb - PTB1 to ADC0_SE5 and ADC1_SE15 xxx1b - PTB0 to ADC0_SE4 and ADC1_SE14 9.3.1.3 FTM Option Register 0 (FTMOPT0) 9.3.1.3.1 Offset Register Offset FTMOPT0 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 137 01b - FTM1 external clock driven by TCLK1 pin. 10b - FTM1 external clock driven by TCLK2 pin. 11b - No clock input 25-24 FTM0 External Clock Pin Select Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 138 NOTE: The pin source of the fault must be configured for FTM3 fault function through the appropriate PORT_PCRn field when the fault comes from an external pin. TRGMUX_FTM3 SELx corresponds to the FTM3 Fault x input. 000b - FTM3_FLTx pin Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 139 PORT_PCRn field when the fault comes from an external pin. TRGMUX_FTM0 SELx corresponds to the FTM0 Fault x input. 000b - FTM0_FLTx pin 001b - TRGMUX_FTM0 out 9.3.1.4 LPO Clock Select Register (LPOCLKS) 9.3.1.4.1 Offset Register Offset LPOCLKS MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 140 0b - Disable 32 kHz LPO_CLK output LPO32KCLKEN 1b - Enable 32 kHz LPO_CLK output 1 kHz LPO_CLK enable 0b - Disable 1 kHz LPO_CLK output LPO1KCLKEN 1b - Enable 1 kHz LPO_CLK output MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 141 11b - Reserved 11-9 ADC1 software pretrigger sources 000b - Software pretrigger disabled ADC1SWPRET 001b - Reserved (do not use) 010b - Reserved (do not use) Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 142 ADC channels are OR'ed together to support up to 16 pretriggers. 0b - PDB output 1b - TRGMUX output 9.3.1.6 FTM Option Register 1 (FTMOPT1) 9.3.1.6.1 Offset Register Offset FTMOPT1 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 143 FTM4SYNCBIT This is used as trigger source for FTM4. See section FTM Hardware Triggers and Synchronization for details on FTM hardware triggering. 10-9 Reserved — Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 144 This is used as trigger source for FTM0. See section FTM Hardware Triggers and Synchronization for details on FTM hardware triggering. 9.3.1.7 Miscellaneous control register 0 (MISCTRL0) 9.3.1.7.1 Offset Register Offset MISCTRL0 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 145 1b - The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]. FTM6 OBE CTRL bit Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 146 1b - The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 147 1b - STOP1 entry successful Reserved — 9.3.1.8 System Device Identification Register (SDID) 9.3.1.8.1 Offset Register Offset SDID 9.3.1.8.2 Function NOTE This register's reset value is loaded during system reset from flash memory IFR. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 148 Specifies the silicon implementation number for the chip. The value is 0 (for WCT1015S and WCT1016S) and 1 (for WCT1014S). 11-8 Package PACKAGE Specifies the available package options for the chip. 0000b - Reserved 0001b - Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 149 • Bit 4: QuadSPI • Bit 3: Reserved • Bit 2: ISELED • Bit 1: Reserved • Bit 0: Reserved 9.3.1.9 Platform Clock Gating Control Register (PLATCGC) 9.3.1.9.1 Offset Register Offset PLATCGC MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 150 Controls the clock gating to the MPU module. 0b - Clock disabled 1b - Clock enabled MSCM Clock Gating Control CGCMSCM Controls the clock gating to the MSCM. 0b - Clock disabled 1b - Clock enabled MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 151 Attempted writes to this register may result in unpredictable behavior. 9.3.1.10.3 Diagram Bits Reserved Reserved EEERAMSIZE Reset Bits Reset 9.3.1.10.4 Fields Field Function 31-28 Reserved — 27-24 Reserved — 23-20 Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 152 9.3.1.11.2 Function NOTE • UID127_96, UID95_64, UID63_32, and UID31_0 together represents 128-bit unique identification number for this device. • This register's reset value is loaded during system reset from flash memory IFR. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 153 Unique identification for the chip. 9.3.1.12 Unique Identification Register Mid-High (UIDMH) 9.3.1.12.1 Offset Register Offset UIDMH 9.3.1.12.2 Function NOTE This register's reset value is loaded during system reset from flash memory IFR. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 154 Unique identification for the chip. 9.3.1.13 Unique Identification Register Mid Low (UIDML) 9.3.1.13.1 Offset Register Offset UIDML 9.3.1.13.2 Function NOTE This register's reset value is loaded during system reset from flash memory IFR. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 155 Unique identification for the chip. 9.3.1.14 Unique Identification Register Low (UIDL) 9.3.1.14.1 Offset Register Offset UIDL 9.3.1.14.2 Function NOTE This register's reset value is loaded during system reset from flash memory IFR. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 156 Reset Bits UID31_0 Reset 9.3.1.14.4 Fields Field Function 31-0 Unique Identification UID31_0 Unique identification for the chip. 9.3.1.15 System Clock Divider Register 4 (CLKDIV4) 9.3.1.15.1 Offset Register Offset CLKDIV4 9.3.1.15.2 Function MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 157 This field sets the divide value for the fractional clock divider used as a source for trace clock. The source clock for the trace clock is set by the SIM_CHIPCTL[TRACECLK_SEL]. Divider output clock = Divider input clock * [(TRACEFRAC+1)/(TRACEDIV+1)]. NOTE: TRACEFRAC should be ≤ TRACEDIV MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 158 Reset Bits Reset 9.3.1.16.3 Fields Field Function 31-1 Reserved — Software trigger to TRGMUX. Writing to this bit generates software trigger to peripherals through TRGMUX (Refer to Figure: Trigger interconnectivity). SW_TRG MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 159: Port Control And Interrupts (Port)
Any pad configuration done in RUN/VLPR mode is retained in low power modes(STOP1,STOP2/VLPS). Wait mode is not supported on this device. Module operation in available power modes for details on available power modes. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 160: Number Of Pcrs
2. Initialize peripheral clock in the Peripheral Clock Controller register(PCC) and peripheral specific clocking configurations. 3. Configure the peripheral 4. Initialize port clock for the peripheral pins in the Peripheral Clock Controller register (PCC_PORTx). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 161: Digital Input Filter Configuration Sequence
PORTx_DFER and reconfigured on wakeup, if required. If filtering is not required in STOP/VLPS modes and is required wakeup onwards without reconfiguring PORTx_DFER (with bus clock as filter clock), it should be ensured that: cycles_tISR >> (PORTx_DFWR+3)*(SCG_xCCR[DIVBUS]+1) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 162: Reset Pin Configuration
• Pin interrupt is functional in all digital pin muxing modes • Digital input filter • Digital input filter for each pin, usable by any digital peripheral muxed onto the • Individual enable or bypass control field per pin MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 163: Modes Of Operation
In Stop mode, the digital input filters are bypassed unless they are configured to run from the LPO clock source. 10.3.2.4 Debug mode In Debug mode, PORT operates normally. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 164: External Signal Description
Pin Control Register n (PORTA_PCR0) See section 10.6.1/172 4004_9004 Pin Control Register n (PORTA_PCR1) See section 10.6.1/172 4004_9008 Pin Control Register n (PORTA_PCR2) See section 10.6.1/172 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 165 0) 4004_9084 Global Pin Control High Register (PORTA_GPCHR) (always 0000_0000h 10.6.3/175 reads 0) 4004_9088 Global Interrupt Control Low Register (PORTA_GICLR) (always 0000_0000h 10.6.4/176 reads 0) Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 166 Pin Control Register n (PORTB_PCR28) See section 10.6.1/172 4004_A074 Pin Control Register n (PORTB_PCR29) See section 10.6.1/172 4004_A078 Pin Control Register n (PORTB_PCR30) See section 10.6.1/172 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 167 Pin Control Register n (PORTC_PCR20) See section 10.6.1/172 4004_B054 Pin Control Register n (PORTC_PCR21) See section 10.6.1/172 4004_B058 Pin Control Register n (PORTC_PCR22) See section 10.6.1/172 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 168 4004_C030 Pin Control Register n (PORTD_PCR12) See section 10.6.1/172 4004_C034 Pin Control Register n (PORTD_PCR13) See section 10.6.1/172 4004_C038 Pin Control Register n (PORTD_PCR14) See section 10.6.1/172 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 169 4004_D010 Pin Control Register n (PORTE_PCR4) See section 10.6.1/172 4004_D014 Pin Control Register n (PORTE_PCR5) See section 10.6.1/172 4004_D018 Pin Control Register n (PORTE_PCR6) See section 10.6.1/172 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 170 0) 4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 0000_0000h 10.6.6/177 4004_D0C0 Digital Filter Enable Register (PORTE_DFER) 0000_0000h 10.6.7/177 4004_D0C4 Digital Filter Clock Register (PORTE_DFCR) 0000_0000h 10.6.8/178 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 171 Chapter 10 Port Control and Interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_D0C8 Digital Filter Width Register (PORTE_DFWR) 0000_0000h 10.6.9/178 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 172: Pin Control Register N (Portx_Pcrn)
PE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. • PS field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 173 The corresponding pin is configured in the following pin muxing slot as follows: Pin disabled (Alternative 0) (analog). Alternative 1 (GPIO). Alternative 2 (chip-specific). Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 174 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 175: Global Pin Control Low Register (Portx_Gpclr)
Corresponding Pin Control Register is updated with the value in GPWD. GPWD Global Pin Write Data Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 176: Global Interrupt Control Low Register (Portx_Giclr)
Selects which Pin Control Registers (31 through 16) bits [31:16] update with the value in GIWD. Corresponding Pin Control Register is not updated with the value in GPWD. Corresponding Pin Control Register is updated with the value in GPWD. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 177: Interrupt Status Flag Register (Portx_Isfr)
The digital filter configuration is valid in all digital pin muxing modes. The output of each digital filter is reset to zero at system reset and whenever the digital filter is disabled. Each bit in the field enables the digital filter of the same number as the field. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 178: Digital Filter Clock Register (Portx_Dfcr)
Digital filters are clocked by the LPO clock. 10.6.9 Digital Filter Width Register (PORTx_DFWR) The digital filter configuration is valid in all digital pin muxing modes. Address: Base address + C8h offset FILT Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 179: Functional Description
When locked, writes to the lower half of that pin control register are ignored, although a bus error is not generated on an attempted write to a locked register. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 180: Global Pin Control
However, the pin control functions cannot be configured using the global interrupt control registers. The global interrupt control registers are write-only registers and always read as 0. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 181: External Interrupts
Low-Power mode. 10.7.5 Digital filter The digital filter capabilities of the PORT module are available in all digital Pin Muxing modes if the PORT module is enabled. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 182 The maximum latency through a digital filter equals three filter clock cycles plus the filter width configuration register. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 183: General-Purpose Input/Output (Gpio)
Base + 80h Port C Base + C0h Port D Base + 100h Port E NOTE In WCT101xS, GPIO can only be accessed by the core through the cross bar interface at 0x400F_F000 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 184: Gpio Register Reset Values
NOTE The GPIO module is clocked by system clock. 11.2.2 Modes of operation The following table depicts different modes of operation and the behavior of the GPIO module in these modes. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 185: Gpio Signal Descriptions
Deassertion: When output, this signal occurs on the rising-edge of the system clock. For input, it may occur at any time and input may be asserted asynchronously to the system clock. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 186: Memory Map And Register Definition
Port Set Output Register (PSOR) WORZ 0000_0000h Port Clear Output Register (PCOR) WORZ 0000_0000h Port Toggle Output Register (PTOR) WORZ 0000_0000h Port Data Input Register (PDIR) 0000_0000h Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 187 Do not modify pin configuration registers associated with pins not available in your selected package. All unbonded pins not available in your package will default to DISABLE state for lowest power consumption. 11.3.1.2.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 188 Writing to this register updates the contents of the corresponding bit in the PDOR as follows: 0b - Corresponding bit in PDORn does not change. 1b - Corresponding bit in PDORn is set to logic 1. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 189 Writing to this register updates the contents of the corresponding bit in the Port Data Output Register (PDOR) as follows: 0b - Corresponding bit in PDORn does not change. 1b - Corresponding bit in PDORn is cleared to logic 0. 11.3.1.5 Port Toggle Output Register (PTOR) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 190 0b - Corresponding bit in PDORn does not change. 1b - Corresponding bit in PDORn is set to the inverse of its existing logic state. 11.3.1.6 Port Data Input Register (PDIR) 11.3.1.6.1 Offset Register Offset PDIR MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 191 0b - Pin logic level is logic 0, or is not configured for use by digital function. 1b - Pin logic level is logic 1. 11.3.1.7 Port Data Direction Register (PDDR) 11.3.1.7.1 Offset Register Offset PDDR MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 192 1b - Pin is configured as general-purpose output, for the GPIO function. 11.3.1.8 Port Input Disable Register (PIDR) 11.3.1.8.1 Offset Register Offset PIDR 11.3.1.8.2 Function This register disables each general-purpose pin from acting as an input. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 193: Functional Description
The logic state of each pin can be controlled via the port data output registers and port data direction registers, provided the pin is configured for the GPIO function. The following table depicts the conditions for a pin to be configured as input/output. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 194 The corresponding Port Control and Interrupt module does not need to be enabled to update the state of the port data direction registers and port data output registers including the set/clear/toggle registers. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 195: Crossbar Switch Lite (Axbs-Lite)
For configuring the bit field MCM_CPCR[CBRR], see the note present in the CBRR 12.1.2 Crossbar Switch slave assignments The following table identifies the slaves connected to the Crossbar Switch and whether the system MPU protects them. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 196: Introduction
• Up to single-clock 32-bit transfer • Programmable configuration for fixed-priority or round-robin slave port arbitration (see the chip-specific information). 12.3 Functional Description Information about general operation and arbitration can be found here. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 197: General Operation
• Round-robin The selection of the global slave port arbitration algorithm is described in the crossbar switch chip-specific information. 12.3.2.1 Arbitration during undefined length bursts Undefined length bursts can be interrupted. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 198 The requesting master's priority level is lower than the current At the conclusion of one of the following cycles: master. • An IDLE cycle • A non-IDLE cycle to a location other than the current slave port MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 199: Initialization/Application Information
The round-robin arbitration mode generally provides a more fair allocation of the available slave-port bandwidth (compared to fixed priority) as the fixed master priority does not affect the master selection. 12.4 Initialization/application information No initialization is required for the crossbar switch. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 200 Initialization/application information MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 201: Memory Protection Unit (Mpu)
MPU slave port 1 SRAM backdoor Code Bus MPU slave port 2 SRAM_L frontdoor System Bus MPU slave port 3 SRAM_U frontdoor Crossbar slave port 3 MPU Slave port 4 QuadSPI MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 202: Current Pid
Region descriptors Slave ports CESR reset value WCT1014S 0081_4001h WCT1015S 0081_4001h WCT1016S 0081_5201h 13.2 Introduction The memory protection unit (MPU) provides hardware access control for all memory references generated in the device. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 203: Overview
For details of the access evaluation macro, see Access evaluation macro. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 204: Features
• Error registers, per slave port, capture the last faulting address, attributes, and other information • Global MPU enable/disable control bit 13.4 MPU register descriptions The programming model is partitioned into three groups: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 205: Mpu Memory Map
0000_0000h 41Ch Region Descriptor 1, Word 3 (RGD1_WORD3) 0000_0000h 420h Region Descriptor 2, Word 0 (RGD2_WORD0) 0000_0000h 424h Region Descriptor 2, Word 1 (RGD2_WORD1) 0000_001Fh Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 206 0000_0000h 4BCh Region Descriptor 11, Word 3 (RGD11_WORD3) 0000_0000h 4C0h Region Descriptor 12, Word 0 (RGD12_WORD0) 0000_0000h 4C4h Region Descriptor 12, Word 1 (RGD12_WORD1) 0000_001Fh Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 207: Control/Error Status Register (Cesr)
Region Descriptor Alternate Access Control 13 (RGDAAC13) 0000_0000h 838h Region Descriptor Alternate Access Control 14 (RGDAAC14) 0000_0000h 83Ch Region Descriptor Alternate Access Control 15 (RGDAAC15) 0000_0000h 13.4.2 Control/Error Status Register (CESR) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 208 0b - No error has occurred for slave port 1. 1b - An error has occurred for slave port 1. Slave Port 2 Error SPERR2 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 209 0001b - 12 region descriptors 0010b - 16 region descriptors Reserved — Valid Global enable/disable for the MPU. 0b - MPU is disabled. All accesses from all bus masters are allowed. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 210: Error Address Register, Slave Port N (Ear0 - Ear4)
CESR[SPERRn], as the error registers are always loaded upon the occurrence of each protection violation. 13.4.3.3 Diagram Bits EADDR Reset Bits EADDR Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 211: Error Detail Register, Slave Port N (Edr0 - Edr4)
This register and the corresponding EARn register contain the most recent access error; there are no hardware interlocks with CESR[SPERRn] as the error registers are always loaded upon the occurrence of each protection violation. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 212 001b - User mode, data access 010b - Supervisor mode, instruction access 011b - Supervisor mode, data access Error Read/Write Indicates the access type of the faulting reference. 0b - Read 1b - Write MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 213: Region Descriptor N, Word 0 (Rgd0_Word0 - Rgd15_Word0)
Bits SRTADDR Reset Bits SRTADDR Reset 13.4.5.4 Fields Field Function 31-5 Start Address SRTADDR Defines the most significant bits of the 0-modulo-32 byte start address of the memory region. Reserved — MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 214: Region Descriptor 0, Word 1 (Rgd0_Word1)
31-5 End Address ENDADDR Defines the most significant bits of the 31-modulo-32 byte end address of the memory region. NOTE: The MPU does not verify that ENDADDR ≥ SRTADDR. Reserved — MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 215: Region Descriptor 0, Word 2 (Rgd0_Word2)
Writes to RGDn_WORD2 clear the region descriptor’s valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write to RGDAACn instead because stores to these locations do not affect the descriptor’s valid bit. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 216 1b - Bus master 4 writes allowed Reserved — This bit must be written with a zero. 22-21 Bus Master 3 Supervisor Mode Access Control Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 217 0b - Do not include the process identifier in the evaluation M0PE 1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation Bus Master 0 Supervisor Mode Access Control Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 218: Region Descriptor 0, Word 3 (Rgd0_Word3)
RGD0_WORD3 40Ch 13.4.8.2 Function The fourth word of the region descriptor contains the optional process identifier and mask, plus the region descriptor’s valid bit. 13.4.8.3 Diagram Bits PIDMASK Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 219: Region Descriptor N, Word 1 (Rgd1_Word1 - Rgd15_Word1)
404h + (n × 10h) 13.4.9.2 Function The second word of the region descriptor defines the 31-modulo-32 byte end address of the memory region. Writes to this register clear the region descriptor’s valid bit (RGDn_WORD3[VLD]). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 220: Region Descriptor N, Word 2 (Rgd1_Word2 - Rgd15_Word2)
NOTE: The MPU does not verify that ENDADDR ≥ SRTADDR. Reserved — 13.4.10 Region Descriptor n, Word 2 (RGD1_WORD2 - RGD15_ WORD2) 13.4.10.1 Offset For n = 1 to 15: Register Offset RGDn_WORD2 408h + (n × 10h) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 221 Writes to RGDn_WORD2 clear the region descriptor’s valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write to RGDAACn instead because stores to these locations do not affect the descriptor’s valid bit. 13.4.10.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 222 Defines the access controls for bus master 2 in Supervisor mode. 00b - r/w/x; read, write and execute allowed 01b - r/x; read and execute allowed, but no write Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 223: Region Descriptor N, Word 3 (Rgd1_Word3 - Rgd15_Word3)
0b - An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed 1b - Allows the given access type to occur MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 224 Provides a masking capability so that multiple process identifiers can be included as part of the region hit determination. If a bit in PIDMASK is set, then the corresponding PID bit is ignored in the comparison. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 225: Region Descriptor Alternate Access Control 0 (Rgdaac0)
Because software may adjust only the access controls within a region descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of this 32- bit entity is available. Writing to this register does not affect the descriptor’s valid bit. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 226 0b - Bus master 4 writes terminate with an access error and the write is not performed M4WE 1b - Bus master 4 writes allowed Reserved — This bit must be written with a zero. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 227 0b - An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 228: Region Descriptor Alternate Access Control N (Rgdaac1 - Rgdaac15)
Because software may adjust only the access controls within a region descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of this 32- bit entity is available. Writing to this register does not affect the descriptor’s valid bit. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 229 0b - Bus master 4 writes terminate with an access error and the write is not performed M4WE 1b - Bus master 4 writes allowed Reserved — This bit must be written with a zero. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 230 0b - An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 231: Functional Description
(RGDn) and performs two major functions: • Region hit determination • Detection of an access protection violation The following figure shows a functional block diagram. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 232 RGDn_Word3[PID] and RGDn_Word3[PIDMASK] are the process identifier fields from region descriptor n. For bus masters that do not output a process identifier, the MPU forces the pid_hit term to assert. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 233: Putting It All Together And Error Terminations
As shown in the third condition, granting permission is a higher priority than denying access for overlapping regions. This approach is more flexible to system software in region descriptor assignments. For an example of the use of overlapping region descriptors, see Application information. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 234: Power Management
(RGDn_Word{0,1,3}). Word 0 and 1 redefine the start and end addresses, respectively. Word 3 re-enables the region descriptor valid bit. In most situations, all four words of the region descriptor are rewritten. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 235 Of particular interest are the two overlapping spaces: region descriptors 2 & 3 and 3 & 4. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 236 • The remaining peripheral region accessible to both processors and the traditional DMA1 master This example shows one possible application of the capabilities of the MPU in a typical system. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 237: Peripheral Bridge (Aips-Lite)
Table 14-1. Register reset values Register WCT1014S WCT1015S WCT1016S MPRA 7770_0000 7770_0000 7777_0000 PACRA 5400_0000 5400_0000 5400_0000 PACRB 4400_0400 4400_0400 4400_0400 PACRD 4400_0000 4400_0000 4400_0000 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 238: Introduction
The slave devices connected to the peripheral bridge are modules which contain a programming model of control and status registers. The system masters read and write these registers through the peripheral bridge. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 239: Memory Map/Register Definition
Off-Platform Peripheral Access Control Register (OPACRH) 0040_0000h Off-Platform Peripheral Access Control Register (OPACRI) 0404_4444h Off-Platform Peripheral Access Control Register (OPACRJ) 0044_4044h Off-Platform Peripheral Access Control Register (OPACRK) 4404_0040h Off-Platform Peripheral Access Control Register (OPACRL) 0400_0444h MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 240 Determines whether the master is trusted for read accesses. 0b - This master is not trusted for read accesses. 1b - This master is trusted for read accesses. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 241 0b - This master is not trusted for read accesses. 1b - This master is trusted for read accesses. Master 3 Trusted For Writes MTW3 Determines whether the master is trusted for write accesses. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 242 The peripheral assignment to each PACR field is defined by the memory map slot of the peripheral. See the chip-specific AIPS information for the field assignment of a particular peripheral. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 243 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Reserved — Supervisor Protect Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 244 1b - Accesses from an untrusted master are not allowed. 23-20 Reserved — 19-16 Reserved — 15-12 Reserved — 11-8 Reserved — Reserved — Reserved — 14.3.1.4 Peripheral Access Control Register (PACRB) 14.3.1.4.1 Offset Register Offset PACRB MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 245 0b - Accesses from an untrusted master are allowed. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 246 0b - Accesses from an untrusted master are allowed. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 247 AIPS information for the field assignment of a particular peripheral. Every PACR field to which no peripheral is assigned is reserved. Reads to reserved locations return zeros, and writes are ignored. 14.3.1.5.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 248 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. 23-20 Reserved — 19-16 Reserved — 15-12 Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 249 OPACR field is defined by the memory map slot of the peripheral. See the chip- specific AIPS information for the field assignment of a particular peripheral. 14.3.1.6.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 250 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. 23-20 Reserved — 19-16 Reserved — Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 251 If not, access terminates with an error response and no peripheral access initiates. 0b - This peripheral does not require supervisor privilege level for accesses. 1b - This peripheral requires supervisor privilege level for accesses. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 252 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. 14.3.1.7 Off-Platform Peripheral Access Control Register (OPACRB) 14.3.1.7.1 Offset Register Offset OPACRB MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 253 0b - This peripheral allows write accesses. 1b - This peripheral is write protected. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 254 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 255 The peripheral assignment to each OPACR field is defined by the memory map slot of the peripheral. See the chip- specific AIPS information for the field assignment of a particular peripheral. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 256 If not, access terminates with an error response and no peripheral access initiates. 0b - This peripheral does not require supervisor privilege level for accesses. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 257 If not, access terminates with an error response and no peripheral access initiates. 0b - This peripheral does not require supervisor privilege level for accesses. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 258 OPACR field is defined by the memory map slot of the peripheral. See the chip- specific AIPS information for the field assignment of a particular peripheral. 14.3.1.9.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 259 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Reserved — Supervisor Protect Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 260 If not, access terminates with an error response and no peripheral access initiates. 0b - This peripheral does not require supervisor privilege level for accesses. 1b - This peripheral requires supervisor privilege level for accesses. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 261 The peripheral assignment to each OPACR field is defined by the memory map slot of the peripheral. See the chip- specific AIPS information for the field assignment of a particular peripheral. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 262 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. 27-24 Reserved — 23-20 Reserved — 19-16 Reserved — 15-12 Reserved — 11-8 Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 263 The peripheral assignment to each OPACR field is defined by the memory map slot of the peripheral. See the chip- specific AIPS information for the field assignment of a particular peripheral. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 264 0b - This peripheral does not require supervisor privilege level for accesses. 1b - This peripheral requires supervisor privilege level for accesses. Write Protect Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 265 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 266 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Reserved — Reserved — MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 267 AIPS information for the field assignment of a particular peripheral. 14.3.1.12.3 Diagram Bits Reset Bits Reset 14.3.1.12.4 Fields Field Function 31-28 Reserved — 27-24 Reserved — Reserved — Supervisor Protect Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 268 If not, access terminates with an error response and no peripheral access initiates. 0b - This peripheral does not require supervisor privilege level for accesses. 1b - This peripheral requires supervisor privilege level for accesses. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 269 The peripheral assignment to each OPACR field is defined by the memory map slot of the peripheral. See the chip- specific AIPS information for the field assignment of a particular peripheral. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 270 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. 19-16 Reserved — 15-12 Reserved — 11-8 Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 271 OPACR field is defined by the memory map slot of the peripheral. See the chip- specific AIPS information for the field assignment of a particular peripheral. 14.3.1.14.3 Diagram Bits Reset Bits Reset 14.3.1.14.4 Fields Field Function 31-28 Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 272 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Reserved — Supervisor Protect Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 273 0b - This peripheral does not require supervisor privilege level for accesses. 1b - This peripheral requires supervisor privilege level for accesses. Write Protect Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 274 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. 14.3.1.15 Off-Platform Peripheral Access Control Register (OPACRJ) 14.3.1.15.1 Offset Register Offset OPACRJ MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 275 0b - This peripheral allows write accesses. 1b - This peripheral is write protected. Trusted Protect Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 276 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. 11-8 Reserved — Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 277 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. 14.3.1.16 Off-Platform Peripheral Access Control Register (OPACRK) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 278 0b - This peripheral allows write accesses. 1b - This peripheral is write protected. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 279 0b - Accesses from an untrusted master are allowed. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 280 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Reserved — 14.3.1.17 Off-Platform Peripheral Access Control Register (OPACRL) 14.3.1.17.1 Offset Register Offset OPACRL MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 281 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 282 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 283: Functional Description
All accesses to the peripheral slots must be sized less than or equal to the designated peripheral slot size. If an access is attempted that is larger than the targeted port, an error response is generated. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 284 Functional description MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 285: Direct Memory Access Multiplexer (Dmamux)
Asynchronous DMA operation does not support trigger options. In cases where multiple DMA request are routed to DMAMUX source, software needs to make sure that only one DMA request is enabled at a time. 15.2 Introduction MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 286: Overview
• The first 4 channels additionally provide a trigger functionality. • Each channel router can be assigned to one of the possible peripheral DMA slots or to one of the always-on slots. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 287: Modes Of Operation
PIT). This mode is available only for channels 0–3. 15.3 Memory map/register definition This section provides a detailed description of all memory-mapped registers in the DMAMUX. 15.3.1 DMAMUX register descriptions 15.3.1.1 DMAMUX Memory map DMAMUX base address: 4002_1000h MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 288 This is true, even if a channel is disabled (ENBL==0). Before changing the trigger or source settings, a DMA channel must be disabled via CHCFGn[ENBL]. 15.3.1.2.3 Diagram Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 289: Functional Description
Besides the normal routing functionality, the first 4 channels of the DMAMUX provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames, or packets at fixed intervals without the need for processor intervention. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 290 This trigger works by gating the request from the peripheral to the DMA until a trigger event has been seen. This is illustrated in the following figure. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 291 DMA to periodically transfer data from one or more GPIO ports, it is possible to sample complex waveforms and store the results in tabular form in on- chip memory. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 292: Dma Channels With No Triggering Capability
DMA transfer will impose on the system. For this option, the DMA channel must be disabled in the DMA channel MUX. • Use explicit software reactivation. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 293: Initialization/Application Information
4. Configure the corresponding timer. 5. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are set. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 294 The following code example illustrates steps 1 and 3 above: In File registers.h: #define DMAMUX_BASE_ADDR 0x40021000/* Example only ! */ /* Following example assumes char is 8-bits */ volatile unsigned char *CHCFG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 295 *CHCFG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); volatile unsigned char *CHCFG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001); volatile unsigned char *CHCFG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002); volatile unsigned char *CHCFG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003); MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 296 *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); In File main.c: #include "registers.h" *CHCFG8 = 0x00; *CHCFG8 = 0x87; MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 297: Enhanced Direct Memory Access (Edma)
The hardware microarchitecture includes: • A DMA engine that performs: • Source address and destination address calculations • Data-movement operations • Local memory containing transfer control descriptors for each of the 16 channels MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 298: Edma System Block Diagram
All the channels provide the same functionality. This structure allows data transfers associated with one channel to be Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 299: Features
It is intended for use in applications where the data size to be transferred is statically known and not defined within the transferred data itself. The eDMA module features: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 300 • Programmable support for scatter/gather DMA processing • Support for complex data structures In the discussion of this module, n is used to reference the channel number. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 301: Modes Of Operation
The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1, ... channel 15. Each TCDn definition is presented as 11 registers of 16 or 32 bits. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 302: Tcd Initialization
• Writes to reserved bits in a register are ignored. • Reading or writing a reserved memory location generates a bus error. 16.4.5 DMA register descriptions 16.4.5.1 DMA Memory map DMA base address: 4000_8000h MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 303 TCD Transfer Attributes (TCD0_ATTR - TCD15_ATTR) Table 16-4 11E6h 1008h - TCD Minor Byte Count (Minor Loop Mapping Disabled) (TCD0_NBY Table 16-4 11E8h TES_MLNO - TCD15_NBYTES_MLNO) Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 304 The channel priority registers assign the priorities; see the DCHPRIn registers. For round-robin arbitration, the channel priorities are ignored and channels are cycled through (from high to low channel number) without regard to priority. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 305 NBYTES field is a 30-bit vector. When minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are assigned to the NBYTES field. 16.4.5.2.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 306 0b - Normal operation 1b - Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 307 • An error termination to a bus master read or write cycle • A cancel transfer with error bit that will be set when a transfer is canceled via the corresponding cancel transfer control bit Fault reporting and handling for more details. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 308 1b - The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. Destination Address Error 0b - No destination address configuration error Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 309 DMA request input signals and this enable request flag must be asserted before a channel's hardware service request is accepted. The state of the DMA enable request flag does not affect a channel service request made explicitly through software or a linked channel request. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 310 0b - The DMA request signal for the corresponding channel is disabled ERQ8 1b - The DMA request signal for the corresponding channel is enabled Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 311 SEEI and CEEI. These registers are provided so that the error interrupt enable for a single channel can easily be modified without the need to perform a read-modify-write sequence to the EEI register. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 312 0b - The error signal for corresponding channel does not generate an error interrupt EEI8 1b - The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 7 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 313 32-bit write while not affecting the other registers addressed in the write. In such a case the other three bytes of the word would all have their NOP bit set so that that these register will not be affected by the write. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 314 The data value on a register write causes the corresponding bit in the EEI to be set. Setting the SAEE bit provides a global set function, forcing the entire EEI contents to be set. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 315 1b - Sets all bits in EEI Reserved — Set Enable Error Interrupt SEEI Sets the corresponding bit in EEI 16.4.5.8 Clear Enable Request Register (CERQ) 16.4.5.8.1 Offset Register Offset CERQ MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 316 0b - Clear only the ERQ bit specified in the CERQ field CAER 1b - Clear all bits in ERQ Reserved — Clear Enable Request CERQ Clears the corresponding bit in ERQ. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 317 Set All Enable Requests 0b - Set only the ERQ bit specified in the SERQ field SAER 1b - Set all bits in ERQ Reserved — Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 318 Reads of this register return all zeroes. 16.4.5.10.3 Diagram Bits Reset 16.4.5.10.4 Fields Field Function No Op enable Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 319 In such a case the other three bytes of the word would all have their NOP bit set so that that these register will not be affected by the write. Reads of this register return all zeroes. 16.4.5.11.3 Diagram Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 320 If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. 16.4.5.12.3 Diagram Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 321 In such a case the other three bytes of the word would all have their NOP bit set so that that these register will not be affected by the write. Reads of this register return all zeroes. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 322 During the interrupt-service routine associated with any given channel, it is the software's responsibility to clear the appropriate bit, negating the interrupt request. Typically, a write to the CINT register in the interrupt service routine is used for this purpose. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 323 1b - The interrupt request for corresponding channel is active Interrupt Request 10 0b - The interrupt request for corresponding channel is cleared INT10 1b - The interrupt request for corresponding channel is active Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 324 The eDMA engine signals the occurrence of an error condition by setting the appropriate bit in this register. The outputs of this register are enabled by the MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 325 Error In Channel 14 0b - An error in this channel has not occurred ERR14 1b - An error in this channel has occurred Error In Channel 13 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 326 1b - An error in this channel has occurred Error In Channel 0 0b - An error in this channel has not occurred ERR0 1b - An error in this channel has occurred 16.4.5.16 Hardware Request Status Register (HRS) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 327 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 328 0b - A hardware service request for channel 7 is not present 1b - A hardware service request for channel 7 is present Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 329 0b - A hardware service request for channel 0 is not present 1b - A hardware service request for channel 0 is present 16.4.5.17 Enable Asynchronous Request in Stop Register (EARS) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 330 1b - Enable asynchronous DMA request for channel 12. Enable asynchronous DMA request in stop mode for channel 11 0b - Disable asynchronous DMA request for channel 11. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 331 1b - Enable asynchronous DMA request for channel 0. 16.4.5.18 Channel Priority Register (DCHPRI0 - DCHPRI15) 16.4.5.18.1 Offset Register Offset DCHPRI3 100h DCHPRI2 101h DCHPRI1 102h DCHPRI0 103h Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 332 The range of the priority value is limited to the values of 0 through 15. 16.4.5.18.3 Diagram Bits CHPRI Register Reset reset values. 16.4.5.18.4 Register reset values Register Reset value DCHPRI0 DCHPRI1 DCHPRI2 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 333 CHPRI Channel priority when fixed-priority arbitration is enabled 16.4.5.19 TCD Source Address (TCD0_SADDR - TCD15_SADDR) 16.4.5.19.1 Offset For n = 0 to 15: Register Offset TCDn_SADDR 1000h + (n × 20h) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 334 16.4.5.20 TCD Signed Source Address Offset (TCD0_SOFF - TCD15_ SOFF) 16.4.5.20.1 Offset For n = 0 to 15: Register Offset TCDn_SOFF 1004h + (n × 20h) 16.4.5.20.2 Diagram Bits SOFF Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 335 SMOD function constraining the addresses to a 0-modulo-size range. 10-8 Source data transfer size NOTE: Using a Reserved value causes a configuration error. SSIZE Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 336 TCD word 2 is defined as follows if: • Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions for the definition of TCD word 2. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 337 16.4.5.23 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (TCD0_NBYTES_MLOFFNO - TCD15_NBYTES_MLOFFNO) 16.4.5.23.1 Offset For n = 0 to 15: Register Offset TCDn_NBYTES_MLOFF 1008h + (n × 20h) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 338 0b - The minor loop offset is not applied to the DADDR 1b - The minor loop offset is applied to the DADDR 29-0 Minor Byte Transfer Count NBYTES Number of bytes to be transferred in each service request of the channel. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 339 If minor loop mapping is enabled and SMLOE and DMLOE are cleared, then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop mapping is disabled, then refer to the TCD_NBYTES_MLNO register description. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 340 TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. 16.4.5.25 TCD Last Source Address Adjustment (TCD0_SLAST - TCD15_SLAST) 16.4.5.25.1 Offset For n = 0 to 15: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 341 16.4.5.26 TCD Destination Address (TCD0_DADDR - TCD15_DADDR) 16.4.5.26.1 Offset For n = 0 to 15: Register Offset TCDn_DADDR 1010h + (n × 20h) 16.4.5.26.2 Function This register contains the destination address of the transfer. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 342 Memory address pointing to the destination data. 16.4.5.27 TCD Signed Destination Address Offset (TCD0_DOFF - TCD15_DOFF) 16.4.5.27.1 Offset For n = 0 to 15: Register Offset TCDn_DOFF 1014h + (n × 20h) 16.4.5.27.2 Diagram Bits DOFF Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 343 If the ELINK field is cleared, this register is defined as follows. 16.4.5.28.3 Diagram Bits Reset 16.4.5.28.4 Fields Field Function Enable channel-to-channel linking on minor-loop complete Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 344 Loop Count (Channel Linking Disabled) (TCD0_CITER_ELINKNO - TCD15_CITER_ ELINKNO), but its fields are defined differently based on the state of the ELINK field. If the ELINK field is set, this register is defined as follows. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 345 NOTE: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. 16.4.5.30 TCD Last Destination Address Adjustment/Scatter Gather Address (TCD0_DLASTSGA - TCD15_DLASTSGA) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 346 This channel reload is performed as the major iteration count completes. The scatter/gather address must be 0-modulo-32-byte, otherwise a configuration error is reported. 16.4.5.31 TCD Control and Status (TCD0_CSR - TCD15_CSR) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 347 • After the major loop counter is exhausted, the eDMA engine initiates a channel service request at the channel defined by this field by setting that channel's TCDn_CSR[START] bit. Channel Done DONE Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 348 If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this flag after the channel begins execution. 0b - The channel is not explicitly started. 1b - The channel is explicitly started via a software initiated service request. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 349 As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. 0b - The channel-to-channel linking is disabled 1b - The channel-to-channel linking is enabled 14-0 Starting Major Iteration Count BITER MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 350 If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as follows. 16.4.5.33.3 Diagram Bits Reset 16.4.5.33.4 Fields Field Function Enables channel-to-channel linking on minor loop complete ELINK Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 351: Functional Description
16.5.1 eDMA basic data flow The basic flow of a data transfer can be partitioned into three segments. As shown in the following diagram, the first segment involves the channel activation: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 352 The following diagram illustrates the second part of the basic data flow: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 353 (if scatter/ gather is enabled). The updates to the TCD memory and the assertion of an interrupt request are shown in the following diagram. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 354: Fault Reporting And Handling
Each of these possible causes are detailed below: • The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries. • The minor loop byte count must be a multiple of the source and destination transfer sizes. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 355 Due to pipeline effect, the next transfer is already in progress when the bus error is received by the eDMA. If a bus error MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 356 If a channel is terminated by an error and then issues another service request before the error is fixed, that channel executes and terminates with the same error condition. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 357: Channel Preemption
3. Enable error interrupts in the EEI register if so desired. 4. Write the 32-byte TCD for each channel that may request service. 5. Enable any hardware service requests via the ERQ register. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 358 CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 359: Programming Errors
The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per channel basis with the exception of channel priority error (ES[CPE]). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 360: Arbitration Mode Considerations
(TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel service request is acknowledged and the channel is selected to execute. After the transfer is complete, the TCDn_CSR[DONE] bit is set and an interrupt generates if properly enabled. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 361 Write 32-bits to location 0x2008 → third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 362 Write 32-bits to location 0x2004 → second iteration of the minor loop. e. Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 363 Write 32-bits to location 0x201C → last iteration of the minor loop → major loop complete. 14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 2 (TCDn_BITER). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 364: Monitoring Transfer Descriptor Status
There are two methods to test for minor loop completion when using software initiated service requests. The first is to read the TCDn_CITER field and test for a change. Another method may be extracted from the sequence shown below. The second method is MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 365 The true values of the SADDR, DADDR, and NBYTES are the values the eDMA engine currently uses in its internal register file and not the values in the TCD local memory for that channel. The addresses, SADDR and MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 366: Channel Linking
TCDn_CITER[E_LINK] = 1 TCDn_CITER[LINKCH] = 0xC TCDn_CITER[CITER] value = 0x4 TCDn_CSR[MAJOR_E_LINK] = 1 TCDn_CSR[MAJOR_LINKCH] = 0x7 executes as: 1. Minor loop done → set TCD12_CSR[START] bit MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 367: Dynamic Programming
This section provides recommended methods to change the programming model during channel execution. 16.6.7.1 Dynamically changing the channel priority The following two options are recommended for dynamically changing channel priority levels: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 368 TCD.done bit is set, indicating the major loop is complete. NOTE The user must clear the The TCDn_CSR[DONE] bit before writing the TCDn_CSR[MAJORELINK] bit. The TCDn_CSR[DONE] bit is cleared automatically by the eDMA engine after a channel begins execution. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 369 1. When the descriptors are built, write a unique TCD ID in the TCDn_CSR[MAJORLINKCH] field for each TCD associated with a channel using dynamic scatter/gather. 2. Write 1b to the TCDn_CSR[DREQ] bit. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 370 If ESG = 0b, read the 32 bit TCDn_DLASTSGA field. If ESG = 0b and the TCDn_DLASTSGA did not change, the attempted dynamic link did not succeed (the channel was already retiring). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 371: Suspend/Resume A Dma Channel With Active Hardware Service Requests
TXFIFO upon the request. If the user needs to suspend the DMA/SPI transfer loop, perform the following steps: 1. Disable the DMA service request at the source by writing 0 to SPI_RSER[TFFF_RE]. Confirm that SPI_RSER[TFFF_RE] is 0. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 372 DMA_HRS[HRSn] is 0 for the appropriate channel. If no service request is present, disable the DMA channel by clearing the channel's ERQ bit. If a service request is present, wait until the request has been processed and the HRS bit reads zero. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 373: Trigger Mux Control (Trgmux)
32-bit trigger control register. Each control register supports up to four triggers, and each trigger can be selected from the available input triggers. The following figure shows the main structure of TRGMUX, using Module_A as an example. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 374 The following figures show the superset of trigger inputs, outputs, and control registers for the MWCT101xS series. See attached MWCT101xS_Trigger_Muxing.xlsx for details on recommendations which must be adhered while using the triggering scheme. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 375 * In the ADC Configuration chapter, see the "Trigger Latching and Arbitration" section for details. * Interrupt enable needs to beconfigured before expecting RTC_alarm and RTC_second trigger from TRGMUX Figure 17-2. Trigger interconnectivity (part 1 of 2: outputs 0-63) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 376 Interrupt enable needs to be configured before expecting RTC_alarm and RTC_second trigger from TRGMUX Note: Above figure shows all the connections. Slots for an absent instance in a particular part are reserved. Figure 17-3. Trigger interconnectivity (part 2 of 2: outputs 64-127) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 377: Chip-Specific Trgmux Registers
17.3 Features The TRGMUX module allows software to select the trigger source for peripherals. The block diagram below shows the trigger selection logic of the TRGMUX module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 378: Memory Map And Register Definition
17.4.1 TRGMUX register descriptions 17.4.1.1 TRGMUX Memory map Table 17-2. Select Bit Fields Field Description SELx This read/write field is used to configure the MUX select for the peripheral trigger inputs. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 379 0001_1110 - (0x1E) ADC0_SC1A[COCO] 0001_1111 - (0x1F) ADC0_SC1B[COCO] 0010_0000 - (0x20) ADC1_SC1A[COCO] 0010_0001 - (0x21) ADC1_SC1B[COCO] 0010_0010 - (0x22) PDB0_CH0_TRIG 0010_0011 - (0x23) Reserved 0010_0100 - (0x24) PDB0_PULSE_OUT 0010_0101 - (0x25) PDB1_CH0_TRIG MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 380 0100_0100 - (0x44) LPI2C1_Slave_trigger 0100_0101 - (0x45) FTM4_INIT_TRIG 0100_0110 - (0x46) FTM4_EXT_TRIG 0100_0111 - (0x47) FTM5_INIT_TRIG 0100_1000 - (0x48) FTM5_EXT_TRIG 0100_1001 - (0x49) FTM6_INIT_TRIG 0100_1010 - (0x4A) FTM6_EXT_TRIG 0100_1011 - (0x4B) FTM7_INIT_TRIG MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 381 0110_1010 - (0x6A) Reserved 0110_1011 - (0x6B) Reserved 0110_1100 - (0x6C) Reserved 0110_1101 - (0x6D) Reserved 0110_1110 - (0x6E) Reserved 0110_1111 - (0x6F) Reserved 0111_0000 - (0x70) Reserved 0111_0001 - (0x71) Reserved MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 382 TRGMUX LPUART0 Register (LPUART0) 0000_0000h TRGMUX LPUART1 Register (LPUART1) 0000_0000h TRGMUX LPI2C0 Register (LPI2C0) 0000_0000h TRGMUX LPSPI0 Register (LPSPI0) 0000_0000h TRGMUX LPSPI1 Register (LPSPI1) 0000_0000h Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 383 17.4.1.2.2 Function This register is for the DMAMUX0 module. 17.4.1.2.3 Diagram Bits SEL3 SEL2 Reset Bits SEL1 SEL0 Reset 17.4.1.2.4 Fields Field Function TRGMUX register lock. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 384 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.3 TRGMUX EXTOUT0 Register (EXTOUT0) 17.4.1.3.1 Offset Register Offset EXTOUT0 17.4.1.3.2 Function This register is for the EXTOUT0 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 385 Trigger MUX Input 0 Source Select SEL0 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 386 This read/write bit field is used to configure the MUX select for peripheral trigger input 2. For the field setting definitions, see Memory map and register definition. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 387 Memory map and register definition. 17.4.1.5 TRGMUX ADC0 Register (ADC0) 17.4.1.5.1 Offset Register Offset ADC0 17.4.1.5.2 Function This register is for the ADC0 module. 17.4.1.5.3 Diagram Bits SEL3 SEL2 Reset Bits SEL1 SEL0 Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 388 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.6 TRGMUX ADC1 Register (ADC1) 17.4.1.6.1 Offset Register Offset ADC1 17.4.1.6.2 Function This register is for the ADC1 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 389 Trigger MUX Input 0 Source Select SEL0 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 390 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 391 17.4.1.8.2 Function This register is for the FTM0 module. 17.4.1.8.3 Diagram Bits SEL3 SEL2 Reset Bits SEL1 SEL0 Reset 17.4.1.8.4 Fields Field Function TRGMUX register lock. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 392 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.9 TRGMUX FTM1 Register (FTM1) 17.4.1.9.1 Offset Register Offset FTM1 17.4.1.9.2 Function This register is for the FTM1 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 393 Trigger MUX Input 0 Source Select SEL0 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 394 This read/write bit field is used to configure the MUX select for peripheral trigger input 2. For the field setting definitions, see Memory map and register definition. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 395 Memory map and register definition. 17.4.1.11 TRGMUX FTM3 Register (FTM3) 17.4.1.11.1 Offset Register Offset FTM3 17.4.1.11.2 Function This register is for the FTM3 module. 17.4.1.11.3 Diagram Bits SEL3 SEL2 Reset Bits SEL1 SEL0 Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 396 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.12 TRGMUX PDB0 Register (PDB0) 17.4.1.12.1 Offset Register Offset PDB0 17.4.1.12.2 Function This register is for the PDB0 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 397 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.13 TRGMUX PDB1 Register (PDB1) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 398 This read-only bit field is reserved and always has the value 0. — 14-8 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 399 Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next system reset clears LK. 0b - Register can be written. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 400 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.15 TRGMUX LPIT0 Register (LPIT0) 17.4.1.15.1 Offset Register Offset LPIT0 17.4.1.15.2 Function This register is for the LPIT0 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 401 Trigger MUX Input 0 Source Select SEL0 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 402 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 403 Offset LPUART1 17.4.1.17.2 Function This register is for the LPUART1 module. 17.4.1.17.3 Diagram Bits Reset Bits SEL0 Reset 17.4.1.17.4 Fields Field Function TRGMUX register lock. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 404 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.18 TRGMUX LPI2C0 Register (LPI2C0) 17.4.1.18.1 Offset Register Offset LPI2C0 17.4.1.18.2 Function This register is for the LPI2C0 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 405 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.19 TRGMUX LPSPI0 Register (LPSPI0) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 406 This read-only bit field is reserved and always has the value 0. — 14-8 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 407 Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next system reset clears LK. 0b - Register can be written. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 408 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.21 TRGMUX LPTMR0 Register (LPTMR0) 17.4.1.21.1 Offset Register Offset LPTMR0 17.4.1.21.2 Function This register is for the LPTMR0 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 409 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.22 TRGMUX LPI2C1 Register (LPI2C1) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 410 This read-only bit field is reserved and always has the value 0. — 14-8 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 411 Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next system reset clears LK. 0b - Register can be written. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 412 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.24 TRGMUX FTM5 Register (FTM5) 17.4.1.24.1 Offset Register Offset FTM5 17.4.1.24.2 Function This register is for the FTM5 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 413 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.25 TRGMUX FTM6 Register (FTM6) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 414 This read-only bit field is reserved and always has the value 0. — 14-8 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 415 Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next system reset clears LK. 0b - Register can be written. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 416 Trigger MUX Input 0 Source Select SEL0 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 417: External Watchdog Monitor (Ewm)
Wait mode and power down mode is not supported. See Module operation in available power modes for details on available power modes. Table 18-1. EWM low-power modes Module mode Chip mode Stop Stop, VLPS MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 418: Introduction
• Programmable window. • Refresh outside window leads to assertion of EWM_OUT_b. • Robust refresh mechanism • Write values of 0xB4 and 0x2C to EWM Refresh Register within 15 peripheral bus clock cycles. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 419: Modes Of Operation
Entry to debug mode has no effect on the EWM. • If the EWM is enabled prior to entry of debug mode, it remains enabled. • If the EWM is disabled prior to entry of debug mode, it remains disabled. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 420: Block Diagram
EWM_in EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active low. EWM_OUT_b EWM reset out signal MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 421: Memory Map/Register Definition
Control Register (CTRL) Service Register (SERV) WORZ Compare Low Register (CMPL) RWONC Compare High Register (CMPH) RWONC Clock Prescaler Register (CLKPRESCALER) RWONC 18.4.1.2 Control Register (CTRL) 18.4.1.2.1 Offset Register Offset CTRL MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 422 EWM_OUT_b signal. This bit when unset, keeps the EWM module disabled. It cannot be re-enabled until a next reset, due to the write-once nature of this bit. 18.4.1.3 Service Register (SERV) 18.4.1.3.1 Offset Register Offset SERV MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 423 18.4.1.4.1 Offset Register Offset CMPL 18.4.1.4.2 Function The CMPL register is reset to zero after a CPU reset. This provides no minimum time for the CPU to refresh the EWM counter. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 424 CPU to refresh the EWM counter. NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 425 This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. NOTE Write the required prescaler value before enabling the EWM. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 426: Functional Description
AC motor in a large appliance. The EWM_OUT_b signal remains deasserted when the EWM is being regularly refreshed by the CPU within the programmable refresh window, indicating that the application code is executed as expected. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 427: Ewm_Out_B Pin State In Low Power Modes
EWM_OUT_b signal that controls the gating circuit. The EWM_in signal is ignored if the EWM is disabled, or if INEN bit of CTRL register is cleared, as after any reset. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 428: Ewm Counter
EWM Service Register. The CPU must access the EWM service register with correct write of unique data within the windowed time frame as determined by the CMPL and CMPH registers for correct EWM refresh operation. Therefore, three possible conditions can occur: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 429: Ewm Interrupt
CLKPRESCALER[CLK_DIV]. This divided clock is used to run the EWM counter. NOTE The divided clock used to run the EWM counter must be no more than half the frequency of the bus clock. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 430 Functional Description MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 431: Error Injection Module (Eim)
The Error Injection Module (EIM) is mainly used for diagnostic purposes. It provides a method for diagnostic coverage of the peripheral memories. See the chip-specific EIM information to determine which peripheral memories are supported by this method. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 432: Overview
64-bit read data bus and an 8-bit checkbit bus. rdata[63](MSB) rdata[62] rdata[61] Module array rdata[0](LSB) chkbit[7] chkbit[0] EIMCR[GEIEN] EICHEN[EICHnEN] EICHDn_WORD0 EICHDn_WORD1 EICHDn_WORD2 Figure 19-1. EIM functional block diagram (64-bit read data bus and 8-bit check bit bus) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 433: Features
Error Injection Channel Descriptor n, Word0 for details. • The remaining words, Word1-3 (EICHDn_WORD1-3), define the data mask. Word2 and Word3 are used only when required by the total width of the MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 434: Eim Memory Map
0000_0000h 200h Error Injection Channel Descriptor n, Word0 (EICHD1_WORD0) 0000_0000h 204h Error Injection Channel Descriptor n, Word1 (EICHD1_WORD1) 0000_0000h 19.3.2 Error Injection Module Configuration Register (EIMCR) 19.3.2.1 Offset Register Offset EIMCR MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 435: Error Injection Channel Enable Register (Eichen)
This bit globally enables or disables the error injection function of the EIM. This field is initialized by hardware reset. 0b - Disabled 1b - Enabled 19.3.3 Error Injection Channel Enable register (EICHEN) 19.3.3.1 Offset Register Offset EICHEN MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 436 Error Injection Channel 1 Enable EICH1EN This field enables the corresponding error injection channel. The Global Error Injection Enable (EIMCR[GEIEN]) field must also be asserted to enable error injection. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 437 — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 438: Error Injection Channel Descriptor N, Word0 (Eichd0_Word0 - Eichd1_Word0)
Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — 19.3.4 Error Injection Channel Descriptor n, Word0 (EICHD0_W ORD0 - EICHD1_WORD0) 19.3.4.1 Offset Register Offset EICHD0_WORD0 100h EICHD1_WORD0 200h MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 439 0b - The corresponding bit of the checkbit bus remains unmodified. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 440: Error Injection Channel Descriptor N, Word1 (Eichd0_Word1 - Eichd1_Word1)
A successful write to this field clears the corresponding error injection channel valid field, EICHEN[EICHnEN]. 19.3.5.3 Diagram Bits B0_3DATA_MASK Reset Bits B0_3DATA_MASK Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 441: Functional Description
Figure 19-1 depicts the interception and override of a 64-bit read data bus and an 8-bit checkbit data bus for an example memory array. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 442 • Read from the memory being injected to see the error • In the error handling routine • Turn off the EIM global module enable (EIMCR) • Disable the EIM channel (EICHxEN) • Clear the data inversion register (EICHDx_WORDy) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 443: Error Reporting Module (Erm)
ERM collects ECC events on memory accesses for platform local memory arrays, such as flash memory, system RAM, or peripheral RAMs. See the chip-specific ERM information for details about supported memory sources and specific memory channel assignments. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 444: Features
20.3.1 ERM Memory map ERM base address: 4001_8000h Offset Register Width Access Reset value (In bits) ERM Configuration Register 0 (CR0) 0000_0000h ERM Status Register 0 (SR0) 0000_0000h Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 445: Erm Configuration Register 0 (Cr0)
20.3.2 ERM Configuration Register 0 (CR0) 20.3.2.1 Offset Register Offset 20.3.2.2 Function This 32-bit control register configures the interrupt notification capability for: • Channel 0 • Channel 1 20.3.2.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 446 1b - Interrupt notification of Memory 1 non-correctable error events is enabled. 25-24 Reserved — 23-22 Reserved — 21-20 Reserved — 19-18 Reserved — 17-16 Reserved — 15-14 Reserved — 13-12 Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 447: Erm Status Register 0 (Sr0)
— Reserved — 20.3.3 ERM Status Register 0 (SR0) 20.3.3.1 Offset Register Offset 20.3.3.2 Function This 32-bit control register configures the interrupt notification capability for: • Channel 0 • Channel 1 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 448 Write 1 to clear this field. This write also clears the corresponding interrupt notification, if CR0[ESCIE1] is enabled. NOTE: See the chip-specific ERM information for details on Memory 1 mapping. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 449: Erm Memory N Error Address Register (Ear0 - Ear1)
19-16 Reserved — 15-12 Reserved — 11-8 Reserved — Reserved — Reserved — 20.3.4 ERM Memory n Error Address Register (EAR0 - EAR1) 20.3.4.1 Offset Register Offset EAR0 100h EAR1 110h MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 450: Functional Description
NOTE: See the chip-specific ERM information for details on Memory n mapping. 20.4 Functional description 20.4.1 Single-bit correction events When a single-bit correction event on Memory n is detected, the ERM: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 451: Non-Correctable Error Events
Error Address Register: EARn (if this register is present for the channel). The ERM holds event information only for the last reported event. To clear the record of an event, write 1 to SRx[NCEn] to change its value to 0. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 452: Initialization
2. During the memory's initialization, if the ERM captures information about any ECC error event, clear the corresponding SRx[SBCn] or SRx[NCEn] field that stores the record of the event. 3. Program the applicable CRx[ESCIEn] and CRx[ENCIEn] fields to enable ERM interrupts as desired. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 453: Watchdog Timer (Wdog)
Wait mode is not supported in this device. See Module operation in available power modes for details on available power modes. Table 21-1. WDOG low-power modes Module mode Chip mode Stop Stop, VLPS MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 454: Default Watchdog Timeout
WDOG IRQ . WDOG delayed + RCM delayed WDOG reset. 1. WDOG IRQ will be executed and RCM IRQ will be pending based on the fact that WDOG has lower number. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 455: Introduction
• Optional timeout interrupt to allow post-processing diagnostics • Interrupt request to CPU with interrupt vector for an interrupt service routine (ISR) • Forced reset occurs 128 bus clocks after the interrupt vector fetch. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 456: Block Diagram
Bus Cycle Control Status 16-bit Window Register Disable Protect Bit Write Control 0xD928 UPDATE PRES WIN Figure 21-1. WDOG block diagram 21.3 Memory map and register definition 21.3.1 WDOG register descriptions MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 457 This section describes the function of Watchdog Control and Status Register. NOTE TST is cleared (0:0) on POR only. Any other reset does not affect the value of this field. 21.3.1.2.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 458 11b - ERCLK (external reference clock) Watchdog Enable This write-once bit enables the watchdog counter to start counting. 0b - Watchdog disabled. 1b - Watchdog enabled. Watchdog Interrupt Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 459 This write-once bit enables the watchdog to operate when the chip is in stop mode. 0b - Watchdog disabled in chip stop mode. 1b - Watchdog enabled in chip stop mode. 21.3.1.3 Watchdog Counter Register (CNT) 21.3.1.3.1 Offset Register Offset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 460 All other writes to this register are illegal and force a reset. 21.3.1.3.3 Diagram Bits Reset Bits CNTHIGH CNTLOW Reset 21.3.1.3.4 Fields Field Function 31-16 Reserved — 15-8 High byte of the Watchdog Counter CNTHIGH Low byte of the Watchdog Counter CNTLOW MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 461 TOVALLOW cannot be 0); otherwise, the watchdog always generates a reset. 21.3.1.4.3 Diagram Bits Reset Bits TOVALHIGH TOVALLOW Reset 21.3.1.4.4 Fields Field Function 31-16 Reserved — Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 462 The WIN register value must be less than the TOVAL register value. 21.3.1.5.3 Diagram Bits Reset Bits WINHIGH WINLOW Reset 21.3.1.5.4 Fields Field Function 31-16 Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 463: Functional Description
An optional fixed prescaler for all clock sources allows for longer timeout periods. When CS[PRES] is set, the clock source is prescaled by 256 before clocking the watchdog counter. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 464: Watchdog Refresh Mechanism
In addition, if window mode is used, software must not start the refresh sequence until after the time value set in the WIN register. See the following figure. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 465 The refresh write sequence can be • either two 16-bit writes ( 0xA602, 0xB480) or four 8-bit writes (0xA6, 0x02, 0xB4, 0x80) if WDOG_CS[CMD32EN] is 0; • one 32-bit write (0xB480_A602) if WDOG_CS[CMD32EN] is 1. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 466: Configuring The Watchdog
• Conversely, if CS[UPDATE] remains 0, the only way to reconfigure the watchdog is by initiating a reset. The unlock sequence is similar to the refresh sequence but uses different values. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 467: Using Interrupts To Delay Resets
WDOG logic loses its clock (the bus clock) and can no longer monitor the counter. If the watchdog counter overflows twice in succession (without an intervening reset), the backup reset function takes effect and generates a reset. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 468: Functionality In Debug And Low-Power Modes
Using this test feature reduces the test time to 512 clocks (not including overhead, such as user configuration and reset vector fetches). To further speed testing, use a faster clock (such as the bus clock) for the counter reference. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 469 As an ongoing test when using the default clock source, software can periodically read the CNT register to ensure the counter is being incremented. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 470: Application Information
DisableInterrupts; // disable global interrupt WDOG_CS &= ~WDOG_CS_EN_MASK; // disable watchdog WDOG_TOVAL= 0xFFFF; while(WDOG_CS[ULK]); // waiting for lock while(~WDOG_CS[RCS]); // waiting for new configuration to take effect EnableInterrupts; // enable global interrupt MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 471: Configure Watchdog
To refresh the watchdog and reset the watchdog counter to zero, a refresh sequence is required. The code snippet below shows an example for 32-bit write. DisableInterrupts; // disable global interrupt WDOG_CNT = 0xB480A602; // refresh watchdog EnableInterrupts; // enable global interrupt MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 472 Application Information MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 473: Cyclic Redundancy Check (Crc)
CRC data register via 8-bit accesses. In this case, the user's software must perform the bytewise transpose function. • Option for inversion of final CRC result • 32-bit CPU register programming interface MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 474: Block Diagram
It resumes after the clock is enabled or via the system reset for exiting the low-power mode. Clock gating for this module is dependent on the MCU. 22.3 Memory map and register descriptions 22.3.1 CRC register descriptions MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 475 CRC mode, the CRC result is available in the LU and LL fields. In 32-bit CRC mode, all fields contain the result. Reads of this register at any time return the intermediate CRC value, provided the CRC module is configured. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 476 When CTRL[WAS] is 1, values written to this field are part of the seed value. When CTRL[WAS] is 0, data written to this field is used for CRC checksum generation. 22.3.1.3 CRC Polynomial register (GPOLY) 22.3.1.3.1 Offset Register Offset GPOLY MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 477 Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not writable in 16-bit CRC mode (CTRL[TCRC] is 0). 15-0 Low Polynominal Half-word Writable and readable in both 32-bit and 16-bit CRC modes. 22.3.1.4 CRC Control register (CTRL) 22.3.1.4.1 Offset Register Offset CTRL MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 478 When asserted, a value written to the CRC data register is considered a seed value. When deasserted, a value written to the CRC data register is taken as data for CRC computation. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 479: Functional Description
1. Clear CRC_CTRL[TCRC] to enable 16-bit CRC mode. 2. Program the transpose and complement options in the CTRL register as required for the CRC calculation. See Transpose feature CRC result complement for details. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 480: Transpose Feature
The user software has the option to configure each transpose operation separately, as desired by the CRC standard. The data is transposed on the fly while being read or written. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 481 3. CTRL[TOT] or CTRL[TOTR] is 10. Both bits in bytes and bytes are transposed. reg[31:0] becomes = {reg[0:7], reg[8:15],reg[16:23], reg[24:31]} Figure 22-3. Transpose type 10 4. CTRL[TOT] or CTRL[TOTR] is 11. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 482: Crc Result Complement
CRC data register every time the CRC data register is read. When CTRL[FXOR] is cleared, reading the CRC data register accesses the raw checksum value. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 483: Reset And Boot
This provides software an option to perform a graceful shutdown. The MCU exits reset in RUN mode where the CPU is executing code. See Boot for more details. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 484: Power-On Reset (Por)
During and following a reset, the JTAG pins have their associated input pins configured • TDI as pullup (PU) • TCK as pulldown (PD) • TMS as pullup and associated output pin configured as: • TDO with no pull-down or pull-up MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 485 Besides LVD operation, the device also supports LVR(Low Voltage Reset) operation. If the supply voltage falls below the reset trip point (VLVR), a system reset will be generated. LVR system is enabled in all modes. LVDRE has effect on LVD operation only. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 486 SPLL also flags LOL in case if the reference to SPLL goes faulty. So while using SPLL, any failure in reference clock source, i.e., SOSC might lead to either LOC or LOL event. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 487 0. Writing 1 to the core hold reset bit in the MDM-AP control register holds the core in reset as the rest of the chip comes out of system reset. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 488: Mcu Resets
The core comes out of reset after one cycle of chip reset. The core can be held in reset using the core hold reset bit in the MDM-AP control register as the rest of the chip comes out of system reset. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 489: Reset Pin
CDBGRSTREQ does not reset the debug-related registers within these modules: • CM4 core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR) • FPB • DWT • ITM • NVIC • Crossbar bus switch • Private peripheral bus MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 490: Boot
To configure for alternate settings, program the appropriate bits in the NVM option byte. The new settings take effect on subsequent POR and any system reset. For more details on programming the option byte, see the flash memory chapter. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 491: Boot Sequence
SCG is enabled in its default clocking mode. 2. Required clocks are enabled (core clock, system clock, flash clock, and any bus clocks that do not have clock gate control reset to disabled). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 492 FlexNVM data. This data is not available immediately out of reset and the system should not access this data until the flash controller completes this initialization step as indicated by the EEERDY flag. Subsequent system resets follow this same reset flow. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 493: Reset Control Module (Rcm)
Information found here describes the registers of the Reset Control Module (RCM). The RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 494: Reset Memory Map And Register Descriptions
MINOR FEATURE Reset RCM_VERID field descriptions Field Description 31–24 Major Version Number MAJOR This read only field returns the major version number for the specification. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 495 Minor Version Number MINOR This read only field returns the minor version number for the specification. FEATURE Feature Specification Number This read only field returns the feature set number. 0x0003 Standard feature set. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 496: Parameter Register (Rcm_Param)
Description 31–17 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Existence of SRS[CORE1] status indication feature ECORE1 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 497 Existence of SRS[POR] status indication feature EPOR This static bit states whether or not the feature is available on the device. The feature is not available. The feature is available. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 498: System Reset Status Register (Rcm_Srs)
Note that multiple flags can be set if multiple reset events occur at the same time. The reset state of these bits depends on what caused the MCU to reset. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 499 This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Stop Acknowledge Error SACKERR Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 500 Reset caused by external reset pin Watchdog WDOG Indicates a reset has been caused by the watchdog timer timing out. This reset source can be blocked by disabling the watchdog. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 501: Reset Pin Control Register (Rcm_Rpc)
NOTE The bus clock filter is reset when disabled or when entering stop mode. The LPO filter is reset when disabled. Address: 4007_F000h base + Ch offset = 4007_F00Ch Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 502 Selects how the reset pin filter is enabled in run and wait modes. All filtering disabled Bus clock filter enabled for normal operation LPO clock filter enabled for normal operation Reserved MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 503: Sticky System Reset Status Register (Rcm_Ssrs)
This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Sticky Stop Acknowledge Error SSACKERR Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 504 Sticky Watchdog SWDOG Indicates a reset has been caused by the watchdog timer timing out. This reset source can be blocked by disabling the watchdog. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 505: System Reset Interrupt Enable Register (Rcm_Srie)
The SRS updates only after the system reset occurs. NOTE The reset delay feature requires the LPO clock to remain active. NOTE This register is reset on Chip POR only, it is unaffected by other reset types. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 506 NOTE: The LOCKUP bit is useful only in devices with more than one core processor. Interrupt disabled. Interrupt enabled. JTAG generated reset JTAG Interrupt disabled. Interrupt enabled. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 507 Reset Delay Time Configures the maximum reset delay time from when the interrupt is asserted and the system reset occurs. 10 LPO cycles 34 LPO cycles 130 LPO cycles 514 LPO cycles MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 508 Reset memory map and register descriptions MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 509: Clock Distribution
Clock selection for most modules is controlled by the PCC module. 25.2 High level clocking diagram The following diagram shows the high-level clocking architecture and various clock sources for this device. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 510: Clock Definitions
2 QSPI clocks are applicable for WCT1016S only and Reserved for others. See QuadSPI clicking diagram in table 'Peripheral module clocking' Figure 25-1. Clocking diagram 25.3 Clock definitions The following table describes clocks shown in Figure 25-1 and other sections of this document. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 511 (÷ 1, 2, 4, 8, 16, 32, 64, or This should be configured to 40 MHz output disabled) or less in RUN mode and 56 MHz or less in HSRUN mode. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 512: Internal Clocking Requirements
80 MHz in normal RUN mode (but not configured to be less than BUS_CLK). • BUS_CLK frequency must be programmed to 56 MHz or less in HSRUN, 48 MHz or less in RUN(when using PLL as system clock source maximum bus clock MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 513 Option 3: Normal RUN (with VCO_CLK = 256 MHz, SPLL_CLK = 128 MHz), using the following Memory Map/Register Definition register settings: 1. Default configuration after reset. FIRC_CLK = 48 MHz. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 514 • SCG_HCCR[DIVBUS] = 0001b • SCG_HCCR[DIVSLOW] = 0010b Table 25-6. High Speed RUN 80 example (mode used by QuadSPI only) Clock Frequency CORE_CLK 80 MHz Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 515 Must be integer divide of the CORE_CLK. The core clock to flash clock ratio is limited to a max value of 8. NOTE All frequencies listed in table above are maximum for VLPR mode. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 516: Clock Divider Values After Reset
25.4.4 VLPR/VLPS mode entry When entering VLPR/VLPS mode, the system clock should be SIRC. The FIRC, SOSC and SPLL must be disabled by software in RUN mode before making any mode transition. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 517: Clock Gating
OSC; SYS_CLK must be >1.5x the protocol SYS_CLK, clock; while FlexCAN SYS_CLK — SOSCDIV2_CLK synchronous operation (when protocol clock is selected to SYS_CLK) can be Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 518 — governed by BUS_CLK Maximum frequency BUS_CLK — — governed by BUS_CLK Maximum frequency BUS_CLK — LPO128K_CLK governed by BUS_CLK Maximum BUS_CLK — — frequency Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 519 — governed by SYS_CLK Memory Modules Maximum frequency FTFC FLASH_CLK — — governed by FLASH_CLK Maximum frequency System RAM SYS_CLK — — governed by SYS_CLK Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 520 • SIRC and LPO_CLK are the valid clock sources for VLP* modes. • SPLL and FIRC are the valid clock sources for HSRUN mode. The following table summarizes the clocks that can be used by each of the modules. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 521 (where 1b = clock enabled) PCC module DMAMUX to module BUS_CLK CMP0 Clock gate enable PCC_<module>[CGC] (where 1b = clock enabled) GPIO GPIO SYS_CLK GPIO bus interface clock Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 522 (where 1 = clock enabled) CHI Clock SOSCDIV2_CLK PE Clock SYS_CLK CAN_CTRL1[CLKSRC] SIM module MSCM SYS_CLK to module Clock gate enable SIM_PLATCGC[CGC<module>] (where 1b = clock enabled) Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 523 WDOG_CS[CLK] bus_clk LPO128K_CLK LPO_CLK internal LPO clk LPO32K_CLK WDOG clock SOSC_CLK internal clk LPO1K_CLK SIRC_CLK external clk SIM_LPOCLKS[LPOCLKSEL] SIM/PMC/TRGMUX TRGMUX BUS_CLK bus interface clock Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 524 Reserved RCM_RPC[RSTFLTSRW] System RAM System RAM SYS_CLK memory clock FTFC PCC module FTFC FLASH_CLK Clock gate enable PCC_FTFC[CGC] (where 1 = clock enabled) Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 525 FTM_CLK is controlled by PCC module and could run up to CPU frequency and provide higher resolution for the FTM timer. The fixed frequency clock is a fixed clock driven by RTC_CLK. SIM_LPOCLKS[RTCCLKSEL] is used to select the RTC_CLK source. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 526 NOTE: The clock selected must remain enabled if the LPTMR is to continue operating in all required low power modes. TPIU Trace clk TPIU Core clk Divider SIM_CLKDIV4[3:0] QuadSPI MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 527 PCC_QSPI[CGC] (where 1 = clock enabled) NOTE: Clock gate enable: SIM_MISCTRL0[QSPI_CLK_SEL] For programmable divider configuration, see QuadSPI_SOCCR[SOCCFG] implementation NOTE While changing peripheral clock source/divider configuration, the corresponding module should be disabled. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 528 Module clocks MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 529: System Clock Generator (Scg)
• 11 High frequency range selected for the crystal oscillator of 8 MHz to 40 MHz. 3. SCG_SIRCCFG[RANGE] • 0 Reserved • 1 Slow IRC high range clock (8 MHz ) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 530: Oscillator And Spll Guidelines
26.1.4 System clock and clock monitor requirement 1. System clock source SOSC/SPLL requirement: Ensure below sequence is followed while switching system clock to SOSC/SPLL: a. System clock source (SOSC/SPLL) is enabled MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 531: Introduction
• System Phase-locked loop (SPLL): • Voltage-controlled oscillator (VCO) • External reference clock is used as the PLL source • Modulo VCO frequency divider • Phase/Frequency detector • Integrated loop filter MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 532: Memory Map/Register Definition
Read accesses may be performed in both supervisor and user mode. NOTE For any writeable SCG registers, only 32-bit writes are allowed. 8-bit or 16-bit writes will result in transfer errors. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 533: Version Id Register (Scg_Verid)
System PLL Configuration Register (SCG_SPLLCFG) 0000_0000h 26.3.1 Version ID Register (SCG_VERID) Note: Writing to this register will result in a transfer error. Address: 4006_4000h base + 0h offset = 4006_4000h VERSION Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 534: Parameter Register (Scg_Param)
Reserved and always has the value 0 when read. CLKPRES[0] Reserved CLKPRES[1]=1System OSC (SOSC) is present CLKPRES[2]=1Slow IRC (SIRC) is present CLKPRES[3]=1Fast IRC (FIRC) is present CLKPRES[6]=1System PLL (SPLL) is present MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 535: Clock Status Register (Scg_Csr)
DIVCORE If SPLL is selected as system clock source, the maximum DIVCORE value is Divide-by-4. 0000 Divide-by-1 0001 Divide-by-2 0010 Divide-by-3 0011 Divide-by-4 0100 Divide-by-5 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 536 Slow Clock Divide Ratio 0000 Divide-by-1 0001 Divide-by-2 0010 Divide-by-3 0011 Divide-by-4 0100 Divide-by-5 0101 Divide-by-6 0110 Divide-by-7 0111 Divide-by-8 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 537: Run Clock Control Register (Scg_Rccr)
0000 Reserved 0001 System OSC (SOSC_CLK) 0010 Slow IRC (SIRC_CLK) 0011 Fast IRC (FIRC_CLK) 0100 Reserved 0101 Reserved 0110 System PLL (SPLL_CLK) 0111 Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 538 1001 Divide-by-10 1010 Divide-by-11 1011 Divide-by-12 1100 Divide-by-13 1101 Divide-by-14 1110 Divide-by-15 1111 Divide-by-16 DIVSLOW Slow Clock Divide Ratio 0000 Divide-by-1 0001 Divide-by-2 0010 Divide-by-3 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 539: Vlpr Clock Control Register (Scg_Vccr)
Selects the clock source generating the system clock in VLPR mode. Attempting to select a clock that is not valid will be ignored. Selects the clock source generating the system clock. Selecting a different clock Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 540 Bus Clock Divide Ratio DIVBUS 0000 Divide-by-1 0001 Divide-by-2 0010 Divide-by-3 0011 Divide-by-4 0100 Divide-by-5 0101 Divide-by-6 0110 Divide-by-7 0111 Divide-by-8 1000 Divide-by-9 1001 Divide-by-10 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 541: Hsrun Clock Control Register (Scg_Hccr)
HSRUN, new system clock divide ratios will not take affect until new clock source is valid. Address: 4006_4000h base + 1Ch offset = 4006_401Ch DIVCORE Reserved DIVBUS DIVSLOW Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 542 This read-only field is reserved and always has the value 0. 7–4 Bus Clock Divide Ratio DIVBUS 0000 Divide-by-1 0001 Divide-by-2 0010 Divide-by-3 0011 Divide-by-4 0100 Divide-by-5 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 543: Scg Clkout Configuration Register (Scg_Clkoutcnfg)
26.3.7 SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG) This register controls which SCG clock source is selected to be ported out to the CLKOUT pin. Address: 4006_4000h base + 20h offset = 4006_4020h CLKOUTSEL Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 544 Fast IRC (FIRC_CLK) 0100 Reserved 0101 Reserved 0110 System PLL (SPLL_CLK) 0111 Reserved 1111 Reserved Reserved This field is reserved. This read-only field is reserved and always has the value 0. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 545: System Osc Control Status Register (Scg_Sosccsr)
This flag is reset on Chip POR only, software can also clear this flag by writing a logic one. System OSC Clock Monitor is disabled or has not detected an error System OSC Clock Monitor is enabled and detected an error Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 546 This field is reserved. Software should write 0 to these bits to maintain compatibility. System OSC Enable SOSCEN If this bit written during clock switching, it should be read back and confirmed before proceeding. System OSC is disabled System OSC is enabled MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 547: System Osc Divide Register (Scg_Soscdiv)
System OSC Clock Divide 1 Clock divider 1 for System OSC. Used to generate the clock source for modules that need an asynchronous clock source. Output disabled Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 548: System Oscillator Configuration Register (Scg_Sosccfg)
Selects the frequency range for the system crystal oscillator (OSC) See chip-specific information for supported crystal oscillator ranges. Reserved Low frequency range selected for the crystal oscillator Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 549 OSC (SOSC) into the SCG, thus either the crystal oscillator or from an external clock input External reference clock selected Internal crystal oscillator of OSC selected. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 550: Slow Irc Control Status Register (Scg_Sirccsr)
Slow IRC is not enabled or clock is not valid Slow IRC is enabled and output clock is valid Lock Register This bit field can be cleared/set at any time. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 551: Slow Irc Divide Register (Scg_Sircdiv)
This bit field is reserved. Software should write 0 to this bit field to maintain compatibility. 15–11 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 10–8 Slow IRC Clock Divide 2 SIRCDIV2 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 552: Slow Irc Configuration Register (Scg_Sirccfg)
The SIRCCFG register cannot be changed when the slow IRC clock is enabled. When the slow IRC clock is enabled, writes to this register are ignored, and there is no transfer error. Address: 4006_4000h base + 208h offset = 4006_4208h Reset Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 553: Fast Irc Control Status Register (Scg_Firccsr)
Slow IRC low range clock (2 MHz) Slow IRC high range clock (8 MHz ) 26.3.14 Fast IRC Control Status Register (SCG_FIRCCSR) Address: 4006_4000h base + 300h offset = 4006_4300h Reset Reserved Reserved Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 554 This field is reserved. Fast IRC Enable FIRCEN If this bit written during clock switching, it should be read back and confirmed before proceeding. Fast IRC is disabled Fast IRC is enabled MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 555: Fast Irc Divide Register (Scg_Fircdiv)
Clock divider 1 for Fast IRC. Used to generate the clock source for modules that need an asynchronous clock source. Output disabled Divide by 1 Divide by 2 Divide by 4 Divide by 8 Divide by 16 Divide by 32 Divide by 64 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 556: Fast Irc Configuration Register (Scg_Firccfg)
This read-only field is reserved and always has the value 0. RANGE Frequency Range See chip-specific information for supported frequency ranges. Fast IRC is trimmed to 48 MHz Reserved Reserved Reserved MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 557: System Pll Control Status Register (Scg_Spllcsr)
System OSC is selected as its source and SOSCERR has set. System PLL Selected SPLLSEL System PLL is not the system clock source System PLL is the system clock source Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 558 As the device exits reset, the SCG_RCCR register should be configured as per the supported frequency ranges of the device BEFORE enabling the SPLL (SPLLEN =1). System PLL is disabled System PLL is enabled MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 559: System Pll Divide Register (Scg_Splldiv)
Clock divider 1 for System PLL. Used to generate the clock source for modules that need an asynchronous clock source. Clock disabled Divide by 1 Divide by 2 Divide by 4 Divide by 8 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 560: System Pll Configuration Register (Scg_Spllcfg)
SCG_SPLLCFG field descriptions Field Description 31–21 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 20–16 System PLL Multiplier MULT Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 561 Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved This field is reserved. Software should write 0 to this bit to maintain compatibility. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 562: Functional Description
SCG Valid Mode Transitions Reset RUN Valid SCG Modes FIRC SOSC SIRC High Speed Very Low Power VLPRUN Valid HSRUN Valid SCG Modes SCG Modes FIRC SIRC Figure 26-1. SCG Valid Mode Transition Diagram MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 563 • RUN MODE: 0011 is written to RCCR[SCS]. HSRUN MODE: 0011 is written to HCCR[SCS]. • FIRCEN = 1 • FIRCVLD = 1 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 564 SIRCCLK is available in Normal Stop and VLPS mode when all the following conditions become true: • SIRCCSR[SIRCEN] = 1 • SIRCCSR[SIRCSTEN] = 1 • SIRCCSR[SIRCLPEN] = 1 in VLPS MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 565: Chip-Specific Pcc Information
Registers for instances unavailable in a particular variant are reserved. 27.2 Introduction The Peripheral Clock Control (PCC) module provides clock control and configuration for on-chip peripherals. Each peripheral has its own clock control and configuration register. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 566: Features
= Not all module functional clocks have a divider or an external clock option. Interface clock = Internal bus interface clock for module registers and logic Functional clock = Clock for module applications (Not all modules have functional clocks.) Figure 27-1. PCC Block Diagram MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 567: Functional Description
27.6 PCC register descriptions 27.6.1 PCC Memory map PCC base address: 4006_5000h Offset Register Width Access Reset value (In bits) PCC FTFC Register (PCC_FTFC) C000_0000h Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 568 8000_0000h 1BCh PCC FTM5 Register (PCC_FTM5) 8000_0000h 1C0h PCC FTM6 Register (PCC_FTM6) 8000_0000h 1C4h PCC FTM7 Register (PCC_FTM7) 8000_0000h 1CCh PCC CMP0 Register (PCC_CMP0) 8000_0000h 1D8h PCC QSPI Register (PCC_QSPI) 8000_0000h MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 569: Pcc Ftfc Register (Pcc_Ftfc)
This read/write bit enables the interface clock for the peripheral, allowing access to the module's registers. It also controls whether the clock selection and divider options can be modified. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 570: Pcc Dmamux Register (Pcc_Dmamux)
This read-only bit field is reserved and always has the value 0. — 27.6.3 PCC DMAMUX Register (PCC_DMAMUX) 27.6.3.1 Offset Register Offset PCC_DMAMUX 27.6.3.2 Function This register is for the DMAMUX module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 571 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 572: Pcc Flexcan0 Register (Pcc_Flexcan0)
This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Gate Control Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 573: Pcc Flexcan1 Register (Pcc_Flexcan1)
This read-only bit field is reserved and always has the value 0. — 27.6.5 PCC FlexCAN1 Register (PCC_FlexCAN1) 27.6.5.1 Offset Register Offset PCC_FlexCAN1 27.6.5.2 Function This register is for the FlexCAN1 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 574 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 575: Pcc Ftm3 Register (Pcc_Ftm3)
This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Gate Control Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 576: Pcc Adc1 Register (Pcc_Adc1)
This read-only bit field is reserved and always has the value 0. — 27.6.7 PCC ADC1 Register (PCC_ADC1) 27.6.7.1 Offset Register Offset PCC_ADC1 27.6.7.2 Function This register is for the ADC1 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 577 001b - Clock option 1 010b - Clock option 2 011b - Clock option 3 100b - Clock option 4 101b - Clock option 5 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 578: Pcc Flexcan2 Register (Pcc_Flexcan2)
This read-only bit field is reserved and always has the value 0. — 27.6.8 PCC FlexCAN2 Register (PCC_FlexCAN2) 27.6.8.1 Offset Register Offset PCC_FlexCAN2 27.6.8.2 Function This register is for the FlexCAN2 module. 27.6.8.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 579: Pcc Lpspi0 Register (Pcc_Lpspi0)
This read-only bit field is reserved and always has the value 0. — 27.6.9 PCC LPSPI0 Register (PCC_LPSPI0) 27.6.9.1 Offset Register Offset PCC_LPSPI0 27.6.9.2 Function This register is for the LPSPI0 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 580 001b - Clock option 1 010b - Clock option 2 011b - Clock option 3 100b - Clock option 4 101b - Clock option 5 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 581: Pcc Lpspi1 Register (Pcc_Lpspi1)
This read-only bit field is reserved and always has the value 0. — 27.6.10 PCC LPSPI1 Register (PCC_LPSPI1) 27.6.10.1 Offset Register Offset PCC_LPSPI1 27.6.10.2 Function This register is for the LPSPI1 module. 27.6.10.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 582: Pcc Lpspi2 Register (Pcc_Lpspi2)
This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.11 PCC LPSPI2 Register (PCC_LPSPI2) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 583 0b - Clock disabled. The current clock selection and divider options are not locked and can be modified. 1b - Clock enabled. The current clock selection and divider options are locked and cannot be modified. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 584: Pcc Pdb1 Register (Pcc_Pdb1)
This read-only bit field is reserved and always has the value 0. — 27.6.12 PCC PDB1 Register (PCC_PDB1) 27.6.12.1 Offset Register Offset PCC_PDB1 27.6.12.2 Function This register is for the PDB1 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 585 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 586: Pcc Crc Register (Pcc_Crc)
This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Gate Control Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 587: Pcc Pdb0 Register (Pcc_Pdb0)
This read-only bit field is reserved and always has the value 0. — 27.6.14 PCC PDB0 Register (PCC_PDB0) 27.6.14.1 Offset Register Offset PCC_PDB0 27.6.14.2 Function This register is for the PDB0 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 588 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 589: Pcc Lpit Register (Pcc_Lpit)
This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Gate Control Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 590: Pcc Ftm0 Register (Pcc_Ftm0)
This read-only bit field is reserved and always has the value 0. — 27.6.16 PCC FTM0 Register (PCC_FTM0) 27.6.16.1 Offset Register Offset PCC_FTM0 27.6.16.2 Function This register is for the FTM0 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 591 001b - Clock option 1 010b - Clock option 2 011b - Clock option 3 100b - Clock option 4 101b - Clock option 5 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 592: Pcc Ftm1 Register (Pcc_Ftm1)
This read-only bit field is reserved and always has the value 0. — 27.6.17 PCC FTM1 Register (PCC_FTM1) 27.6.17.1 Offset Register Offset PCC_FTM1 27.6.17.2 Function This register is for the FTM1 module. 27.6.17.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 593: Pcc Ftm2 Register (Pcc_Ftm2)
This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.18 PCC FTM2 Register (PCC_FTM2) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 594 0b - Clock disabled. The current clock selection and divider options are not locked and can be modified. 1b - Clock enabled. The current clock selection and divider options are locked and cannot be modified. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 595: Pcc Adc0 Register (Pcc_Adc0)
This read-only bit field is reserved and always has the value 0. — 27.6.19 PCC ADC0 Register (PCC_ADC0) 27.6.19.1 Offset Register Offset PCC_ADC0 27.6.19.2 Function This register is for the ADC0 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 596 010b - Clock option 2 011b - Clock option 3 100b - Clock option 4 101b - Clock option 5 110b - Clock option 6 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 597: Pcc Rtc Register (Pcc_Rtc)
This read-only bit field is reserved and always has the value 0. — 27.6.20 PCC RTC Register (PCC_RTC) 27.6.20.1 Offset Register Offset PCC_RTC 27.6.20.2 Function This register is for the RTC module. 27.6.20.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 598: Pcc Lptmr0 Register (Pcc_Lptmr0)
This read-only bit field is reserved and always has the value 0. — 27.6.21 PCC LPTMR0 Register (PCC_LPTMR0) 27.6.21.1 Offset Register Offset PCC_LPTMR0 100h 27.6.21.2 Function This register is for the LPTMR0 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 599 001b - Clock option 1 010b - Clock option 2 011b - Clock option 3 100b - Clock option 4 101b - Clock option 5 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 600: Pcc Porta Register (Pcc_Porta)
101b - Divide by 6. 110b - Divide by 7. 111b - Divide by 8. 27.6.22 PCC PORTA Register (PCC_PORTA) 27.6.22.1 Offset Register Offset PCC_PORTA 124h 27.6.22.2 Function This register is for the PORTA module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 601 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 602: Pcc Portb Register (Pcc_Portb)
This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Gate Control Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 603: Pcc Portc Register (Pcc_Portc)
This read-only bit field is reserved and always has the value 0. — 27.6.24 PCC PORTC Register (PCC_PORTC) 27.6.24.1 Offset Register Offset PCC_PORTC 12Ch 27.6.24.2 Function This register is for the PORTC module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 604 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 605: Pcc Portd Register (Pcc_Portd)
This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Gate Control Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 606: Pcc Porte Register (Pcc_Porte)
This read-only bit field is reserved and always has the value 0. — 27.6.26 PCC PORTE Register (PCC_PORTE) 27.6.26.1 Offset Register Offset PCC_PORTE 134h 27.6.26.2 Function This register is for the PORTE module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 607 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 608: Pcc Flexio Register (Pcc_Flexio)
This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Gate Control Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 609: Pcc Ewm Register (Pcc_Ewm)
This read-only bit field is reserved and always has the value 0. — 27.6.28 PCC EWM Register (PCC_EWM) 27.6.28.1 Offset Register Offset PCC_EWM 184h 27.6.28.2 Function This register is for the EWM module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 610 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 611: Pcc Lpi2C0 Register (Pcc_Lpi2C0)
This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Gate Control Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 612: Pcc Lpi2C1 Register (Pcc_Lpi2C1)
This read-only bit field is reserved and always has the value 0. — 27.6.30 PCC LPI2C1 Register (PCC_LPI2C1) 27.6.30.1 Offset Register Offset PCC_LPI2C1 19Ch 27.6.30.2 Function This register is for the LPI2C1 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 613 001b - Clock option 1 010b - Clock option 2 011b - Clock option 3 100b - Clock option 4 101b - Clock option 5 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 614: Pcc Lpuart0 Register (Pcc_Lpuart0)
This read-only bit field is reserved and always has the value 0. — 27.6.31 PCC LPUART0 Register (PCC_LPUART0) 27.6.31.1 Offset Register Offset PCC_LPUART0 1A8h 27.6.31.2 Function This register is for the LPUART0 module. 27.6.31.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 615: Pcc Lpuart1 Register (Pcc_Lpuart1)
This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.32 PCC LPUART1 Register (PCC_LPUART1) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 616 0b - Clock disabled. The current clock selection and divider options are not locked and can be modified. 1b - Clock enabled. The current clock selection and divider options are locked and cannot be modified. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 617: Pcc Lpuart2 Register (Pcc_Lpuart2)
This read-only bit field is reserved and always has the value 0. — 27.6.33 PCC LPUART2 Register (PCC_LPUART2) 27.6.33.1 Offset Register Offset PCC_LPUART2 1B0h 27.6.33.2 Function This register is for the LPUART2 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 618 010b - Clock option 2 011b - Clock option 3 100b - Clock option 4 101b - Clock option 5 110b - Clock option 6 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 619: Pcc Ftm4 Register (Pcc_Ftm4)
This read-only bit field is reserved and always has the value 0. — 27.6.34 PCC FTM4 Register (PCC_FTM4) 27.6.34.1 Offset Register Offset PCC_FTM4 1B8h 27.6.34.2 Function This register is for the FTM4 module. 27.6.34.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 620: Pcc Ftm5 Register (Pcc_Ftm5)
This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.35 PCC FTM5 Register (PCC_FTM5) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 621 0b - Clock disabled. The current clock selection and divider options are not locked and can be modified. 1b - Clock enabled. The current clock selection and divider options are locked and cannot be modified. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 622: Pcc Ftm6 Register (Pcc_Ftm6)
This read-only bit field is reserved and always has the value 0. — 27.6.36 PCC FTM6 Register (PCC_FTM6) 27.6.36.1 Offset Register Offset PCC_FTM6 1C0h 27.6.36.2 Function This register is for the FTM6 module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 623 010b - Clock option 2 011b - Clock option 3 100b - Clock option 4 101b - Clock option 5 110b - Clock option 6 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 624: Pcc Ftm7 Register (Pcc_Ftm7)
This read-only bit field is reserved and always has the value 0. — 27.6.37 PCC FTM7 Register (PCC_FTM7) 27.6.37.1 Offset Register Offset PCC_FTM7 1C4h 27.6.37.2 Function This register is for the FTM7 module. 27.6.37.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 625: Pcc Cmp0 Register (Pcc_Cmp0)
This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.38 PCC CMP0 Register (PCC_CMP0) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 626 0b - Clock disabled. The current clock selection and divider options are not locked and can be modified. 1b - Clock enabled. The current clock selection and divider options are locked and cannot be modified. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 627: Pcc Qspi Register (Pcc_Qspi)
This read-only bit field is reserved and always has the value 0. — 27.6.39 PCC QSPI Register (PCC_QSPI) 27.6.39.1 Offset Register Offset PCC_QSPI 1D8h 27.6.39.2 Function This register is for the QSPI module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 628 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 629: Memories And Memory Interfaces
Table 28-1. Reference links to related information Topic Related module Reference System memory map See attached MWCT101xS_memory_map.xlsx Clocking System Clock Generator Clock Distribution Arm Cortex-M4 core Arm Cortex-M4F core Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 630: Sram Sizes
No ECC or access error is generated for FlexRAM used as System RAM. The region of size equal to FlexRAM (4 KB) after SRAM_U end address is reserved, but no access error is generated for this region. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 631: Sram Accessibility
The following table illustrates these scenarios. Table 28-4. SRAM simultaneous accesses Core code bus access Core system bus access Non-core bus master access SRAM_L SRAM_U — SRAM_L — SRAM_U — SRAM_U SRAM_L MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 632: Sram Arbitration And Priority Control
Chip Control register (CHIPCTL) and write 1 to them to allow accesses to SRAM. 28.3.5 SRAM access: Behavior of device when in accessing a memory with multi-bit ECC error MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 633 ECC error. CPU gets an ERM interrupt necessary health checks for system (provided it is enabled). level communication to external world, as ECC errors are not expected and can refer to unexpected event. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 634 SRAM configuration MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 635: Chip-Specific Lmem Information
For each WCT101xS product's SRAM sizes and other details, see SRAM sizes. 29.2 Introduction The Local Memory Controller provides the processor with tightly-coupled processor- local memories and bus paths to all slave memory spaces. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 636: Block Diagram
• Two output ports are the CCM (Core Code Master) bus used for PC accesses that do not hit the PC cache or SRAM_L or are non-cacheable and the CSM (Core System Master) bus used for PS references that do not hit the SRAM_U. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 637: Cache Features
(for example, sequential instruction execution or usage of a data structure). • Temporal locality — An access to an area of memory is likely to be repeated within a short time period (for example, execution of a code loop). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 638 2. Non-cacheable — access to address spaces with this cache mode are not cacheable. These accesses bypass the cache and access the output bus. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 639 Cache line control register (PCCLCR) 0000_0000h Cache search address register (PCCSAR) 0000_0000h Cache read/write value register (PCCCVR) 0000_0000h Cache regions mode register (PCCRMR) AA0F_A000h 29.3.1.2 Cache control register (PCCCR) 29.3.1.2.1 Offset Register Offset PCCCR MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 640 1b - When setting the GO bit, invalidate all lines in way 0. 23-4 Reserved — Forces no allocation on cache misses (must also have PCCR2 asserted) Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 641 If a physical address is specified, both ways of the cache are searched, and the command is only performed on the way which hits. 29.3.1.3.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 642 Selects tag or data for search and read or write commands. 0b - Data 1b - Tag Reserved — Way select WSEL Selects the way for line commands. 0b - Way 0 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 643 29.3.1.4.2 Function The CSAR register is used to define the explicit cache address or the physical address for line-sized commands specified in the CLCR[LADSEL] bit. 29.3.1.4.3 Diagram Bits PHYADDR Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 644 29.3.1.5 Cache read/write value register (PCCCVR) 29.3.1.5.1 Offset Register Offset PCCCVR 29.3.1.5.2 Function The CCVR register is used to source write data or return read data for the commands specified in the CLCR register. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 645 After a region is demoted, its cache mode can only be raised by a reset, which returns it to its default state. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 646 10b - Write-through 11b - Write-back 27-26 Region 2 mode Controls the cache mode for region 2 00b - Non-cacheable 01b - Non-cacheable 10b - Write-through Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 647 00b - Non-cacheable 01b - Non-cacheable 10b - Write-through 11b - Write-back 11-10 Region 10 mode Controls the cache mode for region 10 00b - Non-cacheable Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 648: Functional Description
10b - Write-through 11b - Write-back 29.4 Functional Description 29.4.1 LMEM Function The Local Memory Controller receives the following requests: • Core master bus requests on the Processor Code (PC) bus, MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 649: Sram Function
All LMEM backdoor port accesses are for the SRAM controller. These accesses go to the SRAM_L or the SRAM_U depending on their specific address. 29.4.2 SRAM Function 29.4.2.1 SRAM Configuration The figure below shows how the SRAM controller is configured. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 650 • SRAM_U — Accessible by the system bus of the core and by the backdoor port. The backdoor port makes the SRAM accessible to the non-core bus masters (such as DMA). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 651: Cache Function
4 KBytes for the Code Cache. The cache has 32-bit address and data paths and a 16-byte line size. The cache tags and data storage use single- port, synchronous RAMs. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 652: Cache Control
29.4.4.1 Cache set commands The cache set commands may operate on: • all of way 0, • all of way 1, or • all of both ways (complete cache). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 653 After a reset, complete an invalidate cache command before using the cache. It is possible to combine the cache invalidate command with the cache enable. That is, setting CCR to 0x8500_0001 will invalidate the cache and enable the cache. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 654 Clear by cache address and way Search by physical address Invalidate by physical address Push by physical address Clear by physical address Write by cache address and way Reserved, NOP Reserved, NOP Reserved, NOP Reserved, NOP MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 655 For line commands with physical addresses, this information is read on a hit before the line command action is performed from the hit cache line or has initial valid bit MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 656 For line commands, CLCR[TDSEL] selects between tag and data. If the line command used a physical address and missed, the data is don't care. For write commands, the CCVR holds the write data. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 657: Chip-Specific Mscm Information
The following table shows these reset values for each product. Table 30-1. MSCM register reset values Register WCT1014S WCT1015S WCT1016S CPxCFG2 0701_0701 0801_0801 0901_0901 CP0CFG2 0701_0701 0801_0801 0901_0901 OCMDR0 CA08_9000 CA08_9000 DC08_9000 OCMDR1 C706_B000 CA08_B000 CA08_B000 OCMDR2 C304_D000 C304_D000 C304_D000 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 658: Overview
Once the core has fetched the needed reset vector(s), it is expected that core and system configuration information is read from a globally-accessible slave peripheral that properly converts the information into more appropriate values. More specifically, the MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 659: Mscm Memory Map/Register Definition
Defines the configuration information for processor 0 (CP0). This region is accessible to any bus master. Attempted user mode or write accesses are terminated with an error. 30.4.2 MSCM register descriptions MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 660 The 32-bit response includes 3 ASCII characters that define the CPU type, along with a byte that defines the logical revision number. The logical revision number follows Arm’s rYpZ nomenclature. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 661 This read-only field defines the processor revision for CPUx: 0x00 corresponds to the r0p0 core release. 0x01 corresponds to the r0p1 core release. 30.4.2.3 Processor X Number Register (CPxNUM) 30.4.2.3.1 Offset Register Offset CPxNUM MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 662 Processor x Number This zero-filled word defines the logical processor number for CPUx If single core configuration, then CPN = 0 30.4.2.4 Processor X Master Register (CPxMASTER) 30.4.2.4.1 Offset Register Offset CPxMASTER MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 663 Field Function 31-6 Reserved — Processor x Physical Master Number PPMN This read-only field defines the physical bus master number for CPUx. PPMN = 0x00 30.4.2.5 Processor X Count Register (CPxCOUNT) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 664 Processor Count PCNT This read-only field defines the processor count for the chip configuration: PCNT = 00 (Single Core) 30.4.2.6 Processor X Configuration Register 0 (CPxCFG0) 30.4.2.6.1 Offset Register Offset CPxCFG0 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 665 • if a 32 Kbyte Instruction Cache, then ICSZ = 0x07 • if a 64 Kbyte Instruction Cache, then ICSZ = 0x08 23-16 Level 1 Instruction Cache Ways ICWY Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 666 Reset values for the Processor X Configuration Register 1: • For CPU0 - CPxCFG1 = 0x00000000 • If the read access is not from a CPU, then the value read is 0x00000000 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 667 This read-only field provides the number of cache ways for the Instruction Cache. L2WY=0x00 indicates not present. 15-0 Reserved — 30.4.2.8 Processor X Configuration Register 2 (CPxCFG2) 30.4.2.8.1 Offset Register Offset CPxCFG2 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 668 • if a 64 Kbyte TCML, then TMLSZ = 0x08 • if a 128 Kbyte TCML, then TMLSZ = 0x09 23-16 Reserved. — 15-8 Tightly-coupled Memory Upper Size Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 669 Reset values for the Processor X Configuration Register 3: • For CPU0 - CPxCFG3 = 0x00000101 • If the read access is not from a CPU, then the value read is 0x00000000 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 670 1b - MMU support is included. Jazelle support This field indicates if Jazelle hardware is supported in the processor. 0b - Jazelle support is not included. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 671 ASCII characters defining the CPU type, along with a byte defining the logical revision number. The logical revision number follows Arm’s rYpZ nomenclature. 30.4.2.10.3 Diagram Bits PERSONALITY Reset Bits PERSONALITY RYPZ Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 672 30.4.2.11 Processor 0 Number Register (CP0NUM) 30.4.2.11.1 Offset Register Offset CP0NUM 30.4.2.11.2 Function The register provides the logical processor number of Processor 0. The logical processor number is always 0. 30.4.2.11.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 673 30.4.2.12.2 Function The register provides the physical bus master number of Processor 0. 30.4.2.12.3 Diagram Bits Reset Bits PPMN Reset 30.4.2.12.4 Fields Field Function 31-6 Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 674 Bits Reset Bits PCNT Reset 30.4.2.13.4 Fields Field Function 31-2 Reserved — Processor Count PCNT This read-only field defines the processor count for the chip configuration: PCNT = 00 (Single Core) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 675 • if a 512 byte Instruction Cache, then ICSZ = 0x01 • if a 1 Kbyte Instruction Cache, then ICSZ = 0x02 • if a 2 Kbyte Instruction Cache, then ICSZ = 0x03 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 676 30.4.2.15.2 Function The CP0CFG1 register provides information on CPU0 Level 2 cache (if present). Access: Privileged read-only NOTE Reset values for the Processor 0 Configuration Register 1: • CP0CFG1 = 0x00000000 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 677 This read-only field provides the number of cache ways for the Instruction Cache. L2WY=0x00 indicates not present. 15-0 Reserved — 30.4.2.16 Processor 0 Configuration Register 2 (CP0CFG2) 30.4.2.16.1 Offset Register Offset CP0CFG2 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 678 This field provides an encoded value of the tightly-coupled local memory upper size. The capacity of the (8+TMUSZ) memory is expressed as Size [bytes] = 2 , where TMUSZ is non-zero; a TMUSZ = 0 indicates the memory is not present. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 679 30.4.2.17.2 Function The CP0CFG3 register provides information on Processor 0 options. NOTE Reset values for the Processor 0 Configuration Register 3: • CP0CFG3 = 0x00000101 30.4.2.17.3 Diagram Bits Reset Bits Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 680 Floating Point Unit This field indicates if hardware support for floating point capabilities are supported in the processor. 0b - FPU support is not included. 1b - FPU support is included. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 681 The following table describes the OCMDRn reset values and the associated memory type: OCMDRn Reset Value On-Chip Memory Type OCMDR0 0xDC089000 Program Flash OCMDR1 0xCA08B000 Data Flash OCMDR2 0xC304D000 EEERAM MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 682 0100b - 8KB OCMEMn 0101b - 16KB OCMEMn 0110b - 32KB OCMEMn 0111b - 64KB OCMEMn 1000b - 128KB OCMEMn 1001b - 256KB OCMEMn 1010b - 512KB OCMEMn Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 683 OCMDRn[4] or OCMDRn[5] bit controls whether prefetches (or speculative accesses) are initiated in response to instruction fetches or data references, see section FMC speculative reads. Value 0 means enable and value 1 means disable. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 684 • Attempted user mode accesses or any access with a size other than 32 bits are terminated with an error. The following table describes the OCMDRn reset values and the associated memory type: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 685 1b - OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. 27-24 OCMSZ OCMSZ OCMEM Size. This read-only field provides an encoded value of the on-chip memory size. 0000b - no OCMEMn Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 686 111b - Reserved OCMPU OCMPU OCMEM Memory Protection Unit. This field is reserved for this device. 11-8 Reserved — Reserved — OCMEM Control Field 1 OCM1 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 687 • Privileged writes from other bus masters are ignored. • Attempted user mode accesses or any access with a size other than 32 bits are terminated with an error. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 688 25% of the address range, this bit is used. 0b - OCMEMn is a power-of-2 capacity. 1b - OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 689 110b - OCMEMn is an EEE. 111b - Reserved OCMPU OCMPU OCMEM Memory Protection Unit. This field is reserved for this device. 11-8 Reserved — Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 690 MSCM Memory Map/Register Definition Field Function — Reserved — Reserved — MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 691: Chip-Specific Fmc Information
System MPU Memory Protection Unit (MPU) Transfers Crossbar Switch Crossbar Switch (AXBS-Lite) Register access Peripheral Bridge Peripheral Bridge (AIPS-Lite) Register controls MSCM OCMC1 field of MSCM registers On-Chip Memory Descriptor Register (OCMDR0) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 692: Fmc Masters
128 (64 for bank1, Data Flash)-bit buffer can store previously accessed flash memory or FlexNVM data for quick access times. 31.2.2 Features The FMC's features include: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 693: Modes Of Operation
The FMC is a flash acceleration unit with flexible buffers for user configuration. Whenever a hit occurs for the prefetch speculation buffer, or the single-entry buffer, the requested data is transferred within a single system clock. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 694: Default Configuration
3. Per 64-bit for Data Flash (bank 1), accessing the third longword requires 3 core clock cycles. The flash memory read itself takes 4 clocks, but the first clock overlaps with the second longword read. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 695: Initialization And Application Information
1 clock each because the data is already available inside the FMC. 31.6 Initialization and application information The FMC does not require user initialization. Flash acceleration features are enabled by default. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 696 Initialization and application information MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 697: Chip-Specific Ftfc Information
LPTimer, SRTC, RCM, SMC and SIM can be read as 0 during this time an can take up to 1 Flash clock cycle tFlash + 1 bus clock cycle tbus time slot of the command MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 698: Flash Memory Types
Emulated EEPROM backup, CSEc features (requires Emulated EEPROM to be enabled). Thus, a single FlexMEM read partition could be requested to be read from, programmed, erased, Emulated EEPROM update, or CSEc cryptographic operation, but only one of these at one time. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 699 When the FlexNVM is configured for Emulated EEPROM, the associated EFlash disappears from the memory map as shown 1. Interleaved blocks have a data width of 128-bits. 2. Non-interleaved blocks have a data width of 64-bits. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 700 Figure 32-2. 512 KB flash memory map 32.1.2.1.1 Emulated EEPROM data set size (EEESIZE) Table 32-2. Emulated EEPROM data set size for 4 KB FlexRAM Data flash IFR: 0x03FE EEERST EEESIZE = Unimplemented or Reserved MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 701 FlexNVM block between data flash memory and emulated EEPROM backup memory supporting emulated EEPROM functions. To program the DEPART value, see the Program Partition command. Table 32-4. FlexNVM partition code Data Flash IFR: 0x03FC DEPART = Unimplemented or Reserved MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 702 When the FlexNVM is configured for Emulated EEPROM, the associated EFlash disappears from the memory map as shown 3. Interleaved blocks have a data width of 128-bits. 4. Non-interleaved blocks have a data width of 64-bits. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 703 = Unimplemented or Reserved Table 32-7. EEPROM Data Set Size Field Description Field Description This read-only bitfield is reserved and must always be written as one. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 704 FlexNVM block between data flash memory and emulated EEPROM backup memory supporting emulated EEPROM functions. To program the DEPART value, see the Program Partition command. Table 32-8. FlexNVM partition code Data Flash IFR: 0x03FC DEPART = Unimplemented or Reserved MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 705 448 KB Program Flash area at the same time as the 64 KB Data Flash/FlexNVM area is being accessed. 5. Interleaved blocks have a data width of 128-bits. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 706 Figure 32-4. 2 MB flash memory map 32.1.2.3.1 Emulated EEPROM data set size (EEESIZE) Table 32-10. Emulated EEPROM data set size for 4 KB FlexRAM Data flash IFR: 0x03FE EEERST EEESIZE = Unimplemented or Reserved MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 707 FlexNVM block between data flash memory and emulated EEPROM backup memory supporting emulated EEPROM functions. Table 32-12. FlexNVM partition code Data Flash IFR: 0x03FC DEPART = Unimplemented or Reserved MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 708: Flash Memory Map
MWCT101xS_memory_map.xlsx. Flash memory base address Registers Program flash memory base address Flash configuration field Program flash memory FlexNVM base address FlexNVM FlexRAM base address FlexRAM Figure 32-5. Flash memory map MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 709: Flash Memory Security
MCU at boot time. For details about the meaning of FOPT values and how to program alternative configuration options, see FOPT boot options. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 710: Simultaneous Operations On Pflash Read Partitions
0s to 0 is not allowed as this overstresses the device. The standard shipping condition for flash memory is erased with security disabled. Data loss over time may occur due to degradation of the erased ('1') states and/or programmed ('0') MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 711: Features
32.2.1.3 FlexRAM features • Memory that can be used as traditional RAM or as high-endurance emulated EEPROM storage • Up to 4 KB of FlexRAM configured for emulated EEPROM or traditional RAM operations MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 712 • Strict Sequential Boot Mode (unchangeable once set) 32.2.1.5 Other FTFC module features • Internal high-voltage supply generator for flash memory program and erase operations • Optional interrupt generation upon flash command completion MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 713: Block Diagram
/ output. Data flash memory — Partitioned from the FlexNVM block, the data flash memory provides nonvolatile storage for user data, boot code, and additional code store. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 714 EEPROM data or as traditional RAM. When configured for emulated EEPROM, valid writes to the FlexRAM generates a new emulated EEPROM backup data record stored in the emulated EEPROM backup flash memory. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 715 Secure — An MCU state conveyed to the FTFC module as described in the Chip Configuration details for this device. In the secure state, reading and changing NVM contents is restricted. Word — 16 bits of data with an aligned word having byte-address[0] = 0. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 716: External Signal Description
Register (FEPROT). 0x0_040D Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT). 0x0_040C Flash security byte. Refer to the description of the Flash Security Register (FSEC). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 717: Program Flash 0 Ifr Map
The data flash 0 IFR is located within the data flash 0 memory block. Address Range Size (Bytes) Field Description 0x00 – 0x3FB, 0x3FE – 0x3FF 1022 Reserved 0x3FD EEPROM Data Set Size 0x3FC FlexNVM Partition Code MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 718: Register Descriptions
During this initialization period the user may write any register. All register writes are also disabled (except for registers FCNFG, FSTAT, FERCNFG and FERSTAT) whenever an erase suspend request is active (FCNFG[ERSSUSP]=1). 32.4.4.1 FTFC register descriptions MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 719 Data Flash Protection Register (FDPROT) Table 32-14 Flash CSEc Status Register (FCSESTAT) Flash Error Status Register (FERSTAT) Flash Error Configuration Register (FERCNFG) 32.4.4.1.2 Flash Status Register (FSTAT) 32.4.4.1.2.1 Offset Register Offset FSTAT MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 720 The read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by writing a 1 to it. Writing a 0 to RDCOLERR has no effect. 0b - No collision error detected Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 721 The erase control bits (ERSAREQ and ERSSUSP) have write restrictions. RAMRDY, and EEERDY are read-only status bits. The reset values for the RAMRDY, and EEERDY bits are determined during the reset sequence. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 722 1b - Suspend the current Erase Flash Sector command execution Reserved — Reserved — RAM Ready RAMRDY This flag indicates the current status of the FlexRAM. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 723 During the reset sequence, the register is loaded with the contents of the flash security byte in the Flash Configuration Field located in program flash memory. 32.4.4.1.4.3 Diagram Bits KEYEN MEEN FSLACC Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 724 10b - MCU security status is unsecure (The standard shipping condition of the FTFC is unsecure.) 11b - MCU security status is secure 32.4.4.1.5 Flash Option Register (FOPT) 32.4.4.1.5.1 Offset Register Offset FOPT MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 725 32.4.4.1.6 Flash Common Command Object Registers (FCCOB0 - FCCO 32.4.4.1.6.1 Offset Register Offset FCCOB3 FCCOB2 FCCOB1 FCCOB0 FCCOB7 FCCOB6 FCCOB5 FCCOB4 FCCOBB Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 726 This number is a reference to the FCCOB register name and is not the register address. FCCOB Number Typical Command Parameter Contents [7:0] FCMD (a code that defines the FTFC command) Flash address [23:16] Flash address [15:8] MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 727 FTFC command (except ERSALLU command and erase all that is triggered external to the FTFC). Unprotected regions can be changed by program and erase operations. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 728 • A '1' in an FPROT[PROT] bit indicates its corresponding flash protection region is unprotected Program flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 729 FSTAT[FPVIOL] bit. A full block erase of a program flash block (except ERSALLU command and erase all that is triggered external to the FTFC) is not possible if it contains any protected region. 32.4.4.1.8 EEPROM Protection Register (FEPROT) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 730 Trying to alter data by writing to any protected area in the emulated EEPROM results in a protection violation error and sets the FSTAT[FPVIOL] bit. 00000000b - EEPROM region is protected 00000001b - EEPROM region is not protected MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 731 This 1-to-0 transition check is performed on a bit-by-bit basis. Those FDPROT bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored. Restriction: The user must never write to the FDPROT register while a command is running (CCIF=0). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 732 Following is a quick reference mapping CSEc status flags from the FCSESTAT register. Table 32-15. Boot/MAC map to CSEc Status Flags <err code> No Boot Type MAC is Empty NO_ERR MAC Mismatch NO_ERR MAC Match NO_ERR MAC_KEY is empty NO_SECURE_BOOT MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 733 The SB bit is set by the secure boot process if the BOOT_MAC_KEY slot is not empty. It is cleared upon reset. Assumes secure boot flavor is configured (serial, parallel or strict) Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 734 The DFDIF flag is readable and writable. The unassigned bits read 0 and are not writable. 32.4.4.1.11.3 Diagram Bits Reset 32.4.4.1.11.4 Fields Field Function Reserved — Double Bit Fault Detect Interrupt Flag Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 735 The FDFD and DFDIE bits are readable and writable. The unassigned bits read 0 and are not writable. 32.4.4.1.12.3 Diagram Bits Reset 32.4.4.1.12.4 Fields Field Function Reserved — Force Double Bit Fault Detect Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 736: Functional Description
Individual regions within the flash memory can be protected from program and erase operations. Protection is controlled by the following registers: • FPROTn — Four registers protect 32 regions of the program flash memory as shown in the following figure MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 737 EEPROM backup Last FlexNVM address Figure 32-8. Data flash protection (2 data flash sizes) • FEPROT — Protects eight regions of the emulated EEPROM memory as shown in the following figure MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 738: Flexnvm Description
The FlexNVM partition code choices affect the endurance and data retention characteristics of the device. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 739 The partition information (EEESIZE, DEPART) is stored in the data flash IFR and is programmed using the Program Partition command (see Program Partition command). Typically, the Program Partition command is executed only once in the lifetime of the device. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 740 32.5.2.4 Write endurance to FlexRAM for emulated EEPROM When the FlexNVM partition code is not set to full data flash, the emulated EEPROM data set size should be set to the non-zero value. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 741: Interrupts
Table 32-16. FTFC interrupt sources FTFC Event Readable Interrupt Status Bit Enable Bit FTFC Command and CSEc command Complete FSTAT[CCIF] FCNFG[CCIE] FTFC Read Collision Error FSTAT[RDCOLERR] FCNFG[RDCOLLIE] FTFC ECC Error Detection FERSTAT[DFDIF] FERCNFG[DFDIE] MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 742: Flash Operation In Low-Power Modes
Configuration details of this device for how to activate each mode. 32.5.6 Flash memory reads and ignored writes The FTFC module requires only the flash address to execute a flash memory read. MCU read access is available to all flash memory. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 743: Read While Write (Rww)
The user must take appropriate counter measures to prevent data loss in case of an interrupted program or erase operation. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 744: Ftfc Command Operations
FTFC command. The individual registers that make up the FCCOB data set can be written in any order. The user must be sure to provide all of the required parameters (which may vary from command to command). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 745 FCCOB and FSTAT registers. 4. The FTFC sets the FSTAT[CCIF] bit signifying that the command has completed. The flow for a generic command write sequence is illustrated in the following figure. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 746 Command Program Flash Data Flash FlexRAM Function 0x00 Read 1s Block × × Verify that a program flash or data flash block is erased. FlexNVM Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 747 Read 8 bytes of a dedicated 64 byte field in the program flash 0 IFR. 0x43 Program Once One-time program of 8 bytes of a Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 748 Program the FlexNVM Partition Code and emulated EEPROM Data Set Size into the data flash IFR. format all emulated EEPROM backup data sectors allocated for emulated Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 749 × × 0x45 Verify Backdoor Access Key × × × 0x49 Erase All Blocks Unsecure × × — 0x80 Program Partition × × × 0x81 Set FlexRAM Function × × × MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 750: Margin Read Commands
Program Check command have a margin choice parameter that allows the user to apply non-standard read reference levels to the program flash and data flash array reads performed by these commands. Using the preset 'user' and 'factory' margin levels, these MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 751: Flash Command Descriptions
This section describes all flash commands that can be launched by a command write sequence. The FTFC sets the FSTAT[ACCERR] bit and aborts the command execution if any of the following illegal conditions occur: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 752 After clearing CCIF to launch the Read 1s Block command, the FTFC sets the read margin for 1s according to Table 32-20 and then reads all locations within the selected program flash or data flash block. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 753 Number of double-phrases to be verified for interleaved flash, phrases for non-interleaved flash [15:8] Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 754 Read-1s fails FSTAT[MGSTAT0] 32.5.11.3 Program Check command The Program Check command tests a previously programmed program flash or data flash longword to see if it reads correctly at the specified margin level. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 755 Margin read commands Table 32-26. Margin level choices for Program Check Read Margin Choice Margin Level Description 0x01 Read at 'User' margin-1 and 'User' margin-0 0x02 Read at 'Factory' margin-1 and 'Factory' margin-0 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 756 The protection status is always checked. The targeted flash locations must be currently unprotected (see the description of the FPROT registers) to permit execution of the Program Phrase operation. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 757 Erase Flash Block command aborts setting the FSTAT[ACCERR] bit. The Erase Flash Block command aborts and sets the FSTAT[FPVIOL] bit if any region within the block is protected (see the description of the program flash protection (FPROT) registers and the MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 758 Table 32-33. Erase Flash Sector command error handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid Flash address is supplied FSTAT[ACCERR] Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 759 Flash Sector operation will eventually complete. If the minimum period is continually violated, i.e., the suspend requests come repeatedly and too quickly, no forward progress is made by the Erase Flash Sector algorithm. The resume/suspend sequence runs indefinitely without completing the erase. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 760 Aborting the erase leaves the bitcells in an indeterminate, partially-erased state. Data in this sector is not reliable until a new erase command fully completes. The following figure shows how to suspend and resume the Erase Flash Sector operation. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 761 Set CCIF ERSSCR Suspended Resume Erase? ERSSUSP: Bit in FCNFG register No, Abort SUSPACK: Internal Suspend Acknowledge Clear ERSSUSP User Cmd Interrupt/Suspend Figure 32-12. Suspend and resume of Erase Flash Sector operation MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 762 After the Program Section operation has completed, the CCIF flag will set and normal access to the FlexRAM is restored. The contents of the Section Program Buffer is not changed by the Program Section operation. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 763 6. To program additional flash sectors, repeat steps through 4. 7. To restore emulated EEPROM functionality, execute the Set FlexRAM Function command to make the FlexRAM available for emulated EEPROM. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 764 Apply the 'Factory' margin to the normal read-1 level Table 32-38. Read 1s All Blocks command error handling Error Condition Error Bit An invalid margin choice is specified FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 765 The Read Once command can be executed any number of times. Table 32-40. Read Once command error handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 766 Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] The requested record has already been programmed to a non-erased value FSTAT[ACCERR] Any errors have been encountered during the verify operation. FSTAT[MGSTAT0] MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 767 FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 1. User margin read may be run using the Read 1s All Blocks command to verify all bits are erased. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 768 Key Byte 0 0x0_0003 Key Byte 1 0x0_0002 Key Byte 2 0x0_0001 Key Byte 3 0x0_0000 Key Byte 4 0x0_0007 Key Byte 5 0x0_0006 Key Byte 6 0x0_0005 Key Byte 7 0x0_0004 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 769 Erase All Blocks Unsecure command, and the FCNFG[RAMRDY] bit is set. If the erase or program verify fails, the FSTAT[MGSTAT0] bit is set. The CCIF flag is set after the Erase All Blocks Unsecure operation completes. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 770 FlexRAM load during reset option (only bit 0 used): 0 - FlexRAM loaded with valid EEPROM data during reset sequence 1 - FlexRAM not loaded during reset sequence Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 771 DFlash where the keys are stored. Additionally if any Flash Keys are write protected, they can't be erased/ removed, thus the DFlash can't be erased and the Authentication process will not pass. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 772 Table 32-54. Valid FlexNVM partition codes : 128 KB and 256 KB configurations with 32 KB FlexNVM FlexNVM Partition Code DEPART Data flash Size (KB) EEPROM-backup Size (KB) (FCCOB5[3:0]) 0000 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 773 EEPROM-backup Size (KB) (FCCOB5[3:0]) 0000 DFlash size (512 KB) 0100 DFlash size - EEPROM size (512 KB - 64 KB = 448 KB) 1111 DFlash size (512 KB) 1. FCCOB5[7:4] = 0000 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 774 The Set FlexRAM Function command changes the function of the FlexRAM: • When not partitioned for emulated EEPROM, the FlexRAM is typically used as traditional RAM. • When partitioned for emulated EEPROM, the FlexRAM is typically used to store EEPROM data. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 775 • Copy-down existing EEPROM data to FlexRAM • Set the FCNFG[EEERDY] flag After clearing CCIF to launch the Set FlexRAM Function command, the FTFC sets the function of the FlexRAM based on the FlexRAM Function Control Code. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 776 (~150uSec) and begin the EEPROM maintenance activities on the entire block of quick write data. The CCIF and EEERDY flag will remain negated until all EEPROM quick write maintenance activities have completed. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 777: Security
Flash Configuration Field (see Flash configuration field description). The following fields are available in the FSEC register. Details of the settings are described in the FSEC register description. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 778 If the keys match, the FSEC[SEC] bits are changed to unsecure the MCU. The entire 8-byte key cannot be all 0s or all 1s, i.e., 0x0000_0000_0000_0000 and 0xFFFF_FFFF_FFFF_FFFF are not accepted by the MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 779: Cryptographic Services Engine (Csec)
SHE specification, therefore we do not replicate the document here. 6. HIS SHE Specification - Secure Hardware Extension Functional Specification; Version 1.0.1; Rev429 from 23.03.2009 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 780 CSEc command will be canceled. 5. Starting execution of CCOB commands or CSEc commands will lock out the CCOB interface, the EEERAM and the PRAM. The lock is in place until the requested command completes. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 781 1’b1 0x4 - 0xA Flash RESERVED 1’b1 0xB - 0xE RESERVED RESERVED 1’b0 RESERVED RAM_KEY Volatile (RAM_KEY) Table 32-64. Other volatile keys Key Name ADDRESS Type Size (Bytes) Comments PRNG_KEY PRNG_STATE MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 782 • Sequential Boot Mode a. Flash system comes out of RESET and main Core stays in RESET, or may execute from ROM code b. FTFC verifies customer firmware block ( via CMAC calculation) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 783 Additionally, non-volatile keys may be disabled (again, each key has an attribute to dictate this behavior) when a debugger is attached (JTAG, BDM, etc.), and will only be re-activated upon the next successful boot. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 784 Sequence Error (ERC_SEQUENCE_ERROR). 4. For continued commands (Command Header Byte[2] =0x01) will ignore any data changes in Byte[1] (data type), Byte[3] (key slot) and any MESSAGE_LENGTH, MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 785 • ERC_RNG_SEED. Example: didn't initialize the seed using the TRNG, i.e., CSESTAT[RIN] != 1 • ERC_NO_DEBUGGING. Example: DEBUG command authentication failed • ERC_BUSY. N/A for FTFC • ERC_MEMORY_FAILURE. Example: general memory technology failure (multi- bit ECC error, common fault detected) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 786 CMAC Verify of a set of 128-bit blocks where there are more than seven 128- bit blocks. 0x00 : 1st Function Call 0x01 : 2nd through nth Function Call MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 787 0x10 - GET_ID 0x11 - BOOT_DEFINE 0x12 - DBG_CHAL 0x13 - DBG_AUTH • ERC_BUSY <— located in FCSESTAT register 0x14 - Reserved 0x15 - Reserved 0x16 - MP_COMPRESS 0x17 - 0xFF - Reserved MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 788 2 changed to indicate this is a continuation of the same command). For continuation of any command, the KeyID, CSEc Format, and Message Length is only captured on the first command written. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 789 CSEc Command and Data Structure for CSE_PRAM content writes/reads is as follows: Figure 32-15. Encrypt ECB input parameter format Byte Page 0x01 0x00 0x00 KeyID Error Bits Reserved PAGE_LENG PLAIN_TEXT 1 [0:15] PLAIN_TEXT 2 [0:15] Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 790 Table 32-67. Encrypt CBC command details Parameter Direction Width KEY_ID PAGE_LENGTH PLAIN_TEXT n * 128 CIPHER_TEXT n* 128 CIPHER_TEXT = ENC (PLAIN_TEXT) CBC,KEY, KEY_ID,IV Error Codes: ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_KEY_NOT_AVAILABLE, ERC_KEY_INVALID,ERC_KEY_EMPTY, ERC_MEMORY_FAILURE, ERC_BUSY, ERC_GENERAL_ERROR MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 791 Figure 32-19. Continuation of input parameters 0x02 0x00 0x01 KeyID Error Bits Reserved PLAIN_TEXT 7 [0:15] PLAIN_TEXT 8 [0:15] PLAIN_TEXT 9 [0:15] PLAIN_TEXT 10 [0:15] PLAIN_TEXT 11 [0:15] PLAIN_TEXT 12 [0:15] PLAIN_TEXT 13 [0:15] MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 792 Error Codes: ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_KEY_NOT_AVAILABLE, ERC_KEY_INVALID, ERC_KEY_EMPTY, ERC_MEMORY_FAILURE, ERC_BUSY, ERC_GENERAL_ERROR Figure 32-21. Decrypt ECB input parameter format 0x03 0x00 0x00 KeyID Error Bits Reserved PAGE_LENG CIPHER_TEXT 1 [0:15] Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 793 Table 32-69. Decrypt CBC command details Parameter Direction Width KEY_ID PAGE_LENGTH CIPHER_TEXT n * 128 PLAIN_TEXT n * 128 PLAIN_TEXT = DEC (CIPHER_TEXT) CBC,KEY, KEY_ID,IV Error Codes : ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_KEY_NOT_AVAILABLE, ERC_KEY_INVALID,ERC_KEY_EMPTY, ERC_MEMORY_FAILURE, ERC_BUSY, ERC_GENERAL_ERROR MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 794 Figure 32-25. Continuation of input parameters 0x04 0x00 0x01 KeyID Error Bits Reserved CIPHER_TEXT 7 [0:15] CIPHER_TEXT 8 [0:15] CIPHER_TEXT 9 [0:15] CIPHER_TEXT 10 [0:15] CIPHER_TEXT 11 [0:15] CIPHER_TEXT 12 [0:15] CIPHER_TEXT 13 [0:15] MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 795 Error Codes: ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_KEY_NOT_AVAILABLE, ERC_KEY_INVALID,ERC_KEY_EMPTY, ERC_MEMORY_FAILURE, ERC_BUSY, ERC_GENERAL_ERROR Figure 32-27. Generate MAC input parameters 0x05 0x00 0x00 KeyID Error Bits Reserved MESSAGE_LENGTH DATA 1 [0:15] DATA 2 [0:15] Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 796 Figure 32-30. Continuation of output parameters 0x05 0x00 0x01 KeyID Error Bits Reserved MESSAGE_LENGTH DATA 8[0:15] MAC[0:15] DATA 10 [0:15] DATA 11 [0:15] DATA 12 [0:15] Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 797 Error Bits Reserved MESSAGE_LENGTH Flash Start Address Reserved Reserved Figure 32-32. CSEc format for CMD_GENERATE_MAC output parameters 0x05 0x01 0x00 KeyID Error Bits Reserved MESSAGE_LENGTH Flash Start Address Reserved MAC [0:15] Reserved MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 798 KEY, KEY_ID = TRUNCATE (MAC, MAC_LENGTH) VERIFICATION_STATUS = (0 ~= ( MAC - MAC calc Error Codes: ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_KEY_NOT_AVAILABLE, ERC_KEY_INVALID,ERC_KEY_EMPTY, ERC_MEMORY_FAILURE, ERC_BUSY, ERC_GENERAL_ERROR Figure 32-33. Verify MAC input parameters MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 799 MAC [0:15] Figure 32-36. Continuation of output parameters 0x06 0x00 0x01 KeyID Error Bits Reserved MAC Length Reserved MESSAGE_LENGTH Verification Data 7 [ 6:15] Status Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 800 MAC [0:15] Reserved Figure 32-38. Verify MAC (pointer method) output parameters 0x06 0x01 0x00 KeyID Error Bits Reserved MAC Length Reserved MESSAGE_LENGTH Flash Start Address Verification Reserved Status MAC [0:15] Reserved MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 801 GENERATE_MAC to take into consideration. For the VERIFY_ONLY attribute, if set, the associated memory key slot will be treated as invalid by the CMD_GENERATE_MAC command (only valid for CMD_VERIFY_MAC). The VERIFY_ONLY attribute has no effect if KEY_USAGE == 0. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 802 Error Bits Reserved M1 [0:15] M2 [0:31] M3 [0:15] Reserved Figure 32-40. Load key output parameters 0x07 0x00 0x01 KeyID Error Bits Reserved M1 [0:15] Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 803 RAM_KEY_PLAIN = 1 Error Codes: ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_BUSY, ERC_GENERAL_ERROR Figure 32-41. Load Plain Key input parameters 0x08 0x00 0x00 KeyID Error Bits Reserved Plain Key[0:15] Reserved This command has no return values MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 804 M4 = UID| ID | ID | ENC RAM_KEY SECRET_KEY EBC, K3 M5 = CMAC (M4) Error Codes: ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_KEY_INVALID, ERC_KEY_EMPTY, ERC_MEMORY_FAILURE, ERC_BUSY, ERC_GENERAL_ERROR Figure 32-42. Export RAM_KEY input parameters MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 805 The command has to ignore active debugger protection or secure boot protection flags on SECRET_KEY. NOTE: The command may need several hundred ms to return Error Codes : ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_MEMORY_FAILURE, ERC_BUSY, ERC_GENERAL_ERROR Figure 32-44. INIT_RNG input parameters MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 806 NOTE: The command may need several hundred ms to return Error Codes : ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_RNG_SEED, ERC_MEMORY_FAILURE, ERC_BUSY, ERC_GENERAL_ERROR Figure 32-45. EXTEND_SEED input parameters 0x0B 0x00 0x00 KeyID Error Bits Reserved ENTROPY [0:15] Reserved MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 807 Figure 32-46. CMD_RND input parameters 0x0C 0x00 0x00 KeyID Error Bits Reserved Reserved Table 32-79. CMD_RND Output Parameters 0x0C 0x00 0x00 KeyID Error Bits Reserved RND [0:15] Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 808 == 1 AND SREG == 1 AND SREG == 0) SECURE BOOT BOOT OK BOOT FINISHED SREG BOOT FINISHED SREG BOOT OK END IF Error Codes : ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_NO_SECURE_BOOT, ERC_BUSY, ERC_GENERAL_ERROR MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 809 BOOT FINISHED END IF Error Codes : ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_NO_SECURE_BOOT, ERC_BUSY, ERC_GENERAL_ERROR Table 32-83. CMD_BOOT_OK Input Parameters 0x0F 0x00 0x00 KeyID Error Bits Reserved Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 810 KEY_MASTER_ECU_KEY Error Codes : ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_KEY_NOT_AVAILABLE, ERC_MEMORY_FAILURE, ERC_GENERAL_ERROR Figure 32-47. GET_ID input parameters 0x10 0x00 0x00 KeyID Error Bits Reser Reserved CHALLENGE [0:15] Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 811 Additionally, starting any FCCOB command in one of the pauses of continuation of a CSEc command will result in the FCCOB command executing to completion as expected, but will kill/cancel the current CSEc command. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 812 2’b01 : Serial Boot method 2’b10 : Parallel Boot method 2’b11 : No Boot defined (MASTER_ECU_KEY) not initialized yet, or non-CSEc enabled part Error Codes: ERC_NO_ERROR, ERC_SEQUENCE_ERROR, , ERC_KEY_INVALID,, ERC_MEMORY_FAILURE, ERC_BUSY, ERC_GENERAL_ERROR MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 813 CMD_DBG_CHAL command would be required to be re- issued before continuing. Table 32-86. DEBUG command details Parameter Direction Width CHALLENGE Error Codes : ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_WRITE_PROTECTED, ERC_RNG_SEED, ERC_NO_DEBUGGING, ERC_MEMORY_FAILURE, ERC_BUSY, ERC_GENERAL_ERROR Figure 32-50. DEBUG input parameters MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 814 WRITE_PROTECTION flag set, the command will stop and not offer any failure analysis mode. After SHE authentication of the process passes, the command will erase the Flash Keys (DFlash), placing the part back into factory status. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 815 Messages must be pre-processed per SHE specification if they do not already meet the full 128-bit block size requirement, i.e., the user/application is responsible for padding if the message is not already 128-bits in length. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 816 0x00 KeyID Error Bits Reserved PAGE_LENG MP_COMPRESS [0:15] DATA 2 [0:15] DATA 3 [0:15] DATA 4 [0:15] DATA 5 [0:15] DATA 6 [0:15] DATA 7 [0:15] Figure 32-55. Continuation of input parameters MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 817: Reset Sequence
If a reset occurs while any FTFC command is in progress, that command is immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. Commands and operations do not automatically resume after exiting reset. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 818 Functional description MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 819: Chip-Specific Quadspi Information
QuadSPI memory size requirement for AHB Buffers is : 128x64 , i.e. 1 KB. 33.1.3 QuadSPI register reset values Table 33-1. QuadSPI register reset values Register Reset value Module Configuration Register (QuadSPI_MCR) 000F_400C Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 820: Use Case
Internal sampling (N/1) (Flash B) DQS sampling Internally method generated DQS External DQS Loopback DQS HyperRAM Internal sampling (4x method) (DDR) DQS sampling Internally method generated DQS External DQS Loopback DQS MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 821: External Memory Options
33.1.7 Recommended software configuration • QuadSPI operation is restricted to system clock as SPLL. • When switching the system modes between HSRUN and RUN, QuadSPI should be disabled and then re-enabled. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 822: Recommended Programming Sequence
Quadspi Clocking mode selection. Always program SCLKCFG[6] twice while configuring mode SCLKCFG[6] selection. 0: Selecting SYS_CLK as AHB read interface Clock and module clock. Mandatory for HSRUN 80/RUN 64/RUN 80 configurations. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 823: Quadspi_Soccr[Soccfg] Implementation
SOC configuration: Fine delay chain configuration for Flash A 7F: Delay of 127 buffers and 128 muxes 7E :Delay of 126 buffers and 127 muxes 7D :Delay of 125 buffers and 126 muxes Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 824 “imprecise” such that an error response on any beat of the burst is reported on the last beat. SOCCFG[28] Programmable Divider Disable. 0: Divider enabled 1: Divider disabled SOCCFG[31:29] Programmable divider configuration selection. 000 : Div by 1 001 : Div by 2 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 825: Introduction
IP registers space (32-bit access) and fill TX Buffer via IPS register space (32-bit access). • AHB master can be a DMA with configurable inner loop size. • Multimaster accesses with priority • Flexible and configurable buffer for each master MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 826: Block Diagram
• Supports all types of addressing. 33.2.2 Block Diagram The following figure is a block diagram of the Quad Serial Peripheral Interface (QuadSPI) module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 827: Quadspi Modes Of Operation
Figure 33-2. QuadSPI Block Diagram 33.2.3 QuadSPI Modes of Operation For power management through IPS interface access and correct config register programming sequences, QuadSPI supports three modes: normal, module disable and stop mode. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 828: Acronyms And Abbreviations
Quad Serial Peripheral Interface Serial Communications Clock Write 1 to clear, writing a 1 to this field resets the flag Input output. In this document, I/O lines are also referred as pads. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 829: Glossary For Quadspi Module
• Single pad: Single line I/O with one data out and one data in line to/from the serial flash device. • Dual pad: Dual line I/O with two bidirectional I/O lines, driven alternatively by the serial flash device or the QuadSPI module Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 830: External Signal Description
Single and Dual Instructions are executed. The module supports driving these inputs to dedicated values. In single I/O mode, QuadSPI drives data on IOFB[0] and expects data on IOFB[1]. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 831: Driving External Signals
DDR mode. It is also provided as an output signal during write data phase. 33.3.1 Driving External Signals The different phases of the serial flash access scheme are shown in the following figure. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 832 • IDLE: Serial flash device not selected. No interaction with the serial flash device. All IOFx signals driven. • INSTRUCTION: Serial flash device selected. The instruction is sent to the serial flash device. All IOFx signals are driven. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 833: Memory Map And Register Definition
The values of the bits or fields are not changed. The condition term [A or B] indicates that the register or field can be written to if at least one of the conditions is fulfilled. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 834: Peripheral Bus Register Descriptions
See section 33.4.2.5/ 4007_6014 Buffer1 Configuration Register (QuadSPI_BUF1CR) See section 33.4.2.6/ 4007_6018 Buffer2 Configuration Register (QuadSPI_BUF2CR) See section 33.4.2.7/ 4007_601C Buffer3 Configuration Register (QuadSPI_BUF3CR) See section Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 835 Serial Flash A2 Top Address (QuadSPI_SFA2AD) See section 33.4.2.28/ 4007_6188 Serial Flash B1 Top Address (QuadSPI_SFB1AD) See section 33.4.2.29/ 4007_618C Serial Flash B2 Top Address (QuadSPI_SFB2AD) See section Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 836 0000_0000h 33.4.2.30/ 4007_624C RX Buffer Data Register (QuadSPI_RBDR19) 0000_0000h 33.4.2.30/ 4007_6250 RX Buffer Data Register (QuadSPI_RBDR20) 0000_0000h 33.4.2.30/ 4007_6254 RX Buffer Data Register (QuadSPI_RBDR21) 0000_0000h Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 837 See section 33.4.2.33/ 4007_632C Look-up Table register (QuadSPI_LUT7) See section 33.4.2.33/ 4007_6330 Look-up Table register (QuadSPI_LUT8) See section 33.4.2.33/ 4007_6334 Look-up Table register (QuadSPI_LUT9) See section Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 838 See section 33.4.2.33/ 4007_6384 Look-up Table register (QuadSPI_LUT29) See section 33.4.2.33/ 4007_6388 Look-up Table register (QuadSPI_LUT30) See section 33.4.2.33/ 4007_638C Look-up Table register (QuadSPI_LUT31) See section Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 839 See section 33.4.2.33/ 4007_63DC Look-up Table register (QuadSPI_LUT51) See section 33.4.2.33/ 4007_63E0 Look-up Table register (QuadSPI_LUT52) See section 33.4.2.33/ 4007_63E4 Look-up Table register (QuadSPI_LUT53) See section Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 840 See section 33.4.2.1 Module Configuration Register (QuadSPI_MCR) The QuadSPI_MCR holds configuration data associated with QuadSPI operation. Write: • SCLKCFG: Disabled Mode • ISD3FB, ISD2FB,ISD3FA, ISD2FA: Disabled Mode • All other fields: Anytime MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 841 31–24 Serial Clock Configuration. This field configuration is chip specific. For details, refer to chip-specific SCLKCFG QuadSPI information. It may be used for dividing clocks. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 842 This field is used to enable variable latency feature in the controller. This field is valid for HyperRAM where VAR_LAT_EN Data strobe acts as an output from the memory during the command and address (CA) cycles of a read or Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 843 It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 844 23–17 This field is reserved. Reserved This field is reserved. Reserved IDATSZ IP data transfer size. Defines the data transfer size in bytes of the IP command. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 845 • TCSS = 0.5 SCK clk if N= 0/1 else, N+0.5 SCK clk if N>1, where N is the setting of TCSS. 2. Any update to the TCSS register bits is visible on the flash interface only from the second transaction following the update. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 846 Master ID. The ID of the AHB master associated with BUFFER0. Any AHB access with this master port number is routed to this buffer. It must be ensured that the master IDs associated with all buffers must be different. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 847 MSTRID field of BUF2CR. Any buffer "miss" leads to the buffer being flushed and a serial flash transaction being triggered as per the sequence pointed to by the SEQID field. Write: • QSPI_SR[AHB_ACC] = 0 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 848 In the case that the ALLMST field is not set, any such transaction (where master port number does not match any of the MSTRID fields) will be returned an ERROR response. Write: • QSPI_SR[AHB_ACC] = 0 Address: 4007_6000h base + 1Ch offset = 4007_601Ch Reserved Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 849 "miss" leads to the buffer being flushed and a serial flash transaction being triggered as per the sequence pointed to by the SEQID field. Write: • QSPI_SR[AHB_ACC] = 0 Address: 4007_6000h base + 20h offset = 4007_6020h Reserved Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 850 QuadSPI information. Write: • QSPI_SR[AHB_ACC] = 0 Address: 4007_6000h base + 24h offset = 4007_6024h SOCCFG Reset QuadSPI_SOCCR field descriptions Field Description SOCCFG SOC Configuration For details, refer to chip-specific QuadSPI information. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 851 It is the responsibility of the software to ensure that BUF1IND value is not greater than the overall size of the buffer. The hardware does not provide any protection against illegal programming. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 852 • QSPI_SR[AHB_ACC] = 0 Address: 4007_6000h base + 38h offset = 4007_6038h TPINDX2 Reserved Reset QuadSPI_BUF2IND field descriptions Field Description 31–3 Top index of buffer 2. TPINDX2 Reserved This field is reserved. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 853 The software should ensure that the serial flash address provided in the QSPI_SFAR register or the incoming AHB address lies in the valid flash address range. Write: • QSPI_SR[IP_ACC] = 0 • QSPI_SR[AHB_ACC] = 0 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 854 The Sampling Register allows configuration of how the incoming data from the external serial flash devices are sampled in the QuadSPI module. Write: Disabled Mode Address: 4007_6000h base + 108h offset = 4007_6108h Reserved Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 855 Select sampling at non-inverted clock Select sampling at inverted clock. 4–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Reserved This field is reserved. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 856 0x2 would indicate 8 bytes are available. Reserved This field is reserved. 33.4.2.17 RX Buffer Control Register (QuadSPI_RBCT) This register contains control data related to the receive data buffer. Write: • QSPI_SR[IP_ACC] = 0 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 857 QSPI_SR[RXWE] flag is asserted.The value should be entered as the number of 4-byte entries minus 1. For example, a value of 0x0 would set the watermark to 4 bytes, 1 to 8 bytes, 2 to 12 bytes, and so on. For details, refer to Usage. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 858 TX buffer. The valid bits will be used and the rest of the bits will be discarded. Write: • QSPI_SR[TXFULL] = 0 32-bit write access required MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 859 4Bytes entries minus 1. For example, a value of 0x0 would set the watermark to 4 bytes, 1 to 8 bytes, 2 to 12 Bytes, and so on.For details, refer to Usage. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 860 The QSPI_SR register provides all available status information about SFM command execution and arbitration, the RX Buffer, TX Buffer, and the AHB Buffer. Address: 4007_6000h base + 15Ch offset = 4007_615Ch Reserved Reserved Reserved Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 861 128 bit data available in TX FIFO for any pop operation; otherwise, QSPI_FR[TBUF] will be set. RX Buffer DMA. Asserted when RX Buffer read out via DMA is active i.e DMA is requested or running. RXDMA Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 862 AHB_ACC IP Access. Asserted when transaction currently executed was initiated by IP bus. IP_ACC Module Busy. Asserted when module is currently busy handling a transaction to an external flash device. BUSY MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 863 QuadSPI module. Write: Enabled Mode Address: 4007_6000h base + 160h offset = 4007_6160h Reserved Reserved Reserved Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 864 QSPI_MCR[CLR_RXF] should be set to clear any remaining data in buffers i.e., reset to flash and AHB domain after re-configuring the correct sequence instruction. Refer to Table 33-14 for a list of legal instructions. 22–18 This field is reserved. Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 865 • Write access to the QSPI_IPCR register. Any command leading to the assertion of the IPIEF flag is ignored • Write access to the QSPI_SFAR register. • Write access to the QSPI_RBCT register. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 866 QuadSPI module from entering Stop Mode or Module Disable Mode when this flag is set. Write: Anytime Address: 4007_6000h base + 164h offset = 4007_6164h Reserved Reserved Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 867 RX Buffer Drain DMA Enable: Enables generation of DMA requests for RX Buffer Drain. When this bit is RBDDE set DMA requests are generated as long as the QSPI_SR[RXWE] status bit is set. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 868 No IPIEF interrupt will be generated IPIEF interrupt will be generated This field is reserved. Reserved This field is reserved. Reserved 3–1 This field is reserved. Reserved Reserved. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 869 Chapter 33 Quad Serial Peripheral Interface (QuadSPI) QuadSPI_RSER field descriptions (continued) Field Description Transaction Finished Interrupt Enable TFIE No TFF interrupt will be generated TFF interrupt will be generated MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 870 An AHB sequence may be suspended when a high priority AHB master makes an access before the AHB sequence completes the data transfer requested. Address: 4007_6000h base + 168h offset = 4007_6168h Reserved Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 871 Suspended Buffer: Provides the suspended buffer number. Valid only when SUSPND is set to 1'b1 SPDBUF 5–1 This field is reserved. Reserved When set, it signifies that a sequence is in suspended state SUSPND MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 872 Buffer Pointer Clear: BFPTRC 1: Clears the sequence pointer for AHB accesses as defined in QuadSPI_BFGENCR. This is a self-clearing field. This bit should be programmed two times to clear the sequence pointers. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 873 • QSPI_SR[IP_ACC] = 0 • QSPI_SR[AHB_ACC] = 0 Address: 4007_6000h base + 184h offset = 4007_6184h TPADA2 Reserved Reset * Notes: • TPADA2 field: See the module configuration for the device specific reset values. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 874 The QSPI_SFB2AD register provides the address mapping for the serial flash B2.The difference between QSPI_SFB2AD[TPADB2] and QSPI_SFB1AD[TPADB1] defines the size of the memory map for serial flash B2. Write: • QSPI_SR[IP_ACC] = 0 • QSPI_SR[AHB_ACC] = 0 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 875 RXDATA RX Data. The RXDATA field contains the data associated with the related RX Buffer entry. Data format and byte ordering is given in Byte Ordering of Serial Flash Read Data MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 876 Setting both the LOCK and UNLOCK bits as "00" or "11" is not allowed. Write: Just after writing the LUT Key Register (QSPI_LUTKEY) Address: 4007_6000h base + 304h offset = 4007_6304h Reserved Reset Reserved Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 877 Address: 4007_6000h base + 310h offset + (4d × i), where i=0d to 63d INSTR1 PAD1 OPRND1 Reset INSTR0 PAD0 OPRND0 Reset * Notes: • The reset values for LUT0 and LUT1 are 0818_0403h and 2400_1C08h respectively. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 878: Serial Flash Address Assignment
Any access to the address space between TOP_ADDR_MEMB1(T B1 (the first of the two independent TOP_ADDR_MEMB1 and TOP_ADDR_MEMA2 will be PADB1) routed to Serial Flash B1 flashes sharing the IOFB) Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 879: Flash Memory Mapped Amba Bus
TOP_ADDR_MEMB2 should be initialized/programmed to TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively (in effect, setting the size of these devices to 0). This would ensure that the complete memory map is assigned to only one flash device. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 880: Ahb Bus Access Considerations
Serial Flash Byte Address Access Access Device QSPI_AMBA_BASE + 0x00 0x00_0000 to 0x00_0003 QSPI_AMBA_BASE + 0x00 QSPI_AMBA_BASE + 0x04 0x00_0004 to 0x00_0007 … … … Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 881: Memory Mapped Serial Flash Data - Individual Flash Mode On Flash B
TOP_ADDR_MEMA2 + 0x04 0x00_0004 to 0x00_0007 … … … TOP_ADDR_MEMB1 - 0x08 (TOP_ADDR_MEMB1- TOP_ADDR_MEMA2 - 0x08) to TOP_ADDR_MEMB1 - 0x08 (TOP_ADDR_MEMB1 - TOP_ADDR_MEMA2 - 0x04 -0x01) Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 882: Ahb Rx Data Buffer (Qspi_Ardb0 To Qspi_Ardb31)
33.5.4.1/882 AHB RX Data Buffer register (ARDB4) 0000_0000h 33.5.4.1/882 AHB RX Data Buffer register (ARDB5) 0000_0000h 33.5.4.1/882 AHB RX Data Buffer register (ARDB6) 0000_0000h 33.5.4.1/882 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 883 RX Buffer, data read via register interface and AHB read, for the description of successive accesses to the RX Buffer content. Refer also to Byte Ordering of Serial Flash Read Data for the byte ordering scheme. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 884: Interrupt Signals
Serial Flash Command Error Logical OR from: ipi_int_cerr IPAEF Peripheral access while AHB busy Error IPIEF Peripheral Command could not be triggered Error IUEF Peripheral Command Usage Error Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 885: Functional Description
Compared to the standard SPI protocol, this communication method uses up to 4 bidirectional data lines operating at high data rates. The communication to the external serial flash device consists of an instruction code and optional address, mode, dummy MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 886 Write data on number of pads sepcified. The data size may size in bytes be overwritten by writing to the IDATSZ field of Configuration Register (QuadSPI_IPCR) register Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 887 QSPI_SFACR[CAS]. For sent(8'd8 example, if CAS is 3, then the address to flash will be [2:0] of means 8 bits Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 888 ADATSZ, as the locations greater than ADATSZ will never be used. For any MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 889 Once the high priority masters access completes, the suspended transaction is resumed (before any other AHB access is entertained). The status of the suspended buffer can be read from Sequence Suspend Status Register (QuadSPI_SPNDST). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 890 QSPI_BUFxCR[ADATSZ] or data size mentioned in the sequence pointed to by the SEQID field when ADATSZ is programmed as zero. A few examples are shown in the figure below: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 891 Each sequence can have a maximum of 8 instruction-operand pairs. The LUT can hold a maximum of 16 sequences. The figure below shows the basic structure of the sequence in the LUT. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 892 (QuadSPI_LCKCR). Note that this IPS transaction should immediately follow the above IPS transaction (no other IPS transaction can be issued in between). A successful write into this register unlocks the LUT. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 893 • Write the serial flash address to be used by the instruction into QSPI_SFAR, refer to Serial Flash Address Register (QSPI_SFAR). For IP Commands not related to specific addresses, the base address of the related flash need to be MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 894 3. Provide initial data for the program command into the circular buffer via register TX Buffer Data Register (QSPI_TBDR) . At least four word of data must be written into the TX Buffer up to a maximum of 32. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 895 Optionally it is possible to clear the RX Buffer pointer prior to triggering the IP Command by writing a 1 into the QuadSPI_MCR[CLR_RXF] field. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 896 QSPI_SR[BUSY] bit until the transaction is finished. The communication with the external serial flash is stopped when the specified number of entries has been filled. 2. Data Transfer from the QuadSPI Module Internal Buffers MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 897 In the IPS address space in the area associated to QSPI_RBDR0 to QSPI_RBDR31 In the AHB address space in the area associated to QSPI_ARDB0 to QSPI_ARDB31. Two successive entries are accessed with one single 64 bit AHB read operation. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 898 AHB interface would be stalled. As soon as the data from the requested address has been read by the QuadSPI module the AHB read access is served. So it is possible to run sequential reads from the AHB buffer at arbitrary speed without MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 899 For IP Commands the read size can be given in number of bytes. If this number is not a multiple of 4, then the last buffer entry is not completely filled with the missing higher numbered bytes at undefined values. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 900 AHB Illegal Transaction Error AITEF AHB Illegal Burst Size Error AIBSEF IP Command Trigger during AHB IPAEF Access Error IP Command Trigger could not be IPIEF executed Error IP Command related Transaction Finished MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 901 The Transmit Buffer Underrun indicates that an underrun condition in the TX Buffer has occurred. It is generated when a write instruction is triggered whilst the Tx Buffer is empty and the QSPI_RSER[TBUIE] bit is set. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 902 F's until the required number of bytes are not sent. This has been done to ensure that the software need not to erase whole sector after underrun, just reprogramming from MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 903 For example in Spansion memory, when the extended address register is updated with a value of 0x01 with the help of the command 17h, it will open Bank1 of the memory. The consequent 24-bit address MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 904: Hyperram Support
• If QuadSPI_MCR[VAR_LAT_EN] field is set, based on the status of RWDS from HyperRAM during Command/Address phase, QuadSPI includes additional initial access latency. If RWDS is high, QuadSPI will include twice + 1 the MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 905: Initialization/Application Information
QSPI_FR. Refer to the related descriptions how to set up the QuadSPI module appropriately. 33.8.2.1 IP Commands Refer to IP Configuration Register (QuadSPI_IPCR) for additional details not explicitly covered in this paragraph. • IP Commands - Normal Operation MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 906 • WRITE_DDR instruction Set when the module tried to push AHB Error Flag ABOF Flash transaction continues until it finishes data into the AHB buffer that Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 907 Buffer Related Error TBUF Note that only the buffer related errors are related to a transaction on the external serial flash. All the other errors do not trigger an actual transaction. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 908: Flash Device Selection
TX buffer fill rate. If this persists, it would eventually lead to an underrun. AHB Bus Side (data read): MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 909 The number of serial flash cycles can be determined in the following way: • Number of serial flash clock cycles required to read 4 bytes, corresponding to one RX Buffer entry (setup of command and address not considered): , 2 cycles for Octal MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 910 Note that the size of the minor loop is determined by the size of the QSPI_TBCT[WMRK] field, therefore the overhead given above distributes among (QSPI_TBCT[WMRK]+1) write accesses of 32 bit each. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 911 2. Not all flash devices support writes at 100Mhz. Please refer to the flash datasheet for the actual page program frequency supported. 3. The assumption for these timings is that the TX Fifo was full when the transaction was initiated 4. Individual flash mode. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 912: Byte Ordering - Endianness
B in the table signifies Byte and the index 1-8 refers to the byte position i.e. 1 refer to bits[7:0], 8 refer to bits[63:56] and so on. Table 33-26. Byte ordering configuration in AHB 64 bit BE 64 bit LE 32 bit BE 32 bit LE MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 913: Programming Flash Data
33.9.2 Reading Flash Data into the RX Buffer Reading the content from the same address provides the following sequence of bytes, identical to the write case: • 01…02…03…04…05…06…07…08 This results in the RX Buffer filled with: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 914: Reading Flash Data Into The Ahb Buffer
Reading the content from the same address as it was written to provides the following sequence of bytes, identical to the write case: • 01…02…03…04…05…06…07…08 This results in the AHB Buffer filled with: Table 33-30. Resulting AHB Buffer Content AHB Buffer Entry Content 64'h01_02_03_04_05_06_07_08 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 915: Driving Flash Control Signals In Single And Dual Mode
QuadSPI instruction set. Most common commands currently have the same instruction code for all vendors, however some commands are unique to specific vendors. Some example sequences are provided below. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 916 (2 bytes) data value, the software should ensure that when Hyperflash/HyperRAM is connected to the controller, the QSPI_SFACR [WA] bit must be set. If this bit is set the controller remaps a byte addressable access to a word addressable access. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 917 8 bit address 00h treated as command CMD_DDR 0x00 8 bit address 00h treated as command CMD_DDR 0xAA 8 bit address AAh treated as command Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 918 24 bit row address CADDR_DDR 0x10 16 bit column address with lower 3 bits valid rest 0 WRITE_DDR 2 bytes data written on 8 pads (D1D2) Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 919 Read 32 Bits on 2 pads in DDR mode JMP_ON_CS 0x00 Jump to instruction 0 (CMD) 33.11.1.6 Fast Read Quad Output (Winbond) The following table shows the Fast read quad output sequence for Winbond memories MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 920 Dual command page program = 0x02 on 2 pads ADDR 0x18 24 Addr bits to be sent on 2 pads WRITE 0x20 Write 32 Bytes on 2 pads STOP 0x00 STOP, Instruction over MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 921: Sampling Of Serial Flash Input Data
QuadSPI is used to read data from the serial flash device. Depending on the actual implementation, there is a delay between the internal clocking in the QuadSPI module and the external serial flash device. Refer to the following figure for an overview of this scheme. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 922: Supported Read Modes
QuadSPI internal reference clock. 33.12.2 Supported read modes Some modes listed here may not be available on this chip. See the chip-specific QuadSPI information for the read modes that this chip supports. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 923 I/2 above. The sampling point relevant for the internal sampling is configured in the QSPI_SMPR register. Refer to Sampling Register (QuadSPI_SMPR) for details. The following table gives an overview of the available configurations for the commands running at regular (full) speed: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 924 QuadSPI information for the read modes that this chip supports. Data sampling in SDR mode can be supported using the DQS sampling method. Refer to Data Strobe (DQS) sampling method for more details. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 925: Data Strobe (Dqs) Sampling Method
When using DQS for SDR reads, QuadSPI internally samples the incoming data on rising edge of the strobe signal. The figure below shows sampling read data in SDR mode using DQS. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 926 Internal Ref clock Data Strobe Signal Data Data sampled on both the edges of Data Strobe Signal Figure 33-11. Data Strobe functionality in DDR mode MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 927 Refer to the figure below for more detail. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 928: Data Input Hold Requirement Of Flash
QuadSPI, if it is 1, then, the data is aligned to 2x internal reference half clock. QSPI_FLSHCR[TDH] Internal Ref clock 2x Internal Ref clock Data aligned to internal Ref clock Data aligned to 2x half clock Figure 33-13. Data Hold MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 929: Introduction
The two primary modes of operation are Run, Stop. The Wait For Interrupt (WFI) instruction invokes Stop modes for the chip. The available power modes allow an application to consume only the power that is necessary for execution. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 930: Entering And Exiting Power Modes
The WFI instruction invokes stop modes for the chip. The processor exits the low-power mode via an interrupt. See Nested Vectored Interrupt Controller (NVIC) Configuration for a description of interrupt operation and which peripherals can cause interrupts. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 931: Clocking Modes
If configured, a DMA request (using the asynchronous DMA wake-up) can also be used to exit Stop for the duration of a DMA transfer before the chip transitions back into STOP2. 34.4.3 DMA wake-up MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 932 DMA wake-up) and can cause the SMC to assert its Stop Abort flag in case VLPS mode entry was happening. After the DMA wake-up completes, entry into low power mode starts. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 933: Compute Operation (Cpo)
The Private Peripheral Bus (PPB) — including the MCM, System Control Space (SCS) (for NVIC), and SysTick — remains accessible during CPO. Although access to the GPIO registers is supported, the GPIO port data input registers do not return valid MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 934: Peripheral Doze
(or CPO), instead of waiting for the bus masters to acknowledge the entry as part of the stop entry sequence. Finally, it can be used to disable selected bus masters or slaves that should remain inactive during a DMA wake-up. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 935: Power Mode Transitions
VLPR modes offer a lower power operating mode than normal modes. VLPR is limited in frequency. Figure 34-1. Power mode state transition diagram NOTE Figure 35-1 in the SMC chapter for more detailed mode transition conditions. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 936: Shutdown Sequencing For Power Modes
No FTFC commands of any type, including CSE commands (for CSEc parts), are available when the chip is in these modes. 34.8 Module operation in available power modes Table 34-4 illustrates module functionality in each of the available modes. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 937 LPO Clock as needs to be source) set) STOP1, FF in STOP2 FF (LPO Clock as Static in source) STOP1, FF in STOP2 Clocks 128 kHz LPO Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 938 EEPROM Emulation and write read and write) write) operation can operation). Only be done. No read operation can FTFC be done. No FTFC commands. commands. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 939 STOP1, FF in STOP2 FF (Only SIRC as source) LPTMR FF (Only SIRC as Async Async operation a source) operation in STOP1, FF in STOP2 Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 940: Quadspi Operation
QuadSPI, then the on chip voltage monitor ensures the operation as per the specifications present in the WCT101xS Datasheet (See table LVR, LVD and POR operating requirements). MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 941: Introduction
The following table shows the translation between the Arm CPU mode and the MCU power modes. RUN is mapped to RUN/VLPR and Deep Sleep is mapped to STOP/VLPS. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 942 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. NOTE If the system clock is changed during the mode transition, the recommendation is to stall the communications for all the peripherals. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 943: Memory Map And Register Descriptions
Stop Control Register (SMC_STOPCTRL) 0000_0003h 35.3.5/949 4007_E014 Power Mode Status register (SMC_PMSTAT) 0000_0001h 35.3.6/950 35.3.1 SMC Version ID Register (SMC_VERID) Address: 4007_E000h base + 0h offset = 4007_E000h MAJOR MINOR FEATURE Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 944: Smc Parameter Register (Smc_Param)
Feature Specification Number This read only field returns the feature set number. 0x0000 Standard features implemented 35.3.2 SMC Parameter Register (SMC_PARAM) Address: 4007_E000h base + 4h offset = 4007_E004h Reset Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 945: Power Mode Protection Register (Smc_Pmprot)
For example, if the MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is still in Normal Run mode. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 946 This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 947: Power Mode Control Register (Smc_Pmctrl)
Chip POR. It is unaffected by reset types that do not trigger Chip POR. See the Reset section details for more information. Address: 4007_E000h base + Ch offset = 4007_E00Ch Reset RUNM STOPM Reset MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 948 NOTE: When set to STOP, the STOPO bits in the STOPCTRL register must be used to select the variants of stop - STOP1/STOP2. Normal Stop (STOP) Reserved Very-Low-Power Stop (VLPS) Reserved Reserved Reseved Reserved MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 949: Stop Control Register (Smc_Stopctrl)
In STOP2, only system clocks are gated allowing peripherals running on bus clock to remain fully functional. In STOP1, both system and bus clocks are gated. Reserved Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 950: Power Mode Status Register (Smc_Pmstat)
This read-only field is reserved and always has the value 0. PMSTAT Power Mode Status NOTE: When debug is enabled, the PMSTAT will not update to STOP or VLPS Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 951: Functional Description
The following figure shows the power mode state transitions available on the chip. Any reset always brings the MCU back to the normal RUN state. Figure 35-1. Power mode state diagram MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 952: Power Mode Entry/Exit Sequencing
The SMC manages the system's entry into and exit from all power modes. This diagram illustrates the connections of the SMC with other system components in the chip that are necessary to sequence the system through all power modes. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 953 STOP2 mode bus clocks will not be gated. 5. Additionally, for VLPS mode, clock generators are disabled in the SCG unless configured to be enabled. See for the programming options. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 954 VLPS abort). It is to be noted here that the VLPS abort is happening due to interrupt while VLPS re-entry, there is no error or data loss in DMA transfer. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 955: Run Modes
• The processor reads the start SP (SP_main) from vector-table offset 0x000 • The processor reads the start PC from vector-table offset 0x004 • LR is set to 0xFFFF_FFFF. To reduce power in this mode, disable the clocks to unused modules. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 956 • The ratio of frequency between HSRUN mode and RUN mode for each system, bus, and flash clocks respectively must be less than or equal to 3. • Stop mode entry is not supported from HSRUN. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 957: Stop Modes
STOP mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the Arm core. The SCG module can be configured to leave the reference clocks running. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 958: Debug In Low Power Modes
When both requests are asserted, the mode controller handles attempts to enter STOP and VLPS by entering an emulated stop state. In this emulated stop state: • the regulator is in run regulation, • the SCG-generated clock source is enabled, MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 959 Chapter 35 System Mode Controller (SMC) • all system clocks, except the core clock, are disabled, • the debug module has access to core registers, and • access to the on-chip peripherals is blocked. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 960 Functional description MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 961: Chip-Specific Pmc Information
• Active POR providing brown-out detect • Low voltage reset (LVR) • Low voltage detect supporting two low voltage trip points and interrupt • Low power oscillator (LPO) with a typical frequency of 128 kHz MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 962: Modes Of Operation
). The LVWF bit is cleared by writing one to the LVWACK bit, but only if the internal supply has returned above the trip point; otherwise, the LVWF bit remains set. This flag gets cleared on reset. The flag is only valid after the device has come MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 963: Low Voltage Reset (Lvr) Operation
LVWF is set. LVWF is cleared by writing one to the PMC_LVDSC2[LVWACK] bit, when the supply returns to above the trip point. 36.6 Memory Map and Register Definition This sections provides the detailed information of all registers for the PMC module. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 964: Pmc Register Descriptions
This register contains status and control bits to support the low voltage detect function. NOTE When the internal voltage regulator is in lowe power mode, the LVD system is disabled, regardless of the PMC_LVDSC1 settings. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 965 1b - If the supply voltage falls below V , a system reset will be generated. Reserved — 36.6.1.3 Low Voltage Detect Status and Control 2 Register (LVDSC2) 36.6.1.3.1 Offset Register Offset LVDSC2 MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 966 This bit enables hardware interrupt requests for LVWF. 0b - Hardware interrupt disabled (use polling) 1b - Request a hardware interrupt when LVWF=1 Reserved — 36.6.1.4 Regulator Status and Control Register (REGSC) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 967 This read-only bit provides the current status of the internal voltage regulator. 0b - Regulator is in low power mode or transition to/from 1b - Regulator is in full performance mode Clock Bias Disable Bit CLKBIASDIS Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 968 Table 36-1. Trimming effect of LPOTRIM[4:0] LPOTRIM[4:0] Decimal Period of LPO clock 10000 –16 lowest 10001 –15 increasing 11110 –2 11111 –1 00000 typical 128 kHz 00001 increasing 01110 01111 highest MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 969 1. Automatically loaded from flash memory IFR after any reset. 36.6.1.5.4 Fields Field Function Reserved — LPO trimming bits LPOTRIM These bits are used for trimming the frequency of the low power oscillator. See the table above for trimming effect. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 970 Memory Map and Register Definition MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 971: Instantiation Information
100 LQFP 100 BGA WCT1016S 100 BGA ADCx_SC1n[ADCH] bit field configurations for a chip are as per the maximum channel configuration for that chip across packages as mentioned in the below table: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 972: Adc Connections/Channel Assignment
WCT101xS. See the below table for register implementation. Table 37-4. WCT101xS register implementation Register/Offset WCT1014S WCT1015S WCT1016S aSC1A - aSC1P/108 -144 Reserved/Not Available/Implemented Available/Implemented implemented Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 973: Dma Support On Adc
• ADC0_SE4 and ADC1_SE14 channels are interleaved on PTB0 pin • ADC0_SE5 and ADC1_SE15 channels are interleaved on PTB1 pin • ADC1_SE8 and ADC0_SE8 channels are interleaved on PTB13 pin • ADC1_SE9 and ADC0_SE9 channels are interleaved on PTB14 pin MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 974: Adc Internal Supply Monitoring
ADC0_SC1n[ADCH] as 010101b). Please refer to SIM_CHIPCTL[ADC_SUPPLY] and SIM_CHIPCTL[ADC_SUPPLYEN] bits. 37.6 ADC Reference Options The ADC supports the following references: • VREFH/VREFL - connected as the primary reference option • VALTH/VREFL - connected as an alternate reference option MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 975: Adc Trigger Sources
• The SIM_ADCOPT[ADCxTRGSEL] field is used to control the ADC triggering source/scheme. • When ADCxTRGSEL=0, the ADC pre-trigger comes from PDB directly. • When ADCxTRGSEL=1, the ADC pre-trigger comes from TRGMUX, as in the case of LPIT. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 976 Trigger Latching and Arbitration Unit* * The block depicts simplified schematic and doesn’t show detailed latching. See section 'Trigger Latching and Arbitration' of ADC chapter for details Figure 37-2. ADC0_PDB0 ADC Triggering scheme example MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 977: Pdb Triggering Scheme
ADHWT trigger_in0 Trigger_source_A ADHWTS A:P PDB0 ADC0 ADC_SC1A:P[COCO] Configured using TRGMUX_PDB0 ADHWT Trigger_source_B trigger_in0 PDB1 ADHWTS A:P ADC1 Configured using TRGMUX_PDB1 ADC_SC1A:P[COCO] Figure 37-3. ADCs triggering with independent sources Case 2: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 978: Trgmux Trigger Scheme
(trigger and pretrigger source). Changing of trigger source can be done anytime by any of the two ways below. Way 1 1. Stop the current trigger generation unit . MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 979: Trigger Latching And Arbitration
Pth request is processed [0 < P <(N-1)], searching will resume with (P +1), followed by (P+2), until the next latched request is found. This searching then rolls over to 0 after (N-1)th trigger and continues until P is reached. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 980 Reselect the trigger source for the trigger handler block (configuration for this resides in a separate module on the chip; refer to the SIM_ADCOPT register in the SIM chapter). Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 981: Adc Triggering Configurations
PDB triggering on channels 0 to 3 or only TRGMUX path on channel 0 to 3. When using direct triggering scheme through PDB, the pretriggers should be minimum 4 bus clock cycles apart. Accordingly, following table shows the ADC triggering configurations and behavior: MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 982 1. Zero delay configured: Trigger is not raised. The sequence error is reported on both the channels. The ADC result register consists of junk information. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 983 Direct Triggering on channel number 4 onwards through same PDB channel: Sequence error for second conversion, COCO might be received or might not. Both the conversion results are invalid. Figure 37-6. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 984 Sequence error for second conversion is reported, COCO will be received for both channels. Both the conversion results are valid. This is due to the virtue of trigger latching gasket, which latches the trigger requests. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 985 Direct Triggering on channel number 4 onwards through same PDB channel: Sequence error for second conversion, COCO will not be received. First conversion results are valid and second conversion results are invalid. Figure 37-9. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 986 Sequence error for second conversion is reported, COCO will be received for both channels. Both the conversion results are valid. This is due to the virtue of trigger latching gasket, which latches the trigger requests. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 987 Chapter 37 ADC Configuration Figure 37-11. 4. Delay configured is greater than ADC conversion time: No sequence error, Both COCOs received. Both conversions are valid. Figure 37-12. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 988: Adc Low-Power Modes
TRGMUX_FTMn TRGMUX_PDBx ADC_R5 ch0_pretrig6 ADHWTS G pretrig6 ADC_R6 ch0_pretrig7 ADHWTS H pretrig7 ADC_R7 ACK[0:15] ADC_SC1 A:H [COCO] DMA_REQ INTERRUPT Figure 37-13. PWM Load Diagnosis – ADC Trigger Concept (block diagram) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 989 Chapter 37 ADC Configuration FTM_init_trig PDB_trigger_in0 PDB_ch0_pretrigger0/ADHWTS A PDB_ch0_pretrigger1/ADHWTS B ADC channel selection PDB_ch0_pretrigger2/ADHWTS C PDB_ch0_pretrigger3/ADHWTS D PDB_ch0_trigger/ADHWT ADHWT Figure 37-14. Example: PWM Load Diagnosis – ADC Trigger Concept 1 (Timing) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 990: Adc Calibration Scheme
37.13 ADC calibration scheme After a POR, and after the flash memory has been made available, the ADC calibration must be executed by use of the CAL bit in the ADC_SC3 control register. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 991 Since the power is continuous in all of the device power modes (STOP2 RUN, and HSRUN), all of the ADC specifications are maintained as per the data sheet. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 992 ADC calibration scheme MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 993: Chip-Specific Adc Information
• Conversion complete/hardware average complete flag and interrupt • Input clock selectable from up to four sources • Operation in low-power modes for lower noise • Selectable hardware conversion trigger with hardware channel select MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 994: Block Diagram
Formatting CFG1,2 REFH ALTH tra n s fe r A C F E Compare ACFGT, ACREN REFL Compare true logic C V1 C V 2 CV1:CV2 Figure 38-1. ADC block diagram MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 995: Adc Signal Descriptions
.statement If externally available, connect the V pin to the same voltage potential as V 38.3.3 Voltage Reference Select and V are the high and low reference voltages for the ADC module. REFSH REFSL MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 996: Analog Channel Inputs (Adx)
Access Reset value (In bits) 0h - 3Ch ADC Status and Control Register 1 (SC1A - SC1P) 0000_003Fh (alias) ADC Configuration Register 1 (CFG1) 0000_0000h Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 997 ADC Status and Control Register 1 (SC1U) 0000_003Fh 15Ch ADC Status and Control Register 1 (SC1V) 0000_003Fh 160h ADC Status and Control Register 1 (SC1W) 0000_003Fh Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 998: Adc Status And Control Register 1 (Sc1A - Asc1P)
38.4.2 ADC Status and Control Register 1 (SC1A - aSC1P) 38.4.2.1 Offset For a = A to P (0 to 15): Register Offset SC1a 0h + (a × 4h) aSC1a (alias for SC1a) 108h + (a × 4h) MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 999 SC1BSC1n registers do not initiate a new conversion. 38.4.2.3 Diagram Bits Reset Bits Reset 38.4.2.4 Fields Field Function 31-8 Reserved — Conversion Complete Flag Table continues on the next page... MWCT101xS Series Reference Manual, Rev. 3, 07/2019 NXP Semiconductors...
Page 1000 001011b - External channel 11 is selected as input. 001100b - External channel 12 is selected as input. 001101b - External channel 13 is selected as input. 001110b - External channel 14 is selected as input. MWCT101xS Series Reference Manual, Rev. 3, 07/2019 1000 NXP Semiconductors...

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