Icom IC-2SA Service Manual page 9

4-2-4 АРС CIRCUIT (MIN AND АРС UNITS)
The APC circuit protects the power module (ІСІ) from
a mismatched output load and selects HIGH and LOW
output power.
The output power level from the power module (ІСТ) is
detected at the APC detector (D10~D12). When antenna
impedance is matched at 50 Q, the detected level is
at a minimum. However, when antenna impedance is
mismatched, the detected voltage is higher than when
matched.
When the antenna impedance is mismatched, the base
voltage of Q3b (APC UNIT) is higher than the other base
voltage of Q3a (reference voltage). ОЗЬ decreases the
collector current of Q1 using Q2. Collector current of
Q1 is used at the drive amplifiers (Q6, Q7) on the
MIN UNIT. Hence, when the antenna impedance is
mismatched, the output power is decreased.
The output power selecting circuit uses the APC circuit.
The PCON voltage from the IO UNIT shifts the reference
voltage, changing the output power to HIGH or LOW
1—3.
4-2-5 ANTENNA SWITCHING CIRCUIT
(MIN UNIT)
When transmitting, 07 and D9 are turned ON. The ВЕ
output signal is not applied to the receiver circuit, passing
through D9 and C60, the low-pass filter (L2~L4, C21
~C25) and then to the antenna. The low-pass filter
suppresses high harmonic components.
PLL CIRCUIT
ІСІ M54959FP
PROGRAM-
MABLE
COUNTER
23
x
рач
4-3-4 VCO CIRCUIT (PLL UNIT)
IC-2SA/SE has 2 VCO circuits for transmitting and
receiving. IC1 pins 10 and 11 output control signals
for selecting the receive VCO circuit (Q1, L1, D1) or
transmit VCO circuit (Q2, 12, 02). Varactor diodes (D1,
D2) provide frequency control. The buffer amplifiers
(Q3~Q5) do not affect the PLL output signal from VCO
oscillation. Q7 selects the transmit or receive VCO
circuit.
, PHASE CHARGE LOOP
DIVIDER m DETECTOR ET PUMP H FILTER
4-3 PLL CIRCUITS
4-3-1 GENERAL (PLL UNIT)
The PLL circuit, using a one chip modulus prescaler (IC1),
directly generates the transmit frequency with the Tx
VCO (Q2) and the 1st LO frequency with the Rx VCO (Q1).
The modulus prescaler (IC1) sets the dividing ratio based
on serial data from the CPU, and compares the phases
of a VCO signal and the reference oscillator frequency.
It detects the out-of-step phase and outputs it. Тһе
reference frequency is oscillated at X1.
4-3-2 REFERENCE OSCILLATOR CIRCUIT
(PLL UNIT)
A reference frequency is produced by the local oscillator
section ої ІСІ and X1. C22 provides frequency control.
4-3-3 LOOP FILTER CIRCUIT (PLL UNIT)
Phase-detected signals from IC1 pin 13 are converted to
DC voltage by a lag-lead loop filter (R17, R18, C28, C29).
The frequency at which the VCO oscillates is controlled
by varactor diodes (01, 02). ОС voltage (PLL lock
voltage) is provided through the buffer amplifier (Q6).
Q10 provides Rx bandpass filter tuning.
BUFFER
Q4
PLL
OUTPUT
BUFFER BUFFER
Q3 Q5
4-3-5 UNLOCK SENSOR CIRCUIT (PLL UNIT)
When the PLL circuit is unlocked, IC1 pin 14 is "HIGH"
and the "HIGH" signal is applied to the CPU pin 7 as an
uniock signal.