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Cypress Semiconductor enCoRe II CY7C63310 Manual

Low speed usb peripheral controller
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1. Features
USB 2.0-USB-IF certified (TID # 40000085)
■
enCoRe™ II USB - "enhanced Component Reduction"
■
Crystalless oscillator with support for an external clock. The
❐
internal oscillator eliminates the need for an external crystal
or resonator.
Two internal 3.3V regulators and an internal USB pull up
❐
resistor
Configurable IO for real world interface without external com-
❐
ponents
USB Specification compliance
■
Conforms to USB Specification, Version 2.0
❐
Conforms to USB HID Specification, Version 1.1
❐
Supports one low speed USB device address
❐
Supports one control endpoint and two data endpoints
❐
Integrated USB transceiver with dedicated 3.3V regulator for
❐
USB signalling and D– pull up.
Enhanced 8-bit microcontroller
■
Harvard architecture
❐
M8C CPU speed is up to 24 MHz or sourced by an external
❐
clock signal
Internal memory
■
Up to 256 bytes of RAM
❐
Up to eight Kbytes of Flash including EEROM emulation
❐
Interface can auto configure to operate as PS/2 or USB
■
No external components for switching between PS/2 and
❐
USB modes
No General Purpose IO (GPIO) pins required to manage dual
❐
mode capability
Low power consumption
■
Typically 10 mA at 6 MHz
❐
10 μA sleep
❐
In system reprogrammability:
■
Allows easy firmware update
❐
GPIO ports
■
Up to 20 GPIO pins
❐
2 mA source current on all GPIO pins. Configurable 8 or
❐
50 mA/pin current sink on designated pins.
Each GPIO port supports high impedance inputs, config-
❐
urable pull up, open drain output, CMOS/TTL inputs, and
CMOS output
Maskable interrupts on all IO pins
❐
A dedicated 3.3V regulator for the USB PHY. Aids in signalling
■
and D– line pull up
Cypress Semiconductor Corporation
Document 38-08035 Rev. *K
Low Speed USB Peripheral Controller
125 mA 3.3V voltage regulator powers external 3.3V devices
■
3.3V IO pins
■
4 IO pins with 3.3V logic levels
❐
Each 3.3V pin supports high impedance input, internal pull
❐
up, open drain output or traditional CMOS output
SPI serial communication
■
Master or slave operation
❐
Configurable up to 4 Mbit/second transfers in the master
❐
mode
Supports half duplex single data line mode for optical sensors
❐
2-channel 8-bit or 1-channel 16-bit capture timer registers.
■
Capture timer registers store both rising and falling edge times.
Two registers each for two input pins
❐
Separate registers for rising and falling edge capture
❐
Simplifies the interface to RF inputs for wireless applications
❐
Internal low power wakeup timer during suspend mode:
■
Periodic wakeup with no external components
❐
12-bit Programmable Interval Timer with interrupts
■
Advanced development tools based on Cypress PSoC® tools
■
Watchdog timer (WDT)
■
Low voltage detection with user configurable threshold
■
voltages
Operating voltage from 4.0V to 5.5V DC
■
Operating temperature from 0–70°C
■
Available in 16 and 18-pin PDIP; 16, 18, and 24-pin SOIC;
■
24-pin QSOP, and 32-pin QFN packages
Industry standard programmer support
■
1.1 Applications
The CY7C63310/CY7C638xx is targeted for the following
applications:
PC HID devices
■
Mice (optomechanical, optical, trackball)
❐
Gaming
■
Joysticks
❐
Game pad
❐
General purpose
■
Barcode scanners
❐
POS terminal
❐
Consumer electronics
❐
Toys
❐
Remote controls
❐
Security dongles
❐
•
198 Champion Court
CY7C63310, CY7C638xx
,
•
San Jose
CA 95134-1709
Revised December 08 2008
enCoRe™ II
•
408-943-2600
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Summary of Contents for Cypress Semiconductor enCoRe II CY7C63310

  • Page 1 1. Features USB 2.0-USB-IF certified (TID # 40000085) ■ enCoRe™ II USB - “enhanced Component Reduction” ■ Crystalless oscillator with support for an external clock. The ❐ internal oscillator eliminates the need for an external crystal or resonator. Two internal 3.3V regulators and an internal USB pull up ❐...

  • Page 2: Logic Block Diagram

    2. Logic Block Diagram Low-Speed USB/PS2 3.3V Transceiver Regulator and Pull up Internal 24 MHz Oscillator Clock Control External Clock POR / Low-Voltage Detect Document 38-08035 Rev. *K Up to 14 Low-Speed Interrupt 4 3VIO/SPI Extended USB SIE Control Pins IO Pins Flash M8C CPU...
  • Page 3 3. Introduction Cypress has reinvented its leadership position in the low speed USB market with a new family of innovative microcontrollers. Introducing enCoRe II USB - “enhanced Component Reduction.” Cypress has leveraged its design expertise in USB solutions to advance its family of low speed USB microcontrollers, which enable peripheral developers to design new products with a minimum number of components.
  • Page 4 5. Pinouts CY7C63801, CY7C63310 16-Pin PDIP P1.2 SSEL/P1.3 SCLK/P1.4 P1.1/D– SMOSI/P1.5 SMISO/P1.6 P1.0/D+ TIO1/P0.6 TIO0/P0.5 P0.0 P0.1 INT2/P0.4 P0.2/INT0 INT1/P0.3 CY7C63813 18-Pin PDIP SSEL/P1.3 SCLK/P1.4 SMOSI/P1.5 SMISO/P1.6 P1.7 P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 CY7C63823 24-Pin QSOP P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 P0.1 P0.0...
  • Page 5 Table 5-1. Die Pad Summary Pad Number Pad Name P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 CLKIN P2.1 P2.0 PI.0 D+ P1.1 D– P1.2 VREG P1.3 P3.0 P3.1 P1.4 P1.5 SMOSI P1.6 SMISO P1.7 Reserved Document 38-08035 Rev. *K Figure 5-2.
  • Page 6 Table 5-2. Pin Description SOIC SIOC PDIP QSOP Note 1. P1.0(D+) and P1.1(D–) pins must be in IO mode when used as GPIO and in I Document 38-08035 Rev. *K Name SOIC PDIP P3.0 GPIO Port 3. Configured as a group (byte). P3.1 P2.0 GPIO Port 2.

  • Page 7: Cpu Architecture

    Table 5-2. Pin Description (continued) SOIC SIOC PDIP QSOP 6. CPU Architecture This family of microcontrollers is based on a high performance, 8-bit, Harvard architecture microprocessor. Five registers control the primary operation of the CPU core. These registers are affected by various instructions, but are not directly accessible through the register space by the user.

  • Page 8: Cpu Registers

    7. CPU Registers The CPU registers in enCoRe II devices are in two banks with 256 registers in each bank. Bit[4]/XIO bit in the CPU Flags register must be set/cleared to select between the two register banks 7.1 Flags Register The Flags Register is set or reset only with logical instruction.

  • Page 9: Addressing Modes

    Table 7-3. CPU X Register (CPU_X) Bit # Field – – Read/Write Default Bit [7:0]: X [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode. Table 7-4. CPU Stack Pointer Register (CPU_SP) Bit # Field –...
  • Page 10 7.2.2 Source Direct The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is an address that points to a location in the RAM memory space or the register space that is the source of the instruction.
  • Page 11 7.2.6 Destination Direct Source Immediate The result of an instruction using this addressing mode is placed within the RAM memory space or the register space. Operand 1 is the address of the result. The source of the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources;...

  • Page 12: Instruction Set Summary

    8. Instruction Set Summary The instruction set is summarized in Table 8-1 Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on the Cypress web site at http://www.cypress.com). Table 8-1. Instruction Set Summary Sorted Numerically by Opcode Order Instruction Format Flags 00 15...

  • Page 13: Memory Organization

    9. Memory Organization 9.1 Flash Program Memory Organization Figure 9-1. Program Memory Space with Interrupt Vector Table after reset 16-bit PC Document 38-08035 Rev. *K Address 0x0000 Program execution begins here after a reset 0x0004 POR/LVD 0x0008 INT0 0x000C SPI Transmitter Empty 0x0010 SPI Receiver Full 0x0014...
  • Page 14 9.2 Data Memory Organization The CY7C63310/638xx microcontrollers provide up to 256 bytes of data RAM. after reset 8-bit PSP Top of RAM Memory 9.3 Flash This section describes the Flash block of the enCoRe II. Much of the user visible Flash functionality including programming and security are implemented in the M8C Supervisory Read Only Memory (SROM).
  • Page 15 Two important variables that are used for all functions are KEY1 and KEY2. These variables are used to help discriminate between valid SSCs and inadvertent SSCs. KEY1 must always have a value of 3Ah, while KEY2 must have the same value as the stack pointer when the SROM function begins execution.
  • Page 16 9.5.3 WriteBlock Function The WriteBlock function is used to store data in the Flash. Data is moved 64 bytes at a time from SRAM to Flash using this function. The WriteBlock function first checks the protection bits and determines if the desired BLOCKID is writable. If write protection is turned on, the WriteBlock function exits setting the accumulator and KEY2 back to 00h.
  • Page 17 Table 9-8. ProtectBlock Parameters Name Address Description KEY1 0,F8h KEY2 0,F9h Stack Pointer value when SSC is executed. CLOCK 0,FCh Clock divider used to set the write pulse width. DELAY 0,FEh For a CPU speed of 12 MHz set to 56h. 9.5.6 EraseAll Function The EraseAll function performs a series of steps that destroy the user data in the Flash macros and resets the protection block in...
  • Page 18 Silicon ID Table 0 [15-8] Family/ Table 1 Die ID Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 The Silicon IDs for enCoRe II devices are stored in SROM tables in the part, as shown in The Silicon ID can be read out from the part using SROM Table reads (Table 0).
  • Page 19 9.5.8 Checksum Function The Checksum function calculates a 16-bit checksum over a user specifiable number of blocks, within a single Flash macro (Bank) starting from block zero. The BLOCKID parameter is used to pass in the number of blocks to calculate the checksum over.
  • Page 20 CLK_EXT CLK_24MHz Document 38-08035 Rev. *K Figure 10-1. Clock Block Diagram CPUCLK SCALE (divide by 2 n = 0-5,7) CLK_USB 24 MHz SCALE SCALE 12 MHz 12 MHz EXT/2 LP OSC CLK_32 32 KHz CY7C63310, CY7C638xx CPU_CLK Page 20 of 83 [+] Feedback [+] Feedback...
  • Page 21 10.1 Clock Architecture Description The enCoRe II clock selection circuitry allows the selection of independent clocks for the CPU, USB, Interval Timers and Capture Timers. The CPU clock CPUCLK is sourced from an external clock or the Internal 24 MHz Oscillator. The selected clock source is optionally divided by 2 , where n is 0-5,7 (see 23).
  • Page 22 Table 10-2. LPOSC Trim (LPOSCTR) [0x36] [R/W] Bit # 32 kHz Low Reserved Field Power – Read/Write Default This register is used to calibrate the 32 kHz Low speed Oscillator. The reset value is undefined but during boot the SROM writes a calibration value that is determined during manufacturing tests.
  • Page 23 Table 10-4. OSC Control 0 (OSC_CR0) [0x1E0] [R/W] Bit # Reserved Field – – Read/Write Default Bit [7:6]: Reserved Bit 5: No Buzz During sleep (the Sleep bit is set in the CPU_SCR on periodically to detect any POR and LVD events on the V the duty cycle—Table 13-3 on page 32).
  • Page 24 Table 10-5. USB Osclock Clock Configuration (OSCLCKCR) [0x39] [R/W] Bit # Field – – Read/Write Default This register is used to trim the Internal 24 MHz Oscillator using received low speed USB packets as a timing reference. The USB Osclock circuit is active when the Internal 24 MHz Oscillator provides the USB clock. Bit [7:2]: Reserved Bit 1: Fine Tune Only 0 = Fine and Course tuning...
  • Page 25 10.1.1 Interval Timer Clock (ITMRCLK) The Interval Timer Clock (TITMRCLK), is sourced from an external clock, the Internal 24 MHz Oscillator, the Internal 32 kHz Low power Oscillator, or the Timer Capture clock. A programmable prescaler of 1, 2, 3 or 4 then divides the selected source.
  • Page 26 Captimer Clock Table 10-7. Clock IO Config (CLKIOCR) [0x32] [R/W] Bit # Field – – Read/Write Default Bit [7:2]: Reserved Bit [1:0]: CLKOUT Select 0 0 = Internal 24 MHz Oscillator 0 1 = External clock – external clock at CLKIN (P0.0) 1 0 = Internal 32 kHz low power oscillator 1 1 = CPUCLK 10.2 CPU Clock During Sleep Mode...
  • Page 27 11. Reset The microcontroller supports two types of resets: Power on Reset (POR) and Watchdog Reset (WDR). When reset is initiated, all registers are restored to their default states and all interrupts are disabled. The occurrence of a reset is recorded in the System Status and Control Register (CPU_SCR). Bits within this register record the occurrence of POR and WDR Reset respectively.

  • Page 28: Sleep Mode

    11.1 Power on Reset POR occurs every time the power to the device is switched on. POR is released when the supply is typically 2.6V for the upward supply transition, with typically 50 mV of hysteresis during the power on transient. Bit 4 of the System Status and Control Register (CPU_SCR) is set to record this event (the register contents are set to 00010000 by the POR).

  • Page 29: Wake Up Sequence

    12.1 Sleep Sequence The SLEEP bit is an input into the sleep logic circuit. This circuit is designed to sequence the device into and out of the hardware sleep state. The hardware sequence to put the device to sleep is shown in Figure 12-1.
  • Page 30 12.3 Low Power in Sleep Mode To achieve the lowest possible power consumption during suspend or sleep, the following conditions must be observed in addition to considerations for the sleep timer: 1. All GPIOs must be set to outputs and driven low. 2.
  • Page 31 13. Low Voltage Detect Control Table 13-1. Low Voltage Control Register (LVDCR) [0x1E3] [R/W] Bit # Reserved Field – – Read/Write Default This register controls the configuration of the Power on Reset/Low voltage Detection block. Note This register exists in the second bank of IO space. This requires setting the XIO bit in the CPU flags register. Bit [7:6]: Reserved Bit [5:4]: PORLEV[1:0] This field controls the level below which the precision power on reset (PPOR) detector generates a reset.
  • Page 32 Table 13-2. Voltage Monitor Comparators Register (VLTCMP) [0x1E4] [R] Bit # Field – – Read/Write Default This read only register allows reading the current state of the Low-Voltage-Detection and Precision-Power-On-Reset compar- ators Bit [7:2]: Reserved Bit 1: LVD This bit is set to indicate that the low-voltage-detect comparator has tripped, indicating that the supply voltage has gone below the trip point set by VM[2:0] (See Table 13-1)

  • Page 33: Port Data Registers

    14. General Purpose IO (GPIO) Ports 14.1 Port Data Registers Table 14-1. P0 Data Register (P0DATA)[0x00] [R/W] Bit # P0.7 P0.6/TIO1 Field Read/Write Default This register contains the data for Port 0. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register returns the current state of the Port 0 pins.
  • Page 34 Table 14-2. P1 Data Register (P1DATA) [0x01] [R/W] Bit # P1.7 P1.6/SMISO Field Read/Write Default This register contains the data for Port 1. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register returns the current state of the Port 1 pins. Bit 7: P1.7 Data P1.7 only exists in the CY7C638xx.
  • Page 35 14.2 GPIO Port Configuration All the GPIO configuration registers have common configuration controls. The following are the bit definitions of the GPIO configuration registers. 14.2.1 Int Enable When set, the Int Enable bit allows the GPIO to generate interrupts. Interrupt generate can occur regardless of whether the pin is configured for input or output.
  • Page 36 3.3V Drive Pull-Up Enable Output Enable Open Drain Port Data High Sink Data In TTL Threshold Table 14-5. P0.0/CLKIN Configuration (P00CR) [0x05] [R/W] Bit # Reserved Int Enable Field Read/Write Default This pin is shared between the P0.0 GPIO use and the CLKIN pin for an external clock. When the external clock input is enabled (Bit[0] in register CPUCLKCR Table 10-3 on page 22) the settings of this register are ignored.
  • Page 37 Table 14-7. P0.2/INT0–P0.4/INT2 Configuration (P02CR–P04CR) [0x07–0x09] [R/W] Bit # Reserved Field – – Read/Write Default These registers control the operation of pins P0.2–P0.4 respectively. The pins are shared between the P0.2–P0.4 GPIOs and the INT0–INT2. These registers exist in all enCoRe II parts. The INT0–INT2 interrupts are different from all the other GPIO interrupts.
  • Page 38 Table 14-9. P0.7 Configuration (P07CR) [0x0C] [R/W] Bit # Reserved Int Enable Field – Read/Write Default This register controls the operation of pin P0.7. The P0.7 pin only exists in the CY7C638(1/2/3)3. Table 14-10. P1.0/D+ Configuration (P10CR) [0x0D] [R/W] Bit # Reserved Int Enable Field...
  • Page 39 Table 14-13. P1.3 Configuration (P13CR) [0x10] [R/W] Bit # Reserved Int Enable Field – Read/Write Default This register controls the operation of the P1.3 pin. This register exists in all enCoRe II parts. The P1.3 GPIO’s threshold is always set to TTL. When the SPI hardware is enabled or disabled, the pin is controlled by the Output Enable bit and the corresponding bit in the P1 data register.

  • Page 40: Serial Peripheral Interface (Spi)

    Table 14-17. P3 Configuration (P3CR) [0x16] [R/W] Bit # Reserved Int Enable Field – Read/Write Default This register exists in CY7C638(2/3)3. This register controls the operation of pins P3.0–P3.1. 15. Serial Peripheral Interface (SPI) The SPI Master/Slave Interface core logic runs on the SPI clock domain, so that its functionality is independent of system clock speed. SPI is a four pin serial interface comprised of a clock, an enable and two data pins.
  • Page 41 15.2 SPI Configure Register Table 15-2. SPI Configure Register (SPICR) [0x3D] [R/W] Bit # Swap LSB First Field Read/Write Default Bit 7: Swap 0 = Swap function disabled. 1 = The SPI block swaps its use of SMOSI and SMISO. This is useful in implementing single wire communications similar to SPI. Bit 6: LSB First 0 = The SPI transmits and receives the MSB (Most Significant Bit) first.
  • Page 42 15.3 SPI Interface Pins The SPI interface uses the P1.3–P1.6 pins. These pins are configured using the P1.3 and P1.4–P1.6 Configuration. Table 15-4. SPI Mode Timing vs. LSB First, CPOL and CPHA LSB First CPHA CPOL S C L K S S E L D A T A M S B...

  • Page 43: Timer Registers

    16. Timer Registers All timer functions of the enCoRe II are provided by a single timer block. The timer block is asynchronous from the CPU clock. 16.1 Registers 16.1.1 Free Running Counter The 16 bit free-running counter is clocked by the Timer Capture Clock (TCAPCLK). It is read in software for use as a general purpose time base.
  • Page 44 Table 16-3. Timer Capture 0 Rising (TIO0R) [0x22] [R/W] Bit # Field Read/Write Default Bit [7:0]: Capture 0 Rising [7:0] This register holds the value of the Free-running Timer when the last rising edge occurred on the TIO0 input. When Capture 0 is in 8-bit mode, the bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register.
  • Page 45 Table 16-8. Programmable Interval Timer High (PITMRH) [0x27] [R] Bit # Reserved Field – – Read/Write Default Bit [7:4]: Reserved Bit [3:0]: Prog Internal Timer [11:8] This register holds the high order nibble of the 12-bit programmable interval timer. Reading this register returns the high order nibble of the 12-bit timer at the instant that the low order byte was last read.
  • Page 46 16.1.2 Timer Capture Cypress enCoRe II has two 8-bit captures. Each capture has separate registers for the rising and falling time. The two eight bit captures can be configured as a single 16-bit capture. When configured, the capture 1 registers hold the high order byte of the 16-bit timer capture value.
  • Page 47 Table 16-12. Capture Interrupt Enable (TCAPINTE) [0x2B] [R/W] Bit # Reserved Field – – Read/Write Default Bit [7:4]: Reserved Bit 3: Cap1 Fall Enable 0 = Disable the capture 1 falling edge interrupt 1 = Enable the capture 1 falling edge interrupt Bit 2: Cap1 Rise Enable 0 = Disable the capture 1 rising edge interrupt 1 = Enable the capture 1 rising edge interrupt...
  • Page 48 CY7C63310, CY7C638xx Figure 16-3. Timer Functional Sequence Diagram Document 38-08035 Rev. *K Page 48 of 83 [+] Feedback [+] Feedback...
  • Page 49 Figure 16-4. 16-Bit Free Running Counter Loading Timing Diagram clk_sys write valid addr write data FRT reload ready Clk Timer 12b Prog Timer 12b reload interrupt Capture timer 16b free running counter load 16b free 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 ACBE ACBF ACC0 running counter Figure 16-5.

  • Page 50: Interrupt Controller

    17. Interrupt Controller The interrupt controller and its associated registers allow the user’s code to respond to an interrupt from almost every functional block in the enCoRe II devices. The registers associated with the interrupt controller allow disabling interrupts globally or individually. The registers also provide a mechanism by which a user may clear all pending and posted interrupts, or clear individual posted or pending interrupts.

  • Page 51: Interrupt Latency

    Figure 17-1. Interrupt Controller Block Diagram Interrupt Taken INT_CLRx Write Interrupt Source (Timer, GPIO, etc.) 17.2 Interrupt Processing The sequence of events that occur during interrupt processing follows: 1. An interrupt becomes active, because: a. The interrupt condition occurs (for example, a timer expires). b.

  • Page 52: Interrupt Registers

    17.5 Interrupt Registers The Interrupt Clear Registers (INT_CLRx) are used to enable the individual interrupt sources’ ability to clear posted interrupts. When an INT_CLRx register is read, any bits that are set indicates an interrupt has been posted for that hardware resource. Therefore, reading these registers gives the user the ability to determine all posted interrupts.
  • Page 53 Table 17-5. Interrupt Mask 3 (INT_MSK3) [0xDE] [R/W] Bit # ENSWINT Field – Read/Write Default Bit 7: Enable Software Interrupt (ENSWINT) 0= Disable. Writing 0s to an INT_CLRx register, when ENSWINT is cleared, causes the corresponding interrupt to clear 1= Enable. Writing 1s to an INT_CLRx register, when ENSWINT is set, causes the corresponding interrupt to post. Bit [6:0]: Reserved Table 17-6.
  • Page 54 Table 17-7. Interrupt Mask 1 (INT_MSK1) [0xE1] [R/W] Bit # TCAP0 Prog Interval Field Int Enable Timer Int Enable Read/Write Default Bit 7: TCAP0 Interrupt Enable 0 = Mask TCAP0 interrupt 1 = Unmask TCAP0 interrupt Bit 6: Prog Interval Timer Interrupt Enable 0 = Mask Prog Interval Timer interrupt 1 = Unmask Prog Interval Timer interrupt Bit 5: 1-ms Timer Interrupt Enable...
  • Page 55 Table 17-8. Interrupt Mask 0 (INT_MSK0) [0xE0] [R/W] Bit # GPIO Port 1 Sleep Timer Field Int Enable Int Enable Read/Write Default Bit 7: GPIO Port 1 Interrupt Enable 0 = Mask GPIO Port 1 interrupt 1 = Unmask GPIO Port 1 interrupt Bit 6: Sleep Timer Interrupt Enable 0 = Mask Sleep Timer interrupt 1 = Unmask Sleep Timer interrupt...
  • Page 56 18. Regulator Output 18.1 VREG Control Table 18-1. VREG Control Register (VREGCR) [0x73] [R/W] Bit # Field – – Read/Write Default Bit [7:2]: Reserved Bit 1: Keep Alive Keep Alive, when set, allows the voltage regulator to source up to 20 µA of current when the voltage regulator is disabled. P12CR[0],P12CR[7] must be cleared.

  • Page 57: Usb Serial Interface Engine (Sie)

    19. USB/PS2 Transceiver Although the USB transceiver has features to assist in interfacing to PS/2, these features are not controlled using these registers. The registers only control the USB interfacing features. PS/2 interfacing options are controlled by the D+ and D– GPIO Configuration register (See Table 14-2 on page 34).

  • Page 58: Usb Device

    21. USB Device 21.1 USB Device Address Table 21-1. USB Device Address (USBCR) [0x40] [R/W] Bit # USB Enable Field Read/Write Default Bit 7: USB Enable This bit must be enabled by firmware before the serial interface engine (SIE) responds to the USB traffic at the address specified in Device Address [6:0].
  • Page 59 21.3 Endpoint 0 Mode Because both firmware and the SIE are allowed to write to the Endpoint 0 Mode and Count Registers, the SIE provides an interlocking mechanism to prevent accidental overwriting of data. When the SIE writes to these registers they are locked and the processor cannot write to them until after it has read them. Writing to this register clears the upper four bits regardless of the value written.
  • Page 60 21.4 Endpoint 1 and 2 Mode Table 21-4. Endpoint 1 and 2 Mode (EP1MODE – EP2MODE) [0x45, 0x46] [R/W] Bit # Stall Reserved Field Read/Write Default Bit 7: Stall When this bit is set the SIE stalls an OUT packet if the Mode Bits are set to ACK-OUT, and the SIE stalls an IN packet if the mode bits are set to ACK-IN.

  • Page 61: Usb Mode Tables

    Table 21-7. Endpoint 2 Data (EP2DATA) [0x60-0x67] [R/W] Bit # Field Read/Write Unknown Unknown Default The Endpoint 2 buffer is comprised of 8 bytes located at address 0x60 to 0x67. The three data buffers are used to hold data for both IN and OUT transactions. Each data buffer is 8 bytes long. The reset values of the Endpoint Data Registers are unknown.
  • Page 62 22.3 SETUP, IN, and OUT Columns Depending on the mode specified in the 'Encoding' column, the 'SETUP', 'IN', and 'OUT' columns contain the SIE's responses when the endpoint receives SETUP, IN, and OUT tokens, respectively. A 'Check' in the Out column means that upon receiving an OUT token the SIE checks to see whether the OUT is of zero length and has a Data Toggle (Data1/0) of 1.
  • Page 63 23. Details of Mode for Differing Traffic Conditions Control Endpoint Bus Event Mode Token Count Dval D0/1 Response S 0010 <=10, <>2 valid 0010 valid 0010 valid ACK_OUT_STATUS_IN 1011 SETUP >10 1011 SETUP <=10 invalid 1011 SETUP <=10 valid 1011 1011 1011 >10...

  • Page 64: Register Summary

    23. Details of Mode for Differing Traffic Conditions Control Endpoint Bus Event Mode Token Count Dval D0/1 Response S 1101 NAK IN 1100 1100 24. Register Summary The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF. Addr Name P0DATA...
  • Page 65 24. Register Summary (continued) The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF. Addr Name TMRCR First Edge 8-bit capture Prescale Hold TCAPINTE Reserved TCAPINTS Reserved CPUCLKCR Reserved USB CLK CLK/2...
  • Page 66 24. Register Summary (continued) The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF. Addr Name INT_VC RESWDT CPU_A CPU_X CPU_PCL CPU_PCH CPU_SP CPU_F Reserved CPU_SCR GIES Reserved OSC_CR0 Reserved No Buzz...
  • Page 67 25. Voltage Vs CPU Frequency Characteristics Figure 25-1. Voltage vs CPU Frequency Characteristics 5.50 4.75 4.00 Running the CPU at 24 MHz requires a minimum voltage of 4.75V. This applies to any CPU speed above 12 MHz, so using an external clock between 12 - 24 MHz must also adhere to this requirement.

  • Page 68: Absolute Maximum Ratings

    26. Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ... –40°C to +90°C Ambient Temperature with Power Applied... –0°C to +70°C Supply Voltage on V Relative to V ...–0.5V to +7.0V DC Input Voltage ...
  • Page 69 27. DC Characteristics (continued) Description Parameter General Differential Input Sensitivity Differential Input Common Mode Range Single Ended Receiver Threshold Transceiver Capacitance Hi-Z State Data Line Leakage PS/2 Interface Static Output Low Internal PS/2 Pull up Resistance General Purpose IO Interface Pull Up Resistance Input Threshold Voltage Low, CMOS mode...
  • Page 70 28. AC Characteristics (continued) Parameter Description USB Driver Transition Rise Time Transition Rise Time Transition Fall Time Transition Fall Time Rise/Fall Time Matching Output Signal Crossover Voltage USB Data Timing Low Speed Data Rate DRATE Receiver Data Jitter Tolerance DJR1 Receiver Data Jitter Tolerance DJR2 Differential to EOP Transition Skew...
  • Page 71 CLOCK GPIO Pin Output Voltage D − PERIOD Differential Data Lines Document 38-08035 Rev. *K Figure 28-1. Clock Timing Figure 28-2. GPIO Timing Diagram R_GPIO F_GPIO Figure 28-3. USB Data Signal Timing Figure 28-4. Receiver Jitter Tolerance Consecutive Transitions N * T PERIOD Paired Transitions...
  • Page 72 Figure 28-5. Differential to EOP Transition Skew and EOP Width PERIOD Differential Data Lines PERIOD Differential Data Lines Document 38-08035 Rev. *K Crossover Point Extended Crossover Point Diff. Data to SE0 Skew N * T PERIOD DEOP Figure 28-6. Differential Data Jitter Crossover Points Consecutive...
  • Page 73 SCK (CPOL=0) SCKH SCK (CPOL=1) MOSI MISO SCK (CPOL=0) SCKH SCK (CPOL=1) MOSI MISO Document 38-08035 Rev. *K Figure 28-7. SPI Master Timing, CPHA = 1 (SS is under firmware control in SPI Master mode) SCKL Figure 28-8. SPI Slave Timing, CPHA = 1 SCKL CY7C63310, CY7C638xx Page 73 of 83...
  • Page 74 SCK (CPOL=0) SCKH SCK (CPOL=1) MDO1 MOSI MISO SCK (CPOL=0) SCKH SCK (CPOL=1) MOSI SDO1 MISO Document 38-08035 Rev. *K Figure 28-9. SPI Master Timing, CPHA = 0 (SS is under firmware control in SPI Master mode) SCKL Figure 28-10. SPI Slave Timing, CPHA = 0 SCKL CY7C63310, CY7C638xx Page 74 of 83...

  • Page 75: Ordering Information

    29. Ordering Information Ordering Code FLASH Size CY7C63310-PXC CY7C63310-SXC CY7C63801-PXC CY7C63801-SXC CY7C63803-SXC CY7C63803-SXCT CY7C63813-PXC CY7C63813-SXC CY7C63823-QXC CY7C63823-SXC CY7C63823-SXCT CY7C63823-XC CY7C63833-LFXC CY7C63833-LTXC CY7C63833-LTXCT 30. Package Handling Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory.

  • Page 76: Package Diagrams

    31. Package Diagrams 0.740 0.770 0.140 0.190 0.115 0.160 0.090 0.110 0.386[9.804] 0.393[9.982] 0.050[1.270] 0.0138[0.350] 0.0192[0.487] Document 38-08035 Rev. *K Figure 31-1. 16-Pin (300-Mil) Molded DIP P1 DIMENSIONS IN INCHES 0.240 0.260 0.015 0.035 SEATING PLANE 0.120 0.140 0.015 0.060 0.055 0.015 0.065...
  • Page 77 0.140 0.190 0.115 0.160 0.090 0.110 0.447[11.353] 0.463[11.760] 0.050[1.270] TYP. 0.013[0.330] 0.019[0.482] Document 38-08035 Rev. *K Figure 31-3. 18-Pin (300-Mil) Molded DIP P3 DIMENSIONS IN INCHES 0.240 0.270 0.030 0.060 0.870 SEATING PLANE 0.920 0.120 0.140 0.015 0.060 0.055 0.015 0.065 0.020 Figure 31-4.
  • Page 78 0.033 REF. 0.150 0.157 0.228 0.244 SEATING PLANE 0.053 0.069 0.004 0.004 0.010 Document 38-08035 Rev. *K Figure 31-5. 24-Pin (300-Mil) SOIC S13 DIMENSIONS IN INCHES JEDEC STD REF MO-119 Figure 31-6. 24-Pin QSOP O241 PIN 1 ID 0.337 0.344 0.007 0.010 0.008...
  • Page 79 CY7C63310, CY7C638xx Figure 31-7. 32-Pin QFN Package 51-85188-*B Figure 31-8. 32-Pin Sawn QFN Package 001-30999 *A Document 38-08035 Rev. *K Page 79 of 83 [+] Feedback [+] Feedback...
  • Page 80 32. Document History Page Document Title: CY7C63310, CY7C638xx enCoRe™ II Low Speed USB Peripheral Controller Document Number: 38-08035 Orig. of Submission Rev. ECN No. Change 131323 221881 See ECN 271232 See ECN 299179 See ECN 322053 See ECN 341277 See ECN 408017 See ECN Document 38-08035 Rev.
  • Page 81 32. Document History Page Document Title: CY7C63310, CY7C638xx enCoRe™ II Low Speed USB Peripheral Controller Document Number: 38-08035 Orig. of Submission Rev. ECN No. Change 424790 See ECN 491711 See ECN 504691 See ECN Document 38-08035 Rev. *K (continued) Description of Change Date Minor text changes to make document more readable Removed CY7C639xx...
  • Page 82 32. Document History Page Document Title: CY7C63310, CY7C638xx enCoRe™ II Low Speed USB Peripheral Controller Document Number: 38-08035 Orig. of Submission Rev. ECN No. Change 2147747 VGT/AESA 05/20/2008 2620679 CMCC/PYRS 12/12/08 Document 38-08035 Rev. *K (continued) Description of Change Date TID number entered on page 1.
  • Page 83 33. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless wireless.cypress.com Memories...

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