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1.0
Features
• USB 2.0 hub controller
• Compliant with the USB 2.0 specification
• Windows
Hardware-quality lab (WHQL)-compliant
• Up to four downstream ports supported
• Supports bus-power and self powered modes
• Single-TT and Multi-TT modes supported
— Single-TT option for low-cost
— Multi-TT option for high performance
• 2-Port
— Single TT option for bus power
• Fit/form/function compatible option with CY7C65640
(TetraHub)
• Multiple package options
— Space-saving 56 QFN
• Single power supply requirement
— Internal regulator for reduced cost
• Integrated upstream pull-up resistor
• Integrated pull-down resistors for all downstream ports
• Integrated upstream and downstream termination
resistors
• Integrated port status indicator controls
• 24-MHz external crystal (integrated PLL)
• Configurable with external SPI EEPROM
— Vendor ID, Product ID, Device ID (VID/PID/DID)
— Number of active ports
— Number of removable ports
— Maximum power setting for high-speed and full-
speed
— Hub controller power setting
— Power-on timer
— Overcurrent detection mode
— Overcurrent timer
— Enable/Disable overcurrent timer
— Overcurrent pin polarity
— indicator pin polarity
— Compound device
— Enable full-speed only
— Disable port indicators
— Gang power switching
— Enable single-TT mode only
— Self/bus powered compatibility
— Fully configurable string descriptors for multiple
language support
• In-system EEPROM programming
Cypress Semiconductor Corporation
Document #: 38-08037 Rev. *D
PRELIMINARY
Low-Power USB 2.0 Hub Controller Family
2.0
EZ-USB HX2LP is Cypress's next-generation family of high-
performance, low-power USB 2.0 hub controllers. HX2LP is an
ultra low-power single-chip USB 2.0 hub controller with
integrated upstream and downstream transceivers, a USB
Serial Interface Engine (SIE), USB Hub Control and Repeater
logic, and Transaction Translator (TT) logic. Cypress has also
integrated many of the external passive components, such as
pull-up and pull-down resistors, reducing the overall bill-of-
materials required to implement a hub design. The entire
HX2LP portfolio consists of:
1. CY7C65640B (TetraHub LP): 4-port/multiple transaction
translator
This device option is fit/form/function compatible with Cy-
press's existing CY7C65640 device. Cypress's "Tetra" ar-
chitecture provides four downstream USB ports, each with
a dedicated Transaction Translator (TT), making it the high-
est-performance hub available. The TetraHub LP also of-
fers best-in-class power consumption. The CY7C65640B is
available in a 56 QFN (TetraHub pin-compatible) for space
saving designs.
2. CY7C65630: 4-port/single transaction translator
This device option is for ultra low-cost applications where
performance is secondary consideration. All four ports
must share a single transaction translator in this configura-
tion. The CY7C65630 is available in a 56 QFN and is also
pin for pin-compatible with the CY7C65640.
3. CY7C65620:
This device option is for a 2-port bus powered application.
Both ports must share a single transaction translator in this
configuration. The CY7C65620 is available in a 56 QFN
and is also pin for pin compatible with the CY7C65640.
All device options are supported by Cypress's world-class
reference design kits, which include board schematics, bill of
materials, Gerber files, Orcad files, and thorough design
documentation.
•
3901 North First Street
EZ-USB HX2LP™
Introduction
,
•
San Jose
CA 95134
Revised March 31, 2005
CY7C656xx
•
408-943-2600
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Related Manuals for Cypress Semiconductor CY7C656xx
Summary of Contents for Cypress Semiconductor CY7C656xx
- Page 1 All device options are supported by Cypress’s world-class reference design kits, which include board schematics, bill of materials, Gerber files, Orcad files, and thorough design documentation. • 3901 North First Street • CY7C656xx EZ-USB HX2LP™ San Jose CA 95134 • 408-943-2600 Revised March 31, 2005...
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Page 2: Block Diagrams
P HY Control D- P W R#[2] LE D P W R#[3] OV R#[2] Figure 3-1. CY7C65640B Block Diagram CY7C656xx High-Speed USB C ontrol Logic SPI Com m unication Block USB D ow nstream Port 4 P ort US B 2.0... - Page 3 Control D- P W R#[2] LE D D- P W R#[3] OV R#[2] Figure 3-2. CY7C65630/CY7C65620 Block Diagram CY7C656xx H igh-Speed USB Contr ol Logic SPI C om m unication Block U SB D ownstream Por t 4 P ort US B 2.0...
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Page 4: Functional Overview
CY7C656xx will be in a high-speed mode, with the upstream D+ pull-up resistor turned off. In USB 1.x systems, no such chirp sequence from the upstream hub will be seen, and CY7C656xx will operate as a normal 1.x hub (operating at full speed). Enumeration After a USB Bus Reset, CY7C656xx is in an unaddressed, unconfigured state (configuration value set to 0). - Page 5 PWR [n]# output pins of the CY7C656xx series are connected to the respective external power switch's port power enable signals. Table 5-1. Automatic Port State to Port Indicator Color Mapping...
- Page 6 Information presented in Table 5-1 and Table 5-2 is from USB 2.0 specification Tables 11-6 and 11-7, respectively. Document #: 38-08037 Rev. *D PRELIMINARY Table 5-2 displays the color definition of the indicators when CY7C656xx is in Manual Mode. Table 5-2. Port Indicator Color Definitions in Manual Mode Color Definition Amber...
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Page 7: Pin Configuration
DD+[3]/NC DD–[2] DD+[2] DD–[1] DD+[1] Figure 6-1. 56-pin Quad Flat Pack No Leads (8 mm x 8 mm) Note: NC are for CY7C65620 ONLY. Document #: 38-08037 Rev. *D PRELIMINARY CY7C656xx AMBER#[3]/NC GREEN#[3]/NC AMBER#[2] GREEN#[2] AMBER#[1] GREEN#[1] OVR#[2] PWR#[2] OVR#[1]... -
Page 8: Pin Description Table
SPI Chip Select. Connect to CS pin of the EEPROM. SPI Clock. Connect to EEPROM SCK pin. I/O/Z SPI Dataline Connect to GND with 15-K Data I/O pins of the EEPROM. CY7C656xx Description through a 100K resistor, and to GND resistor and to the Page 8 of 23... - Page 9 Default is Active LOW. Polarity is controlled through EEPROM. Input Overcurrent Condition Detection Input. Default is Active LOW. Polarity is controlled through EEPROM. Power Switch Driver Output. Default is Active LOW. Polarity is controlled through EEPROM. CY7C656xx Description Page 9 of 23...
- Page 10 Device Descriptor The standard device descriptor for CY7C656xx is based on the VID, PID, and DID found in the SPI EEPROM. This VID/PID/DID in the EEPROM will overwrite the default VID/PID/DID. If no EEPROM is used, the CY7C656xx will enumerate with the default descriptor values as shown below.
- Page 11 7 Bytes bDescriptorType ENDPOINT_DESCRIPTOR bEndpointAddress IN Endpoint #1 bmAttributes Interrupt wMaxPacketSize Maximum Packet Size bInterval Polling Rate Field Name bLength 10 Bytes bDescriptorType DEVICE_QUALIFIER bcdUSB bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 bNumConfigurations bReserved CY7C656xx Description Description Description Description Page 11 of 23...
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Page 12: Configuration Options
00: Ganged power switching (all ports’ power at once) 01: Individual port power switching (Default in CY7C656xx) b2: Identifies a Compound Device, 0: Hub is not part of a compound device (Default in CY7C656xx), 1: Hub is part of a compound device. b4, b3: Over-current Protection Mode 00: Global Overcurrent Protection. - Page 13 (USB 2.0, 11.24.2.5). For sys- tems that do not accept this, the IllegalHubDescriptor con- figuration bit may be set to allow CY7C656xx to accept a DescriptorType of 0x00 for this command. Default is 1. Bit 6: CompoundDevice: Indicates whether the hub is part of a compound device.
- Page 14 USB hosts use a DescriptorTypeof 0x00 instead of HUB_DESCRIPTOR, 0x29. According to the USB 2.0 stan- dard, a hub must treat this as a Request Error, and STALL the transaction accordingly (USB 2.0, 11.24.2.5). For sys- CY7C656xx reported HubDescriptor: Page 14 of 23...
- Page 15 IllegalHubDescriptor con- figuration bit may be set to allow CY7C656xx to accept a DescriptorType of 0x00 for this command. Default is 0, rec- ommended setting is 1. Bit 6: CompoundDevice: Indicates whether the hub is part of a compound device.
- Page 16 SetCongfiguration 00000000B GetInterface 10000001B Note: 12. Only one configuration is supported in CY7C656xx. Document #: 38-08037 Rev. *D PRELIMINARY Byte c: iSerialNumber Array of addresses for the iSerialNumber strings. Each ad- dress is two bytes long, stored LSB first. The array has NumLangs entries (2 * NumLangs bytes).
- Page 17 1,2, 3, 4 or 5 Byte 1: Port 0x03 Feature Byte 0: [13] Selector Selectors (PORT_INDICATOR) 0, 1, 2, or 3 Byte 1: Port 0x06 Descriptor Type and Descriptor Index CY7C656xx wIndex wLength Data 0x0000 None 0x0000 None 0x0000 None 0x0000 None 0x0000 None...
- Page 18 Test_K Port Test_SE0_NAK Port Test_Packet Port Test_Force_Enable Port Port Port Port Port Port Port Port Port Port Selector Value CY7C656xx wIndex wLength Data 0x0000 None 0x0000 None TT State TT State Length 0x0000 None Length Data Length Data [15] Selector Value...
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Page 19: Led Connections
4.7 nF 250V Figure 11-1. USB Upstream Port Connection PWRx 150 µF 0.01 µF DD–[X] DD+[X] Figure 12-1. USB Downstream Port Connection GREEN#[x] AMBER#[x] Figure 13-1. USB Downstream Port Connection CY7C656xx BUSPOWER 100 k D– SHELL 3.3V Page 19 of 23... -
Page 20: System Block Diagram
OVR2 PWR3 PWR3 OVR3 OVR3 PWR4 PWR4 OVR4 OVR4 SPI_CS SPI_CS SPI_SCK SPI_SCK SPI_SD SPI_SD Figure 14-1. Sample Schematic CY7C656xx PWR1 DD–[1] PWR4 150 F DD+[1] 0.01 F PWR3 PWR2 PWR1 GREEN#[1] AMBER#[1] PWR2 DD–[2] 150 F DD+[2] 0.01 F... -
Page 21: Electrical Characteristics
High-speed Host 15.5 AC Electrical Characteristics Both the upstream USB transceiver and all four downstream transceivers have passed the USB-IF USB 2.0 Electrical Certi- fication Testing. Conditions CY7C656xx parallel resonant, fundamental mode, 12-pF load capacitance, 0.5 mW Min. Typ. Max. -
Page 22: Ordering Information
16.0 Ordering Information Ordering Code CY7C65640B-56LFXC CY7C65630-56LFXC CY7C65620-56LFXC CY46XX 17.0 Package Diagrams The CY7C656xx is available in a space-saving 56-pin QFN (8 × 8 mm). TOP VIEW 7.90[0.311] 8.10[0.319] 7.70[0.303] 7.80[0.307] 0.80[0.031] DIA. Dimensions in mm E-Pad size 6.0 x 6.0 mm typ Windows is a registered trademark of Microsoft Corporation. - Page 23 Document History Page Document Title: CY7C656xx EZ-USB HX2LP™ Low-Power USB 2.0 Hub Controller Family Document Number: 38-08037 REV. ECN NO. Issue Date 131505 02/12/2004 231329 See ECN 250869 See ECN 330195 See ECN 342997 See ECN Document #: 38-08037 Rev. *D PRELIMINARY Orig.
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