Table of Contents
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Description
This section describes the microprocessor, math coprocessor,
channel differences, memory subsystems, and miscellaneous system
| ports and connectors for the Model 65 SX.
Additional information on
| these topics can be found in the Hardware Interface Technical
| Reference listed in the preface of this manual.
Microprocessor and Math Coprocessor
The Model 65 SX uses an 80386SX Microprocessor that runs at
16 MHz and has a 24-bit address and a 16-bit data interface.
The
80386SX Microprocessor is software compatible with the 80386
Microprocessor.
The 80387SX Math Coprocessor matches the speed of the system
microprocessor and operates in the synchronous mode.
The 80387SX
Math Coprocessor is software compatible with the 80387 Math
Coprocessor.
| Micro Channel Implementation
This section describes the implementation of the Micro Channel
architecture on the Model 65 SX system.
For more information, refer
to the Hardware interface Technical Reference Micro Channel
architecture information.
| Exception Reporting
| Exceptions should be reported using the asynchronous channel check
| procedure.
The synchronous channel check procedure is not
| supported.
Central Arbiter
The central-arbitration control point gives intelligent subsystems on
the channel the ability to share and control the system.
It allows
burst-data transfers and prioritization of control between devices.
The central arbiter supports up to 15 arbitrating devices (levels 0
through E) and the system microprocessor (level F).
Model 65 System Board
— October 1990
3-3
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