Philips CDF 100 Service Manual page 14

5.1.5 Bitstream DAC
SAA7321 : NMOS digital filter with enhanced
concealment of uncorrectable errors
. HS flexible data input
. Phase linear digital filter with 1st order noise shaper
. 256 times oversampling by linear interpolation and
sample hold
. 16 bit super linear resolution
. Switch capacitor 1 bit converter
Low power consumption typ. 300 mW
Temperature range -40 C - + 85 C
Single supply operation + 5 V
PIN ABBRE- DESCRIPTION
NO. VIATION
1 CDR Capacitor Damping Right
2 DER De-Emphasis Right
3 VrefR Reference voltage Right
4 VSSAR Ground Analogue Right
5 VSSA Ground logic Analogue section
6 VSSAL Ground Analogue Left
7 Vreft. Reference voltage Left
8 DEL De-Emphasis Left
9 CDL Capacitor Damping Left
10 INTL Integrator Left
11 VDDAL Power Supply +5V Analogue Left
12 OALI- Operational Amplifier Left Input-
13 OALI+ OpAmp Left Input+
14 OALO OpAmp Left Output
15 VDDret Power Supply: +5V
16 VRO Reference Voltage Output
17 VRC Reference Voltage Capacitor
18 TEST4 Test output 5 (NC)
19 DAO 12S Serial Data Output (NC)
20 CLO 12S Serial bit Clock Output (NC)
21 WSO 12S Word Select Output (NC)
22 VDD1 Power supply +5V Digital
23 vVDD2 Power Supply +5V (OSC)
24 XTAL2 Crystal oscillator output
25 XTAL1 Crystal oscillator input
26 XSYS System clock output (NC)
27,28 VSS Ground digital section
29 TEST1 Test input 1
30 WSI {2S Word Select input (WSAB)
31 CLI 12S Serial bit Clock input (CLAB)
32 DAI 12S Serial Data input (DAAB)
33 nc.
34 DEC De-Emphasis Control
35 MUTE Mute:
36 ATT Attenuation
37,38 TEST2,3 Test output 2 and 3 (open)
39 VDDA Power Supply +5V Analogue
40 OARO OpAmp Right Output
41 OARI+ OpAmp Right Input +
42 OARI- OpAmp Right Input -
43 VDDAR Power Supply +5V Analogue right
44 INTR Integrator Right
"BITSTREAM" DIGITAL-TO-ANALOGUE
CONVERSION - SIMPLY EXPLAINED
As a technique, Digital-to-Analogue (D/A) conversion is
inevitably partly digital and partly analogue.in view of the
extreme precision of digital technology, however, the
more digital D/A conversion is, the betier the result is
likely to be. CD is a 16-bit digital audio system (each
16-bit sample is a 16-bit binary number), and the
successive samples are converted into a continuous
analogue audio waveform by the Digital-to-Analogue
Converter (DAC).
ORTHODOX D/A CONVERSION
The orthodox way to do this is to convert each bit of the
16-bit number individually into an equivalent analogue
current or voltage value, add the values together to
obtain the total analogue value and then assemble
successive total values together into a continuous audio
waveform.(Basic 16-bit conversion diagram). After the
16-bit number is decoded, this process is entirely
analogue.
THE ULTIMATE SOLUTION: "BITSTREAM" 1-BIT
CONVERSION
The (Philips)"Bitstream" system uses a 1-bit converter.
That is to say, it produces 1-bit samples from the 16-bit
CD samples. Each 1-bit sample consists of the MSB, or
"sign bit". It can only indicate + Ve or - Ve. But from this
information, a positive or negative pulse is produced.
Meanwhile, the remainder of the 16-bit sample is carried
over to the next 16-bit sample, where it may influence the
value of the next 1-bit sample. By this process, a train of
pulses is produced; and it is the variations in density of
the pulses that represent the variations in the audio
waveform. By averaging the pulses (i.e. by low-pass
filtering), the analogue audio waveform is regenerated).
"Bitstream" signal processing
The samples decoded from the Compact Disc are tumed
into the 256-times oversampled "bitstream" in 3 stages.
- Four-times oversampling with interpolation. This
attenuate harmonic images of the audio signal and
ensures a flat audio response curve in the same way as
the digital filtering of an orthodox Philips 16-bit converter.
- 64-times oversampling with interpolation. This produces
11,289,600 16-bit samples per second, very closely
defining the decoded audio signal.
- 16-bit/1-bit code conversion with noise shaping. This
produces the single-bit pulse train.
in "Bitstream" D/A conversion, only the fina! signal
averaging is performed with analogue circuitry. No
component element matching is required, and linearity is
excellent. There is no MSB switch around O V level, and
thus no crossover distortion.
5.1.6 Compact disc blockdecoder.
The CDBD ( CD - BLOCK DECODER ) is an integrated
circuit which is intended to perform the basic functions on
EFM decoder data (CD-ROM /XA /CD-1) to get block
structured descrambied data. Three input formats (12S,
SONY and MEC) are hardware selectable by means of
two selection lines. The output is an parallel output ( 8 bit
plus errorfilag ) with "output enable" for the possibility of
bus structured architecture. The CDBD is programmable
via the pC INTERFACE , Chip Select, two address lines
a read/write line and an 8 bits bus. in order to find the
beginning of a sector in the data stream the sync detector
continuously searches for the 12 bytes sync pattern.
The CRC circuit checks the EDC in the data and put its
result into the status register (bit 3).
Both HEADER and SUBHEADER can be read out via the
HC INTERFACE.
PCS 66 394