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Description
Vertical sync signal output
46)
TESTI | I | Test pin Normally "L*
(built-in pull-down resistor)
[a
Ys
© | Superimpose control output
48 | CSYNC | © | Composite syne signal output
49]
4¥SC2 | I | External clock input when superimpose
(built-in feedback resistor)
Le
EFLG | 0 | Errorcondition monitor
51 | FSX | O | Errorcondition monitor trigger
52]
DEN | I | Disc information display enable
(built—in pull-down resistor)
H: BGC, L: enable
53]
PALID | I | External control when superimpose PAL
(built-in pull-up resistor)
54 | HRESET | I | Horizontal timing external control
|
55 | FSC | O | Subcarrier clock output
NTSC mode: 3.579545 MHz
PAL mode: 4.433619 MHz
56 | VRESET | I | Vertical timing external control
57}
RESET | I ] Reset input
58|
NP1
| I | NTSC/PAL selection terminal (RGB encoder)
H: NTSC, L: PAL
59 | N/P2 | I | NTSC/PAL selection terminal (CD-G Saal
L
H: NTSC, L: PAL
60}
SON | I | Superimpose ON/OFF
61 | xan2_
| 1 | Crystal resonator 17.734476 MHz for PAL) |
62 | XOUT2 | O | Crystal resonator 17.734476 MHz (for PAL)
63 | XIN1 | I | Crystal resonator 1431818 MHz (for NTSC)
67
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