Kenwood UD-300 Service Manual page 43

UD-300
CIRCUIT DESCRIPTION
| Pin No.) Pin name | 1/0 Function
| 50 APTR reese Control output for correcting aperture. Set to "H'' when Rch.
51 APTL O | Control output for correcting aperture. Set to ''H" when Lch.
52. | Vss | — | GND.
53 XTAI |e | X'tal oscillation circuit input of 16.9344MHz, or input of 33.8688MHz.
[_ 54 XTAO {0 X'tal oscillation circuit output of 16.9344MHz. '|
55 XTSL | X'tal selection input terminal. Set to "L'' when x'tal is 16.9344MHz, and to ''H" when 33.8688MHz.
56 | FSTT O | 28 division output of terminals 53 and 54. Does not vary as pitch varies.
57 C4M OQ | 4.2336MHz output. Varies as pitch varies.
58 C16M O | 16.9344MHz output. Varies as pitch varies. |
59 MD2 | | Digitalout ON/OFF control. Turns on when "H", and off when "'L".
60 DOUT | O | Digital-out output terminal.
61 EMPH O | Outputs "'H' when playing disc has emphasis, and ''L'' when the latter does not.
62 WFCK O | WFCK (Write Frame Clock) output.
63 SCOR O | Outputs 'H" when sub-code syne SO or Si is detected.
64 SBSO O | Serial output of Sub P ~ W.
65 | EXCK | Clock input for SBSO read out.
66 SQSO 0 Sub Q 80-bit and PCM peak, and level data 16-bit output.
67 SQCK Clock input for SQSO read out.
68 MUTE Mutes when "H", and resets when "L".
| 69 | SENS | — | Outputs SENSto CPU.
70 XRST | Resets system when '"'L".
71 DATA Inputs serial data from CPU.
72 XLAT Latches serial data when latch input from CPU fails.
73 Voo - | Power supply (+5V).
74 CLOK | Serial data transfer clock input from CPU.
75 SEIN Input SENS from SSP.
76 CNIN Inputs signals for counting number of track jumps. "
77 DATO O | Outputs serial data to SSP.
78 XLTO O | Outputs serial data latch to SSP, and latches at fall.
79 CLKO © | Outputs serial data transfer clock to SSP.
80 MIRR
Notes
* The 64-bit slot is 2's compliment output of LSB first, and the + The GFS becomes "'H" when the frame sync is matched to the
48-bit slot is 2's compliment output of MSB first. internal protection timing.
GTOP is used to monitor the protective condition of the frame
sync. ("H" : Sync protective window is released.)
XUGF is the frarne sync obtained from the EFM signal, which
is a negative pulse. This is the signal before the protection of
sync.
XPLCK is the inverted clock of EFM PLL. PLLis so made that
the falling edge will be matched to the change point of the
EFM signal.
RFCK is a signal having the period of 136 obtained by the
accuracy of X'tal.
C2P0 is a signal indicating the error condition of data
XRAOF is a signal generated when 32 KRAM exceeds he jitter
margin of +28F.
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