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FL8400
3. Regenerative Circuit
3-1. RF circuit
The currents from photodiodes (A, B, C and d) are fed to iC 104 through pins 7 and 8 and converted to
voltage by RF I-V amplifiers (1) and (2) respectively there, added by the RF summing amplifier and
output from pin 2 as a signal. It can be checked at the test point (RF T.P.) provided on its way by means
of the eye pattern check.
Pick-up
Fig. 7
3-2. EFM demodulation, error correection, serial/parallel conversion
The EFM comparator changes RF signal into a binary value. As the asymmetry generated due to
variations in disc manufacturing cannot be eliminated by the AC coupling along, the reference voltage
of EFM comparator is controlled utilizing the fact that the generation probability of 1, 0 is 50% each in
the binary EFM signals. -
1¢102
Ic104
Wc
A
ic
i
—cS
AUTO ASYMMETRY
CONTROL AMP
28)
t
|
'
1
|
!
CMOS BUFFER
I
AUTO ASYMMETRY
|
|
BUFFER
|
i
'
|
|
!
2)
RFI
>—{(1)
H
H
EFM COMPARATOR
I
Arts apa cS
eto
ll
Fig. 8
As this comparator is a current SW type, each of the H and L levels does not equal the power supply
voltage, requiring feedback through a CMOS buffer.
R8, R9, C8, and C9 form a LPF to obtain (Vec+DGND)/2V, When fe (cut-off frequency) is made more than
500 Hz the EFM low-frequency component leaks badly, degenerating the block error rate.
3-3. Digital Signal Processor
The EFM signals from pin 27 of IC104 are sent to pin 5 of IC102, then demodulated from 14 bits to 8 bits
by EFM readjustment. At the same time any error, if found, is corrected (CIRC) and the signals are sent
to the D/A converter interface. After that they are output as 16-bit digital signals from pins 76, 78 and 80
of C102 and fed to the D/A Converter of IC107. In this case, EFM demodulation, error correction and
serial/parallelconversion are performed by the internal circuitny of 1C102.
1C104
1C102
Error
Correction
EFM
E——*
demodulation
18
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