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M
GEA MX8 ULP HW manual
icro
Getting started manual
DATE
REVISION
10/01/2023
1.0.0
25/01/2023
1.0.1
03/03/2023
1.0.2
15/03/2023
1.0.3
02/10/2023
1.0.4
03/01/2024
1.0.5
22/01/2024
1.0.6
***** Revision History *****
CHANGE DESCRIPTION
Release
General improvement
Mechanics size updated, added LCD peripheral i/f, updated CPU & Memory specs, fixed issue on PN
structure, updated Electrical specs, added module connector positioning, updated peripheral mux chapter
Corrected mistake on peripheral mux chapter
Corrected typo error on mux chapter
Improved block diagram and mux chapter, corrected mistake on main features. Preliminary power
consumption measurements.
Added ADC signals pinout, fixed some typos
1
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Table of Contents
Related Manuals for ENGICAM MicroGEA MX8 ULP HW
Summary of Contents for ENGICAM MicroGEA MX8 ULP HW
- Page 1 GEA MX8 ULP HW manual icro Getting started manual ***** Revision History ***** DATE REVISION CHANGE DESCRIPTION 10/01/2023 1.0.0 Release 25/01/2023 1.0.1 General improvement Mechanics size updated, added LCD peripheral i/f, updated CPU & Memory specs, fixed issue on PN 03/03/2023 1.0.2 structure, updated Electrical specs, added module connector positioning, updated peripheral mux chapter...
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Page 2: Table Of Contents
Table of Contents 1. Introduction ....................................3 Introduction.............................. 4 Block Diagram ............................5 Main Features ............................6 Document and Standard References ...................... 6 1.4.1 External Industry Standard Documents ....................6 1.4.2 NXP Documents ..........................6 Acronyms and Abbreviations used ......................7 2.Mechanical data .................................. -
Page 3: Introduction
Chapter 1 1. Introduction This Chapter gives background information on this document. Section includes： General Overview ✓ Acronyms and Abbreviations Used ✓ Document and Standard References ✓... -
Page 4: Introduction
1.1 Introduction This document is created to guide users to design MicroGEA compliant carrier board. It will focus only on the interfaces in MicroGEA pinouts and related peripherals. This document helps walk hardware designers through the various stages of designing a carrier board on this platform. Using this document, hardware designers can efficiently locate the resources they need at every step in the board design flow. -
Page 5: Block Diagram
1.2 Block Diagram... -
Page 6: Main Features
1.3 Main Features 1.4 Document and Standard References External Industry Standard Documents • The I2C Specification, Version 2.1, January 2000, Philips Semiconductor (now NXP) (www.nxp.com). • I2S Bus Specification, Feb. 1986 and Revised June 5, 1996, Philips Semiconductor (now NXP) (www.nxp.com). •... -
Page 7: Acronyms And Abbreviations Used
1.5 Acronyms and Abbreviations used ABBREVIATION EXPLANATION Analogue to Digital Converter Controller Area Network, a bus that is manly used in automotive and industrial environment Central Processor Unit Digital to Analogue Converter Electromagnetic Interference, high frequency disturbances Electrostatic Discharge, high voltage spike or spark that can damage electrostatic- sensitive devices Inter-integrated circuit, a bus for single-ended multi-master/multi-slave serial communication Ground... -
Page 8: Mechanical Data
Chapter 2 2.Mechanical data This Chapter gives information about PCB and module's dimensions. Section includes： Mechanical data ✓ Assembly Top view ✓ Assembly Bottom view ✓ Interface Connectors ✓... -
Page 9: Assembly Top View
2.1 Assembly Top View In the Figure below is shown top view assembly plan. Figure 1 2.2 Assembly Bottom View The Figure below shows the bottom view assembly plan. Figure 2... -
Page 10: Interface Connectors
2.3 Interface Connectors The following information report the connectors, referred to the series DF40 (HRS) compliant with the MicroGEA SOM interface. CARRIER CONNECTORS Note: for information on the connectors’ positioning on carrier board, refer to Chapter 5.1.4... -
Page 11: Ordering Information And Features
Chapter 3 3.Ordering Information and Features This Chapter gives the ordering information and technical specifications of the modules. Section includes： ✓ MicroGEA MX8ULP Ordering code ✓ CPU & memory specifications ✓ Operating temperature range... -
Page 12: Ordering Information
3.1 Ordering Information Following we provide the ordering information and the description for the Basic technical specification modules: Part name Ordering Code Description CPU & Memory specifications CPU junction Operating temperature Module available temperature range °C range °C (excepted CPU) at least until 002680036DI440 -40 to +105... -
Page 13: Part Number Structure
3.2 Part Number Structure The standard order codes shown in the following table: 0026 Reserved Reserved RAM SIZE RAM SIZE OPTION AVAILABLE OPTION AVAILABLE No option No LCD NON- VOLATILE MEMORY VOLATILE MEMORY SPECIFICATION SOM TYPE SOM TYPE MicroGEA 8ULP 4GB eMMC 8GB eMMC TEMPERATURE QUALIFIER... -
Page 14: Pinout
Chapter 4 4. Pinout This Chapter gives the pinout information. Section includes： Pinout overview ✓ i.MX Pad specifications ✓ Electrical specification ✓... -
Page 15: Module Pinout
4.1 Module Pinout The module's interface is achieved by 2 connectors HRS code DF40C-90DP that mates with HRS code DF40C-90DS on the carrier board, or compatible (for further details refer to Chapter 2.3). Peripherals are implemented either on Application Domain (AP) or on Real Time Domain (RT). See Domain column on the following tables for more details. A CONNECTOR (J2) NAME PAD on i.MX... - Page 16 NAME PAD on i.MX DESCRIPTION GPIO Dom Voltage EVEN NAME PAD on i.MX DESCRIPTION GPIO Voltage BOOT_MODE0 BOOT_MODE0 Boot mode selection LPI2C4_SDA PTF9 I2C signal (pull-up needed on +3,3V carrier) BOOT_MODE1 BOOT_MODE1 Boot mode selection BL_PWM PTA4 Backlight control +3,3V I2S0_RXD0 PTC4 I2S Data In...
- Page 17 B CONNECTOR (J1) NAME PAD on i.MX DESCRIPTION GPIO Dom Voltage EVEN NAME PAD on i.MX DESCRIPTION GPIO Dom Voltage DPI0_D20 PTE1 Display Port +3,3V DPI0_D10 PTF13 Display Port +3,3V DPI0_D21 PTE2 Display Port +3,3V DPI0_D15 PTD20 Display Port +3,3V DPI0_D11 PTF12 Display Port...
- Page 18 NAME PAD on i.MX DESCRIPTION GPIO Dom Voltage EVEN NAME PAD on i.MX DESCRIPTION GPIO Dom Voltage PTC18 PTC18 General GPIO +3,3V Ground PTC19 PTC19 General GPIO +3,3V LPI2C1_SCL PTA12 I2C signal (pull-up needed on +3,3V carrier) Ground LPI2C1_SDA PTA13 I2C signal (pull-up needed on +3,3V carrier)
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Page 19: Electrical Specifications
4.2 Electrical specifications V Min (Volts) V Typ (Volts) V Max (Volts) + 3,3 VBUS_OTG_USB, VBUS_USB GPIO V(oh) + 2,88 GPIO V(ol) + 0,33 GPIO V(ih) + 2,25 GPIO V(il) + 0,67 Table 4 This measure has been done testing the module's start at the limit temperatures of -40°C and +85°C Module Test condition Current Min @Vin... -
Page 20: Carrier Board Design
Chapter 5 5. Carrier Board Design This Chapter gives the technical specifications for carrier board design. Section includes： ✓ Carrier Board recommendations Power signals and backup battery ✓ ✓ Serials ✓ CAN Bus Ethernet ✓ ✓ ✓ SDIO Boot mode ✓... -
Page 21: Carrier Board Recommended Specifications
5.1 Carrier board recommended specifications 5.1.1 Planarity in finish process Due to the technical and mechanical specifications of the connector we suggest the maximum planarity of the footprint on PCB, so we suggest a type of finish obtained by horizontal process (we suggest and use for our carrier boards a type Chemical Gold finish). 5.1.2 Planarity of PCB Also, the planarity of the entire Printed Circuit Board must be kept in check especially when the carrier board grows in size. -
Page 22: How To Power The Module
5.2 How to power the module Read carefully the related sections before starting the power stage design. This module needs to be supplied with a +3.3Vin power. Refer to the table below for the power supply range specification. The power dissipated by the module in the operating mode is about 200 mA, but the system must provide at least a power of 1A at 3.3V to allow the start of the module. -
Page 23: How To Connect 3-Wire Rs232 Serial Port
5.3 How to connect 3-wire RS232 serial port This section shows how to use the UARTs as 3-wire RS232 serial ports. UART is used for asynchronous serial communication, in which the data format and transmission speeds are configurable. The following table shows the UARTs pins numbering. A Connector Name Primary Function Description... -
Page 24: How To Connect A Rs485 Serial Port
5.4 How to connect a RS485 serial port This chapter shows how an RS485 serial port can be connected to the module. The figure below shows how the UART signals are used to connect to a RS485 transceiver on the starter kit. Figure 5 The pins involved in this RS485 communication example are listed in the following table. -
Page 25: How To Connect Can Bus Interfaces
5.5 How to connect CAN BUS interfaces This chapter describes how CAN bus transceiver can be connected to a module. The figure below shows how CAN bus is connected in the evaluation board. Figure 6 The following table describes the pins' numbering in the main connector involved in the CAN interface A Connector Name Primary Function Description... -
Page 26: How To Design The Ethernet Interface
5.6 How to design the Ethernet interface The NXP i.MX8ULP Ethernet Media Access Controller (MAC) is designed to support both 10 and 100 Mbps Ethernet/IEEE standard 802.3™ networks. The 10-Mbps and 100-Mbps RMII Ethernet physical interfaces is supported. The figure shows how to connect the Ethernet interface to the module. -
Page 27: Component Placement Considerations
5.6.1 Component Placement considerations Components placement can affect signal quality, emissions and can decrease EMI problems. If the magnetics are a discrete component than the distance from the connector RJ45 should be kept under 25mm of separation. To decrease EMI problems the distance between magnetics and Phy should be at least 25mm or greater to isolate the PHY from magnetics. -
Page 28: Cable Transient Event And Phy Protection
5.6.2 Cable Transient Event and PHY Protection Cable transient events are + and - DC surges that are induced across the transformer onto the PHY side of the TX+/- and RX+/- signals as shown in the figure below. The PHY side of the transformer should not contain any DC component other than the typical 3.3V pull-up on the center tap of the transformer for analog signal biasing. -
Page 29: Phy Ethernet
5V. D3 and D4 act the same way when the transient is across the RX+/- differential pair. The total capacitance seen by each differential pair must not exceed 50pF (25pF single ended). Figure 10 Recommended by ENGICAM: Diode array TVS, 4 CH, ESD, 3.3V Wurth Elektronik 824015043... -
Page 30: How To Connect The Usb Host Interface
5.7 How to connect the USB host interface The module provides 2 ports for USB host interface. The figure shows how to connect these ports to the Module. Figure 11 A Connector Name Primary Function CPU Pin Name GPIO Capable Voltage Description USB0_DM... -
Page 31: How To Connect The Sd Card Interface
5.8 How to connect the SD CARD interface The NXP i.MX8ULP Ultra Secured Digital Host Controller (uSDHC) provides the interface between the host system and MMC/SD/SDIO cards, including cards with reduced size or mini cards. The module includes these features and the figure shows how the Micro SD Card connector is connected to MicroGEA Module in the evaluation board. -
Page 32: How To Connect An Lcd Display
5.9 How to connect an LCD display 5.9.1 Connection map for 24bit display The following map represent the connection mode applied to 24bit TFT display. TFT LCD is a variant of LCD that improves image qualities. For every connection the colour controlled is joined A Connector B Connector Name... -
Page 33: Dsi Interface
5.9.2 DSI Interface The Display Serial Interface (DSI) is a specification by the Mobile Industry Processor Interface (MIPI) Alliance aimed at reducing the cost of display controllers in a mobile device. Name CPU Pin Name Primary Function Description GPIO Capable Voltage Connector DSI_D0_P... -
Page 34: Boot Mode Pin
5.10 Boot Mode Pin Boot mode pins 47, 49 of the A Connector determine how the module boot. The following table lists the possible options of the boot mode: BOOT_MODE1 (PIN 49) BOOT_MODE0 (PIN 47) Action Boot From Fuses (DEFAULT) Serial Downloader* Table 16 If pins are left open the Default config is “Boot from Fuses”. -
Page 35: How To Connect The Audio Interface
5.11 How to connect the Audio Interface The figure shows how to connect the module I2S interface to a low-power stereo codec, e.g. NXP SGTL5000, that includes headphones and is designed to provide a comprehensive audio solution for portable products that require line-in, mic-in, line-out, headphone-out and digital I/O. -
Page 36: How To Connect The Reset Pin
5.12 How to connect the reset pin The nRESET signal Pin 85 on A connector, has input/output functionality and shall be driven in open-drain mode. The signal has an internal 10K pull-up and a 50 Ohm series resistors; the maximum recommended capacitive load is about 1nF. Figure 15 : driven low by SOM during the POR state Delay... -
Page 37: Peripheral Multiplexing
Chapter 6 6. Peripheral multiplexing This Chapter gives the alternative peripheral information Section includes： ✓ ✓ ✓ UART ✓ ✓ ✓ ✓ ✓... -
Page 38: Peripheral Multiplexing Description
6.1 Peripheral multiplexing description Following is described the opportunity to use alternative interfaces using the properties of multiplexing pin. Please consider that customization of the module can cause the loss of compliance with MicroGEA's standard. Note: The i.MX8ULP’s peripherals are implemented on both Cortex A35 and M33, so the CPU pads associated to PTA, PTB, PTC are implemented on Cortex M33, the pads associated to PTD, PTE and PTF are implemented on Cortex A35. - Page 39 LPSPI4 signals interfaces (Application Domain – Cortex®-A35) Pin on connector A Pin on connector B Pin Name on i.MX MicroGEA Signal Voltage reference reference PTF9 PTD21 LPSPI4_SOUT +3,3V PTF8 PTD20 LPSPI4_SIN +3,3V 8/39 PTF11/PTD23 LPSPI4_PCS0 +3,3V 10/34 PTF10/PTD22 LPSPI4_SCK +3,3V 73/78 PTE8 PTD16 / PTF4...
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Page 40: I2S Configuration
6.1.2 I2S Configuration The following tables show the pin configurations for I2S Bus on module's connector. I2S0 bus interfaces (Real Time Domain – Cortex®-M33) Pin on connector A Pin on connector B Pin Name on i.MX MicroGEA Signal Voltage reference reference PTC4 I2S0_RXD0... -
Page 41: I2C Configuration
6.1.3 I2C Configuration The following tables shows an alternative I2C configuration. I2C0 Interfaces (Real Time Domain – Cortex®-M33) Pin on connector A Pin on connector B Pin Name on i.MX MicroGEA Signal Voltage reference reference 41/67 PTA16 PTA0/ PTA8 LPI2C0_SCL +3,3V 25/ 90 PTA9/ PTA17... -
Page 42: Alternative Uart Pins Tables
6.1.4 Alternative UART PINs tables The following tables show an alternative UART configuration. UART0 interfaces (Real Time Domain – Cortex®-M33) Pin on connector A Pin on connector B Pin Name on i.MX MicroGEA Signal Voltage reference reference 41 / 62 PTA16 PTA0/ PTA12 LPUART0_CTS (Input) -
Page 43: Sd Interfaces
6.1.5 SD Interfaces The following tables show the pin configurations for SD on module's connector. SDHC1 interfaces (Application Domain – Cortex®-A35) Pin on connector A Pin on connector B Pin Name on i.MX MicroGEA Signal Voltage reference reference PTD16 SDHC1 CD +3,3V 32 / 84 PTD21/ PTF1... -
Page 44: Pwm
6.1.7 PWM It's possible to set the pins shown in the tables as PWM signals. Pin on connector A Pin on connector B Pin Name on i.MX MicroGEA Signal reference Voltage reference PTA1 TPM0_CH0 +3,3V PTA16 PTA2 TPM0_CH1 +3,3V PTA17 PTA3 TPM0_CH2 +3,3V... -
Page 45: Adc
6.1.8 ADC The following table shows the pin configurations for ADC signals. (Real Time Domain – Cortex®-M33) Pin on connector A Pin on connector B Pin Name on i.MX MicroGEA Signal Voltage reference reference PTA8 ADC1_CH0A +3,3V PTA9 ADC1_CH0B +3,3V PTA10 ADC1_CH1A +3,3V... -
Page 46: On-Line Support
Engicam explicitly reserves the rights to change or add to the contents of this manual or parts of it without special notification. All operating parameters must be validated for each customer application by customer’s technical experts.
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