Truth Table For Store/Display Clock; Latch Clock Timing For 4-Channel Operation - Tektronix 7D01 Instruction Manual

Theory of Operation—7D01 (SN B020000 & up)
STORE/DISPLAY CLOCK GATE
U110
INPUTS OUTPUTS
PINNUMBER@=® 11.107 ~—S5. | | 14* 2
x HI LO HI LO LO
Xx HI LO LO] HI HI
HI LO HI x LO LO
LO LO HI x HI LO
* ALSO PINS 12, 3, AND 4
X INDICATES EITHER STATE
1967-54
Figure 3-3. Truth Table for Store/Display Clock Gate.
U268B in the Word Selector stage of the Word Recognizer
circuit. The outputs of U106A and U106B arealso con-
nected to pins 5 and 9 of gates U108A and U108B,
respectively.
When the SAMPLE INTERVAL switchis in the EXT posi-
tion, the external store signal at pins 6 and 10 of U108A
and U108B is LO. With one input of each gate LO,the gates
are enabled. (Pins 7 and 11 of U108 are LO during Store
mode.) The output signal from U106A or U106B is inverted
and coupled through U108A or U108B. The outputs of
U108A, U108B, U110A, and U110B are connected together
in '"wired-OR" configurations. A HI output from any of
the gates will drive the output lines HI. When the SAMPLE
INTERVAL switch is not in the EXT position, the external
store signal is HI, disabling U108A and U108B. When the
7D01 is in the Store mode, the store signal from the Trigger
circuit is HI. The store signal is connected to pin 10 of
U110B and pin 6 of U136B. Exclusive-OR gate U136B
inverts the store signal and connects it to pin 7 of U110A
and pins 7 and 11 of U108. When the store signal is HI,
U110B is disabled and U110A is enabled. U110A couples
the store clock signal from the Time Basecircuit.
Latch Clock
The Latch Clock, U120, U132A, and U136A, strobes data
into the Data Latch from the Data Selector. The timing of
the Latch Clock output depends on the setting of the
DATA CHANNELSswitch.
FOUR CHANNEL. Figure 3-4 showsthe timing of the
Latch Clock outputs for 4-channel operation. When DATA
vee UU
PIN 3, 12
U120, Q0 | |
U120, Q1 | |
U120, a2 J | |.
U120, Q3 | |
U132A
carey
|
|
CLOCK)
1967-55
Figure 3-4. Latch Clock timing for 4-channel operation.
CHANNELSswitch $1218 is set for 4-channel operation,
pins 12, 11, and 9 of U120 are held HI. When the Q2 out-
put of U120 (also connected to pin 10, function select
input) is LO, the next rising edge of the clock transfers the
data at the D@ through D3 inputs to the outputs. When the
data from the DATA CHANNELS switchis transferred to
the outputs, the O@, Q1, and O2 outputs go HI (the D3
input is open or LO). A HI level at the S1 input (pin 10)
sets U120 into the shift-left mode. Each rising edge of the
clock signal moves the data at each output of U120 to the
next output, until the Q2 output returns to a LO level.
This occurs every fourth clock pulse. Gate U132A produces
a HI output when both the Q3 output of U120 and the
clock signal are LO. The output of U132A is connected
through U136A to the clock inputs of the Data Latch
stages. Buffer U136A delays the output of U132A to
compensate for propagation delays through the circuitry.
EIGHT CHANNEL. Figure 3-5 showsthe timing of the
Latch Clock outputs for 8-channel operation. When the
DATA CHANNELSswitch is set for 8-channel operation,
pins 12 and 9 (D@and D2) of U120 are held HI. When the
Q2 output of U120 is LO, the rising edge of the next clock
pulse transfers the data at the D@ through D3 inputs to the
outputs. When the input data is transferred to the outputs,
the Q@ and Q2 outputs go HI. A HI level at the S1 input
(pin 10) sets U120 into the shift-left mode. The next rising
edge of the clock signal moves the LO level at the Q1
output to the O2 output. With the S1 input LO, U120 is
again ready to transfer data from the inputs to the outputs
on the next rising edge of the clock signal. The output of
U132A is HI when both the O3 output of U120 and the
clock signal are LO. This occurs every second clock pulse.