Ic912 (V Driver); Ic905 (H Driver, Cds, Agc And A/D Converter) - FujiFilm FinePix S2000HD Service Manual

3. Schematics
3-1-3.

IC912 (V driver)

The V driver (IC 912) is needed to create the clocks that
drive the CCD (vertical transfer clock and the clock for
the electronic shutter). XV1 to XV17 output by IC101 are
superimposed by the vertical transfer clock onto XV1, XV3,
XV5, XSG7, XSG9 and XSG11 in IC912 so as to generate
XSG1 to XSG10 as 3-value pulses. XSUB output from IC101
is the discharge pulse for the electronic shutter.
GND
V1
Level
V2 OV2
conversion CH1 conversion
VL
GND
Level
V4 OV4
CH2 conversion
conversion
VL
GND
Level
V6 OV6 V3
conversion
CH3 conversion
VL
GND
Level
OV8
V8
conversion
CH4 conversion
VL
GND
Level
V10 OV10
V5
conversion
CH5 conversion
VL
GND
Level
OV12
V12
conversion
CH6 conversion
VL
GND
Level
V7S OV7S
conversion V7
CH7 conversion
VL
GND
Level
V9L OV9L
conversion
CH8
conversion
VL
GND
Level
V9R OV9R
conversion
VL
GND
Level
V11L OV11L
conversion
VL
GND
Level
V11R OV11R
conversion
VL
<Fig 3-3. IC912 block diagram>
3-2
VH GND VH GND
V9
Level
Level
OV1A OV9A
CH9 conversion
VL VL
VH GND
VH GND
Level
OV1B Level
OV9B
CH10 conversion
VL VL
VH GND
VH GND
V11
Level
Level OV11A
OV3A
CH11
conversion
VL
VL
VH GND
VH GND
Level Level
OV11B
OV3B
CH12
conversion
VL
VL
VH GND
Level
OV5A
VH GND
VL
SUB
Level
OSUB
VH GND
SUBCNT conversion
VL
Level
OV5B
VL
VH GND
Level
OV7A
VL
VH GND
Level
OV7B
VL
Confidential: FUJIFILM Service Center Use Only
FinePix S2000HD Service Manual
3-1-4. IC905 (H driver, CDS, AGC and A/D
converter)
IC905 includes the H driver, CDS, AGC and A/D conversion
functions. It internally emits H1, H2, H3, H4 and RG as reset
pulses and the horizontal clock driver for the CCD image
sensor and outputs them to the CCD. The video signals
output from the CCD are input to pin 25 on IC905. It has
an internal sampling hold block that uses SHP and SHD
pulses, and uses this to implement CDS (Correlated Double
Sampling). After passing through the CDS circuit, the signals
are sent through the VGA (Variable Gain Amplifier) circuit
and internally converted to Low-Voltage Differential Signals
(LVDS) before being input to IC101.
VGA gain is controlled at pins (32), (33) and (34) using serial
signals output from IC101.
-3, 0, +3, +6dB
CDS
CCDIN
3V INPUT
LDO
REG
1.8V OUTPUT
RG
HORIZONTAL
HL
DRIVERS
4
H1 TO H4
GP01
GP02
<Fig 3-4. IC905 block diagram>
REFT REFB
AD9971
VREF
6~42 dB
12-BIT
REDUCED
VGA
ADC
RANGE
LVDS
OUTPUT
CLAMP
INTERNAL
CLOCKS
PRECISION
INTERNAL
TIMING
REGISTERS
GENERATOR
SYNC
GENERATOR
HD VD CLI
TCLKP
TCLKN
DOUT0P
DOUT0N
DOUT1P
DOUT1N
SL
SCK
SDATA