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Circuit Description
The receiver consists of a single main PCB. Circuit diagrams are in the
pocket on the rear cover. Some receivers may have an extension board
in place of the main microprocessor U700 (see page 20).
The adjacent "main" block diagram shows the main functional blocks.
For copyright reasons, the VideoCrypt functions are given on a sepa-
rate sheet. (See the pocket on the rear cover.) The following descrip-
tion is for receivers with an integral VideoCrypt decoder. Most of this
also applies to non-VideoCrypt receivers; The differences are indicated
'on page 24.
TUNER AND VIDEO PROCESSING
Tuner
When a programme is selected via the handset, data received by the
sensor IR 700 is fed, as TTL level data, to the microprocessor U700. In
turn U700 supplies tuning data to a frequency synthesiser U100. The
synthesiser forms the reference oscillator for the phase locked loop
which controls the local oscillator in the tuner. The prescaler output of
the tuner is obtained by dividing the local oscillator frequency by 128.
The local oscillator is set 479.5 MHz higher in frequency than the
chosen programme and is mixed with the incoming signal. The signal
is then amplified by an IF stage centred at 479.5 MHz with a band-
width of 27 MHz. The 479.5 MHz FM signal is then demodulated in the
tuner to give the required composite video baseband signal (CVBS)
output.
The frequency synthesis is performed by U100 which receives divider
ratio data for the required programme via the 3-wire serial bus from
the microprocessor U700. The data is on pin 5, clock on pin 4 and
select on pin 3 of U100. The synthesiser generates a reference fre-
quency from the 5.625 MHz crystal (X100) input on pins 1 and 2. The
prescaler input on pin 11 of U100 is divided down according to the
divider ratio sent from U700 and compared with the generated
reference (see also the diagram on page 20). The error signal from the
phase locked loop (pulses on pin 14 of U100) is integrated by Q100
and associated components. These determine how much of the 30 V
supply appears as the tuner control voltage on pin 15 of the tuner. The
5V supply to the tuner is on pin 12.
To compensate for the LNB's local oscillator frequency conversion
offsets, information on the position of the signal relative to the
27 MHz bandpass filter within the tuner passes from pin 10 of
TUNER100 to pin 35 of U700. The frequency synthesised within U100 is
then varied under control from U700. This automatic frequency
control (AFC) keeps the signal central in the 27 MHz bandpass filter.
in dual-input models of the receiver, the Tuning Menu can be used to
specify whether a programme is received via LNB 1 or LNB 2. The line
LNB_SELECT controls both the supply and select for the LNBs and
comes from pin 21 of U700. Pin 4 of the tuner is the select line for
LNB1 and it is enabled by Q106; pin 6 is the select line for LNB 2 and it
is enabled by Q107. Power to the LNBs passes through the tuner via
pin 3 for LNB 1 and pin 5 for LNB 2. There are further details about the
LNB supply in the SMPS circuit description on page 19.
The baseband signal from pin 13 of the tuner is low pass filtered by
R110, C112, C113 and L100. It is then buffered by emitter follower
Q101 and AC coupled into the video input pin (pin 20) of the sound
and video processor and switch matrix (U500) by C548. The baseband
signal from U101 emitter is also high pass filtered by C556, C555, C549,
R539, R538 and L503 to filter out the video, and the resulting audio
subcarriers are input to the FM input (pin 23) of the sound and video
processor (U500).
Dual Bandwidth Tuner
The bandwidth of the tuner is controlled by the BANDWIDTH control
line which comes from pin 14 of the modulator chip U200. This pin is
an open collector output and must have the pull up resistor R112
fitted to function properly. U200 is under the control of the
microprocessor U700 via the ?C bus.
MSS 100 Series Satellite Receiver
ENGLISH
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