Memories And Battery Supplies; Eproms; Ram; Battery Buffered Ram - HP 8153A Service Manual

Signal LDS triggers PAL UI09 which generates the data acknowledge
(LDTACK) signal after a programmed number of clock cycles. This
delay depends on PA17, PA18 and PA19, LAS and LI~TACK.
Memories and Battery Supplies
This section describes the circuitry shown in schematic lB.
EPROMs,
EPROMs U20l, U202 and U204 are the devices in which all
the fìrmware instructions for the instrument are stored. The
programming is done at the ti me of manufacturing.
Data is read from an EPROM, by selecting and enabling the
device and sending the address of the desired memory location.
The EPROMs are selected with signals LMEMOS, LMEMIS and
LMEM2S from the address decoder UI05. The outputs are enabeled
by signal LREAD from the interface control circuit Ul03, Ul04.
RAM
RAM U208 is the working memory for the microprocessor. Data can
be written into, as weli as re ad out of, a RAM memory location.
During power on the EPROM data (fìrrnware) from the inserted
modules are stored in this memory for further processing.
Selection is made with signal LMEM4S from the address decoder.
Read write function is determined by signals LREAD and LWRITE
from the interface control circuit UI03, UI04.
Battery Buffered RAM
RAM U209 is used to stare application and customer specifìc data
(such as HP-IB address, display brightness, module parameters
etc ... ). A battery voltage is applied to this RAM when the
instrument is switched off', and this data is preserved. In addition,
the battery supplies the Real Time Clock U406 (schematic lD) after
power off.
The battery voltage supply is controlled by the LPOR signal from
the reset circuit (Ul09, see "Reset Circuit (Ul09) with Buffers
(Ul04)").
Device-Bus Interface
This ìnformation deals with schematic lC.
Data and addresses to and from the modules are sent via the device
bus interface.
LDBS clocks the address latches and the data buffers.
The channels (modules) are selected by the address latch U503 and
the multiplexer U401. Addresses for the module are latched by U502.
1-2 Theory of Operation