Epiq Solutions Sidekiq Z2 Development Manual
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Also See for Sidekiq Z2:
- Hardware user manual (64 pages) ,
- Getting started manual (2 pages)
Related Manuals for Epiq Solutions Sidekiq Z2
Summary of Contents for Epiq Solutions Sidekiq Z2
- Page 1 Sidekiq Z2 and Matchstiq Z3u FPGA Development Manual Version 3.16.2 Updated 03/10/22...
- Page 2 Disclaimer Epiq Solutions is disclosing this document (“Documentation”) as a general guideline for development. Epiq Solutions expressly disclaims any liability arising out of your use of the Documentation. Epiq Solutions reserves the right, at its sole discretion, to change the Documentation without notice at any time.
- Page 3 Sidekiq Z2 and Matchstiq Z3u FPGA Development Manual...
- Page 4 3.15.1 Documentation update only relating to fpga programming and packed Updated mode not being available on the Z platforms. 10/29/21 03/10/2022 3.16.2 Z3u: Add board_id to the FPGA_REG_VERSION register for Zu3 RevD. Sidekiq Z2 and Matchstiq Z3u FPGA Development Manual...
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Page 5: Table Of Contents
8.3.2 Building Matchstiq Z3u......................28 8.4 Build with Windows........................29 8.5 Programming..........................29 8.5.1 Programming the Sidekiq Z2 FPGA..................29 8.5.2 Programming the Matchstiq Z3u FPGA................29 8.6 Testing the Bitstream........................ 29 8.7 Using JTAG for Debug......................29 Sidekiq Z2 and Matchstiq Z3u FPGA Development Manual... - Page 6 Table of Figures Figure 1: Sidekiq Z2 Simplified Block Diagram..................13 Figure 2: User App Block Diagram.......................14 Figure 3: Sample Timing Diagram......................17 Figure 4: Sample User App to IIO Diagram..................18 Figure 5: Sidekiq Z2 Zynq Processing System..................25 Sidekiq Z2 and Matchstiq Z3u FPGA Development...
- Page 7 Table of Tables Table 1: Terms and Definitions......................11 Table 2: Rx Control Register........................ 15 Table 3: User Registers........................19 Sidekiq Z2 and Matchstiq Z3u FPGA Development Manual...
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Page 8: About This Document
This document provides the necessary details for developing FPGA applications on the Sidekiq SDR or the Matchstiq Z3u SDR developed by Epiq Solutions [1]. It is provided with the purchase of a Sidekiq Z2 Platform Development Kit or a Matchstiq Z3u Platform Development Kit. -
Page 9: Introduction
Epiq Solutions. The Sidekiq Z2 PDK reference design and the Matchstiq Z3u reference design does, however, utilize certain critical components from the Analog Devices' IIO design, and details for building both the EVK (Sidekiq Z2 only) and PDK components to achieve a final bitstream is described in Section 8. -
Page 10: References
Available at: https://epiqsolutions.com/support [5] Analog Devices, Inc. IIO and Support www.analog.com [6] Matchstiq Z3u Hardware User Manual Epiq-Solutions-Matchstiq-Z3u-Hardware-User-Manual_vx.x.pdf Available at: https://epiqsolutions.com/support [7] Sidekiq Z2 Getting Started Guide Z2 Getting Started Guide.pdf https://epiqsolutions.com/support Sidekiq Z2 and Matchstiq Z3u FPGA Development Manual... -
Page 11: Terms And Definitions
Field Programmable Gate Array Free-running counter Industrial I/O (Analog Devices, Inc.) In-Phase / Quadrature Phase Intellectual Property Megahertz Personal Computer Platform Development Kit Radio Frequency Receive Software Defined Radio Transmit Table 1: Terms and Definitions Sidekiq Z2 and Matchstiq Z3u FPGA Development Manual... -
Page 12: Fpga Reference Design
In Figure 1, red blocks are available in RTL, but should not be modified. Yellow blocks should not require modification, but certain applications may necessitate changes. Green blocks are the intended targets for user modification. Sidekiq Z2 and Matchstiq Z3u FPGA Development Manual... -
Page 13: Top Level
Figure 1: Sidekiq Z2 Simplified Block Diagram 7.2 Top Level The Top Level block, sidekiq_z2_top (Sidekiq Z2 and Matchstiq Z3u share the some top level RTL file) is the top-level RTL and instantiates various blocks. This section will serve to describe each block's functions and use. -
Page 14: User_App
Sidekiq and Matchstiq variants. This allows end users to share user_app modules between platforms and allow upgrades to future platforms with minimal rework required. Figure 2: User App Block Diagram Sidekiq Z2 and Matchstiq Z3u FPGA Development Manual... -
Page 15: User_App Signals
RF chip is not running or no external reference is present. For Sidekiq Z2 and Matchstiq Z3u, this is the same clock as the host_clock. ref_clk is an accurate 40MHz clock shared with the RF chip. If no external reference is present or if the RF chip is turned off, this clock will not be present. -
Page 16: Rx Path Inputs To User_App
Sidekiq Z2 and Matchstiq Z3u supports one I/Q channel. While sample_valid is high, each rising edge of the sample clock delivers a new sample consisting of twelve bits each of I and Q data. Each channel must be enabled by software before the sample_valid signal will go high. -
Page 17: Outputs From User_App
IIO. This allows users to transfer extra data with each set of 1018 samples. The metadata is latched in on each the first of the 1018 data words. Sidekiq Z2 and Matchstiq Z3u FPGA Development Manual... -
Page 18: User_App Tx Interface
Within the user_app, user_reg_if provides an address space to drive or read status of user logic. As the functionality of user_reg_if is nearly identical to reg_if, please see Section 7.4 for information. The code comments within user_reg_if serve to provide a template for adding user registers. Sidekiq Z2 and Matchstiq Z3u FPGA Development Manual... -
Page 19: Reg_If / User_Reg_If
(FPGA driven) registers are: SW Address (hex) FPGA Name R / R/W 0x8700 reg_7_0 0x8704 reg_7_1 0x8708 reg_7_2 0x870C reg_7_3 0x8710 reg_7_4 0x8714 reg_7_5 0x8718 reg_7_6 0x871C reg_7_7 Table 3: User Registers Sidekiq Z2 and Matchstiq Z3u FPGA Development Manual... -
Page 20: Iio_Data_If
Sidekiq Z2 and Matchstiq Z3u only supports one channel of Rx and one channel of Tx. Being able to adjust the size of the Tx FIFO is not required like it is on older platforms that use the PCIe interface. -
Page 21: Gpio/Uart
PS. Signals associated with the latter case can be found as top level pins of sidekiq_z2_top.v that route to the Zynq system wrapper module. Please see the Sidekiq Z2 Hardware User's Manual [4] and Matchstiq Z3u Hardware User's Manual [6] for more detailed information regarding these gpio and uart pins and functionality. -
Page 22: System_Wrapper
PL, and modifications to the adc_dma module to support packet streaming with timestamp capability. A block diagram of the Zynq processing system used by Sidekiq Z2 is shown below. This image is just to give a feel for the architecture of the system block design. For the actual schematic, open your vivado project in gui mode, and double click on the system.bd file in your design. - Page 23 Sidekiq Z2 and Matchstiq Z3u FPGA Development Manual...
- Page 24 Sidekiq Z2 and Matchstiq Z3u FPGA Development Manual...
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Page 25: Figure 5: Sidekiq Z2 Zynq Processing System
Figure 5: Sidekiq Z2 Zynq Processing System Sidekiq Z2 and Matchstiq Z3u FPGA Development Manual... -
Page 26: Building And Debugging
On Sidekiq Z2, the period constraint for sample_clk_a is defined by the data_clk constraint found in the user_app_sidekiq.xdc file within the user_app directory. -
Page 27: Custom User_Apps
See the add_files commands for the existing *.xci in the build script that applies to your platform (Sidekiq Z2 or Matchstiq Z3u). Use this as a template for the command line that you will need to add. If you do not include all necessary modules, the build will fail with an error indicating what needs to be added to the project. -
Page 28: Build With Linux
Note that the only supported Vivado version for Sidekiq Z2 is 2018.2. The Sidekiq Z2 FPGA is now built as part of the top level project wide linux build process. Once you have the plutosdr-fw directory sitting in your current working directory, you can build the entire project with a top level make command. -
Page 29: Build With Windows
Development Manual [2] for descriptions of the provided test apps. Each app can be run without any parameters to view proper usage and view the command line parameters that are available for each app. Sidekiq Z2 and Matchstiq Z3u FPGA Development Manual... - Page 30 Both Xilinx and Digilent type programmers can be connected to the JTAG port on the I/O Access card. Please see the Sidekiq Z2 Hardware User's Manual [4] or the Matchstiq Z3u Hardware User's Manual [6] for more information on the I/O Access/JTAG breakout card and it's associated JTAG port.
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