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BE-2520
5-6. Calendar timer control
:
2) Significance of RP5C15 input/output signals -:
pec1s
Signal name
—
Discription
Used for interfacing with an external device.
;
Valid when CS = H and CS = L. Connected to the
S6P
:
A4 line.
RESET 2
5
-
:
:
:
Cc
reat
cs
Connected to the RESET line.
p woe J
z
ea)
32. 768K
CKOUT
Basic clock output
:
A0-A3
Address input. Connected to the CPU address bus
RC-KZ1018CCZZ
1/O contro! input. Goes low when data:is read
| from the. PR5C15
to the CPU.
1/0 control input, Goes low when data is read
| from the CPU to the PR5C15.
Calender timer data input/output
Alarm output (1Hz or 16Hz), not used.
The CPU controls the calendar timer chip RP5C15.
f
.
.
:
OSCIN
32.768KHz crystal oscillation input
1) The calendar timer is read and written using the AO—A4
—t—
1/O command. The data can be read or written by spe-
OSCOUT
| 32.768kHz crystal oscillation output
cifying the 1/O address of the specific register.
vcc
Connécted to the VRAM
5-7. Key, mode switch and display control
Display Tube
Key matrix
Mode SW
® ©
inverter
CPU
4-16 Decoder & Latch
(uPD780)
(Dis
rev
play digit
LHOO080
key scan)
3-State Buffer
4514
®
®
Chip Select
Decoder
Circuit
SN74LS138
"SGS: Segment select (a ~ g)
KRO ~ KRB5: Key read (mode SW)
MCS: Segment, buzzer select (DP, COM, W, buzzer)
G1 ~ G13: Displyay digit
SCS: Display digit (key scan) select
a~ g, DP,-COM, ¥: Display segment
KRS: Key read select
BZ:
Buzzer
KSO ~ KS6: Key scan
KS7:
Mode switch scan
—31-
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