Pioneer DV-45A Service Manual page 99

@ Pin Function
[rT SSCSCSC~C~SCSCS im Functions
LN iomiaewee ST
in Stabe sale 8 6H]
| ow | This order effective / invalidity of data done a sample of by BD pin.
It is done a sample with a start edge of BCLK.
[no]
[aor 208 [BOTT
9006 MD LISI
Data transfer line with SDRAM
97-102
|
53-55
58-63 |MA [11:0] OUT {Address line of SDRAM
65, 67, 69
66,68 |MBA [1:0] SDRAM bank choice line
OD QO Cc
70 DCS
OUT |Chip select of SDRAM
RAS (Row Address Strobe) control line of SDRAM
78 CAS OUT |CAS (Column Address Strobe) control line of SDRAM
ae oe
|} 83 [DOML DQM control line of SDRAM
OUT
OUT
DWE WE control line of SDRAM
OUT
UT
83
MCLK | OUT | Movement clock of SBRAM
182
PXCLKP OUT |54MHz pixel clock
PXCLK O 27MHz pixel clock
ae ee PD [7:0] Digital pixel data.
188-192
;
Y/Cb/Cr is done multiple of by 8 bit bus, and it is output.
CSYNG Composite SYNC signal input terminal
OSDKEY UT [OSD key flag output
PWD OUT |The phase comparator output for external synchronization movement
HSYNC Horizontal synchronizing signal output pin
} 180 | VSYNC OUT |Vertical synchronizing signal output pin
OUT Serial PCM data for DAC
It output Ls/Rs data.
Serial PCM data for DAC
DACGCLK Exaggerated sample movement clock of DAC
} 161 | CDBCK | iN | The pulse code modulation bit clock which is input by CDDSP
| IN
[e)
=
OUT
OUT
Serial PCM data for DAC
AAD OUT {Anciallary data output
It output C/Sw data.
zc °
Lg It output Lf/Rf data.
166
167 Serial PCM data for DAC
188 It is for the down mixture output.
159 LRCLK Clock for channel distinction of pulse code modulation audio system data (L/R)
CDLRCK The UR clock which is input by CODSP
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