3-3-4, A/D And D/A Conversion; Clock Generation Circuit Biock 0; Usb Interface In Cstessecccassccescscvccecssbeassstiacsetivccnseunesdieesvavenes; Thermal Head Bock - Sony UP-897MD Service Manual

3-3-4. A/D and D/A Conversion
The video signal output from a video circuit (IC501) is
converted into a digital signal using an A/D converter and
transferred to memory using a system control circuit
(IC104). The A/D-converted data is D/A-converted using
a video encoder in the system control circuit (C104) and
input to a video circuit 7C501). After that, the data is
output to the BNC connector via the selector switch in a
video circuit. In ordinary EE, instead of this path, data is
looped in a video circuit and output via the selector switch
described above. Data is output from a system control
circuit in the case of the scale change for which a video
signal is processed.
3-3-5. Clock Generation Circuit Block
A clock of 23.04 MHz is generated as the sampling clock
of a video signal using a clock circuit (C509). The phase
of the clock generated using this clock circuit is adjusted to
the phase at the falling edge of an HD pulse (horizontal
sync pulse) during image read operation. The read
position can be always made constant when the phase
relation between the HD pulse and clock is compensated.
FE 10512 a
IC509 SYSTEM
vari ctock ic |CLK-OUT. | conTROLL
HD_OUT 10104
Ic
0
23,04MHZ
IC502
A/D
CONVERTER
ey ie
|
Clock generation circuit
3-4. USB Interface
There is a USB1.0 interface (mini B connector) for
firmware rewrite operation. The USB1.0 interface is
controlled by IC104 (TMS320DM310ZHK22). Refer to
"2-6. Firmware Version Upgrade" for how to rewrite
firmware.
3-4
3-5. Thermal Head Block
3-5-1. Structure
A thermal head consists of 1280 dots (64 bits X 20) per
line.. There are twenty pairs of blocks below.
VH
Output-stage
transistor
LATCH Latch block
>—Ler [eet ost GT bes
P>—Lor foe [eT GT bee |
CLK —>- Re
Internal circuit configuration of thermal head
(corresponding to one port)
Shift register
block
DATA
Print data
DATA SS
64CLK
CLK
Wo =—tsti<'"C™SOSOSOCO(;*COO~*~;~™S
|}«——| Head heating time
STROBE
Timing chart
3-5-2. Basic Operation
Each signal is input from IC202 to the thermal head for
operations below.
(1) Print data is input to the shift register block in
synchronization with a CLK pulse. (64-bit data)
(2) The data input in step (1) is moved from the shift
register block to the latch block when a latch pulse is
input.
(3) When a STB pulse is input, the "H" and "L" data of a
latch block turn on and off an output-stage transistor
and a resistor is heated for the color development of
thermosensible paper.
UP-897MD