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of a specimen are to be measured, the indicator meter is switched to the
amplitude detector.
The indicator then operates with zero at the left end of
the scale. When only capacitance is to be measured and conductance is to be
ignored, the indicator is switched to the phase detector.
In this mode, the
indicator operates zero center.
The mode to be used is selected by the switch
just beneath the meter:
ZERO LEFT for both capacitance and conductance;
ZERO CENTER for capacitance alone.
Figure 3 shows the 75D in simplified block form.
The unbalance signal from the bridge is fed to the pre-amplifier stages VI01
and VI02.
Output from the pre-amplifier is then coupled to V201 in the
Oscillator-Detector section, where the signal is split into two paths.
One
signal path goes to the phase detector chain, while the other goes to the
amplitude detector.
The amplitude detector is basically a straight amplifier circuit (V202) and a
diode rectifier (CR204).
The dc output of this rectifier is applied to thenull
indicator meter.
To prevent errors and difficulties resulting from the presence
of stray rf fields, oscillator harmonics and other extraneous signals,
the
signal input to V202 is passed through a highly-selective quartz crystal filter
(Y201 - Y202). This two-section filter exhibits a passband of between 50 and
100 Hz, with very steep skirts.
Figure 4 shows, in a simplified schematic, the phase detector circuits.
The
1 MHz signal resulting from a bridge unbalance is amplified and fed to the
phase detector at the junction of C204, L203 and C209.
The
parallel-resonant tuned circuit formed by L203, C204 and C205 causes
an equal and opposite voltage to appear at the junction of C205, L203 and C210.
These two voltages are applied to diodes CR202 and CR203, while the reference
voltage from the oscillator is applied to the junction of these two diodes.
When the PHASE control (Cl07) is correctly adjusted, the input voltages to the
phase detector resulting from a capacitive unbalance are set so that one is in
phase with the reference voltage and the other is 180° out of phase with it.
The input voltages resulting from a conductance unbalance, on the other hand,
are such that one leads the reference voltage by 90° and the other lags by 90°.
The input voltages are combined vectorially with the reference voltage in the
phase detector.
For the condition of a capacitive unbalance in the bridge, one
input (in phase wih the reference voltage) adds to the reference vector, while
the other input ( 180° out of phase with the reference voltage) subtracts from
the reference vector.
These voltages are combined and rectified by CR202
and CR203.
The resultant dc outputs are such that one becomes less negative,
while the other becomes more negative.
These dc voltages are applied to the
grids of the dual-triode dc amplifier V301 .
As the dc grid potentials under
these conditions are not equal, there is a resultant change in the anode current
which deflects the null indicator accordingly.
75D
b-370
9
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