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IC BLOCK DIAGRAM
Pin | Pin
20 | EFM
21 | VSEL
Function
DC
Pin
Pin
Wie)
Function
bc
Volt
No.
| name
Volt
Output of EFM comparator
4.1V
22 | ASY
I
Input of auto asymmetry
_
(voltage measured at open
control amplifier.
state).
23 | DVcc}
— | Positive power supply for
+5V
Reference input level setting
+5V
:
EFM comparator.
pin for auto asymmetry
24 | Vcc
—
| Positive power supply
+5V
control amplifier. Vcc with
+5V power, GND with +10V
power.
1€201 CX20108 SERVO SIGNAL PROCESSOR
GNO
TG!
FF
uA
a
COMPARATOR 1
Riera j
IIL LOGIC
Function
TAO
TAO
DIRC
SL®
SLO
SLO
FEO
FEO
FE
ATSC
FS3
Vee
Pin
No.
Pin
name
SRCH
1/0
Function
2 | TA (+)
=
4/TE(-) | —
5 | SENSE
Oo
6 | C. OUT
O
7 | XRST
Gain selection pin of tracking
amplifier.
It is opened or set at ground level.
Non-inverted input of operational
amplifier 2.
Output of operational amplifier 4.
Inverted input of operational
amplifier 4.
Output of SSP internal state in
accordance with CPU > SSP
addresses.
(The output varies depending upon
the address contents of internal
serial register.)
Output for track number counting at
the time of high speed accessing.
All the contents of internal register
are cleared with CPU > SSP set at
Low level. This signal is connected
to CPU reset pin.
8 [DATA
9 [XLT
10
jCLK
11
|MIRR
+
Serial data transfer of CPU > SSP.
This signal is input from LSB.
DO — D7.
Serial data latch of CPU > SSP.
When this signal is at Low level, the
contents of internal serial shift
register are transferred to the
respective addressdecoded latches.
After the transfer, it is needed to
return it to High level as there arises
no trigger signal.
Serial data transfer clock for CPU >
SSP.
Data entry is allowed at the falling
edge of this signal. Before or after
the transfer, it is needed to set the
signal at High level.
Mirror signal input from RF amplifier.
— 1 5—
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