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2-4. Clock generator
The basic pulse circuit is not provided in the ER-1921/2396 itself. An
independent oscillation circuit is provided in each device (CPU,
CKDC-III)
4) #PD7811A CPU oscillation circuit (main-PWB)
31
30
Oo 12MHZ
33PF x2
Ty.
Fig. 2-4
X2
x1
CPU
pPD7811A
Basic clock is supplied from a 12MHz ceramic oscillator,
'The CPU contains an oscillation circuit from which the basic clock is
internally derived. If the CPU was not operating properly, the signal
dose nat appear on this line in most cases.
2) HD4708A73FS CKDC-III oscillation circult
(Display-PWB)
43
22h
x!
x1
1M
o
4.19MHz
42
zp
CKDC III
48
X2
is
32.768KHz
$I]
c3t
_[o2
HD4708A73FS
455)
39P
Fig. 2-5
Two oscillators are connected to the CKDC-iII.
The main clock X1 generates 4.19MHz which is used during power
on.
When power is tumed off or when the MODE switch is set
to the OFF
position, the CKDC-III goes into the standby mode and the main
clock stops.
The sub-clock X2 generates 32.768KHz which is primarily used to
update the internat RTC (real time clock). During the standby mode, it
keeps oscillating to update the clock and monitoring the power recov-
ery.
24
2-5. P-OFF circult
Fig. 2-6
At power on
:
When P-ON voltage reaches 16V, the current flows through the
zener diode (MTZ16B) so that the level at point @ goes high.
The level of P-OFF rises as VCC increases. As a result, the P-OFF
signal changes from low to high level.
At power off
When the power is turned off, the P-ON voltage drops under 15V
causing the zener diode to stop current flow, which causes potential
at point @ to drop.
Power ON
Power OFF
ieee
oe
ENS, =! +30V
P-ON
GND
Se
ee
ee
POINT @:
GND
+5V
P-OFF
GND
Fig. 2-7
2-6. Reset circuit
MODE SW
SRV MODE
Fig. 2-8
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