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VIDEO CD PROCESSOR
ES3210
ES3210 PINOUT
80
79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
VPP
81
LA12
82
LA13
83
LA14
84
LA15
85
LA16
86
LA17
87
ACLK
88
AOUT/SEL_PLL0
89
ATCLK
90
ATFS/SEL_PLL1
91
DOE#
92
AIN
93
ARCLK
94
ARFS
95
TDMCLK
96
TDMDR
97
TDMFS
98
99
CAS#
VSS
100
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
ES3210 PIN DESCRIPTION
Name
Number
I/O
VDD
1, 31, 51
I
Voltage supply for 3.3V.
RAS#
2
O
DRAM row address strobe (active low).
DWE#
3
O
DRAM write enable (active low).
MA[8:0]
12:4
O
DRAM multiplexed row and column address bus.
DBUS[15:0]
28:13
I/O
DRAM data bus I/O [15:0].
RESET#
29
I
System reset (active low).
VSS
30, 50, 80, 100
I
Ground.
YUV[7:0]
39:32
O
YUV[7:0] pixel output data.
VSYNC
40
I/O
Vertical sync for screen video interface, programmable for rising or falling edge.
HSYNC
41
I/O
Horizontal sync for screen video interface, programmable for rising or falling edge.
CPUCLK
42
I
RISC and system clock input. CPUCLK is used only if SEL_PLL[1:0] = 00.
PCLK2X
43
I/O
Pixel clock; two times the actual pixel clock for screen video interface.
8-5
51
50
49
48
47
46
45
44
43
42
ES3210
41
40
39
100-pin PQFP
38
37
36
35
34
33
32
31
30
Definition
VIDEO CD PROCESSOR
ES3210
PIN DESCRIPTION (Continued)
Name
Number
PCLK
44
AUX[7:0]
54:52, 49:45
LD[7:0]
62:55
LWR#
63
LOE#
64
VSS
LCS[3,1,0]#
65:67
AUX4
LA[17:0]
87:82, 79:68
AUX3
VPP
81
AUX2
AUX1
ACLK
88
AUX0
PCLK
AOUT/
89
PCLK2X
SEL_PLL0
CPUCLK
HSYNC
VSYNC
YUV7
YUV6
YUV5
YUV4
YUV3
YUV2
YUV1
YUV0
VDD
ATCLK
90
ATFS
91
SEL_PLL1
DOE#
92
AIN
93
ARCLK
94
ARFS
95
TDMCLK
96
TDMDR
97
TDMFS
98
CAS#
99
8-5
I/O
Definition
I/O
Pixel clock qualifier in for screen video interface.
I/O
Auxiliary control pins (AUX0 and AUX1 are open collectors).
I/O
RISC interface data bus.
O
RISC interface write enable (active low).
O
RISC interface output enable (active low).
O
RISC interface chip select (active low).
O
RISC interface address bus.
I
Digital supply voltage for 5V.
I/O
Master clock for external audio DAC (8.192 MHz, 11.2896 MHz, 12.288 MHz, 16.9344
MHz, and 18.432 MHz).
O
Dual-purpose pin. AOUT is the audio interface serial data output
I
Select PLL[0] input. The matrix below lists the available clock frequencies and their
respective PLL bit settings.
SEL_PLL1 SEL_PLL0 Clock Output
0
0
Bypass PLL
0
1
54.0 MHz
1
0
67.5 MHz
1
1
81.0 MHz
I/O
Audio transmit bit clock.
O
Audio transmit frame sync.
I
Refer to the description and matrix for SEL_PLL0 pin 89.
O
DRAM output enable (active low).
I
Audio serial data input.
I
Audio receive bit clock.
I
Audio receive frame sync.
I
TDM interface serial clock.
I
TDM interface serial data receive.
I
TDM interface frame sync.
O
DRAM column address strobe bank 0 (active low).
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