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VIDEO CD/DVD COMPANION PROCESSOR
ES3207
PINOUT
80
79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
DSC_D7
81
HSYNC#
82
DSC_D6
83
VSYNC#
84
DSC_D5
85
YUV7
86
YUV6
87
YUV5
88
YUV4
89
VCC
90
ES3207
VSS
91
YUV3
92
DSC_D4
93
YUV2
94
DSC_D3
95
YUV1
96
DSC_D2
97
YUV0
98
DSC_D1
99
VSS
100
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
PIN DESCRIPTION
Name
Number
I/O
VSS
1:2,25:26,29:31,72,75,
I
Ground.
77,91,100
VCC
3:5,16,32,66,73,78,90
I
Voltage supply, 5 V.
DSC_C
6
I
Clock for programming to access internal registers.
AUX[15:0]
40:38,36:34,20,18,14,
I/O Auxiliary control pins.
67:70,11,9,7
DSC_D[7:0]
81,83,85,93,95,97,99,8 I/O Data for programming to access internal registers.
DSC_S
10
I
Strobe for programming to access internal registers.
DCLK
O
Dual-purpose pin. DCLK is the MPEG decoder clock.
12
EXT_CLK
I
EXT_CLK is the external clock. EXT_CLK is an input during bypass PLL mode.
RST#
13
I
Video reset (active-low).
MUTE
15
O
Audio mute.
MCLK
17
I
Audio master clock.
TWS
I
Dual-purpose pin. TWS is the transmit audio frame sync.
19
SPLL_OUT
O
SPLL_OUT is the select PLL output.
8-4
51
VSSA
50
MIC1
49
MIC2
48
AOL
47
AOR
46
VCCA
45
VCCA
44
VREFP
43
VREFM
42
VSSA
41
AUX15
40
AUX14
39
AUX13
38
RBCK / SER_IN
37
AUX12
36
AUX11
35
AUX10
34
RSD / SEL_PLL0
33
VCC
32
VSS
31
30
Definition
VIDEO CD/DVD COMPANION PROCESSOR
ES3207
PIN DESCRIPTION
Name
Number
I/O
TSD
21
I
Transmit audio data input.
TBCK
22
I
Transmit audio bit clock.
RWS
23
O
Dual-purpose pin. RWS is the receive audio frame sync.
SEL_PLL1
I
Pins SEL_PLL[1:0] select the PLL clock frequency for the DCLK output.
SEL_PLL1
0
0
1
1
RSTOUT#
24
O
Reset output (active-low).
NC
27:28,65:76
No connect. Do not connect to these pins.
RSD
O
Dual-purpose pin. RSD is the receive audio data input.
33
I
SEL_PLL0 along with SEL_PLL1 select the PLL clock frequency for the DCLK out-
SEL_PLL0
put. See the table for pin number 23.
RBCK
O
Dual-purpose pin. RBCK is the receive audio bit clock.
I
SER_IN is the serial input DSC mode.
37
SER_IN
0 = Parallel DSC mode.
1 = Serial DSC mode.
VSSA
41,50:51,56:57,62:63
I
Analog ground.
VREFM
42
I
DAC and ADC minimum reference. Bypass to VCMR with 10 m F in parallel with 0.1 m F.
VREFP
43
I
DAC and ADC maximum reference. Bypass to VCMR with 10 m F in parallel with 0.1 m F.
VCCA
44:45,59:60
I
Analog VCC, 5 V.
AOR
46
O
Right channel output.
AOL
47
O
Left channel output.
MIC2
48
I
Microphone input 2.
MIC1
49
I
Microphone input 1.
VREF
52
I
Internal resistor divider generates Common Mode Reference (CMR) voltage.
Bypass to analog ground with 0.1 m F.
VCM
53
I
ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25 V.
Bypass to analog ground with 47 m F electrolytic in parallel with 0.1 m F.
RSET
54
I
Full scale DAC current adjustment.
COMP
55
I
Compensation pin.
CDAC
58
O
Modulated chrominance output.
YDAC
61
O
Y luminance data bus for screen video port.
VDAC
64
O
Composite video output.
XOUT
71
O
Crystal output.
XIN
74
I
27 MHz crystal input.
PCLK
79
I/O 13.5 MHz pixel clock.
PCLK2X
80
I/O 27 MHz (2 times pixel clock).
HSYNC#
82
O
Horizontal sync (active-low).
VSYNC#
84
O
Vertical sync (active-low).
YUV[7:0]
86:89,92,94,96,98
I
YUV data bus for screen video port.
8-4
Definition
SEL_PLL0
DCLK
0
Bypass PLL (input mode)
1
27 MHz (output mode)
0
32.4 MHz (output mode)
1
40.5 MHz (output mode)
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