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RDS/RBDS DECODER
BU1924F
BLOCK DIAGRAM
MUX
100k
4
270p
120k
100k
anti-aliasing
filter
V
ref
3
2.2µF
V
1
DD
5
1
Analog
Power supply
V
1
SS
6
PLL
PLL
57kHz
1187.5Hz
1
V
2
DD
12
RDS
Digital
2
Power supply
V
2
SS
11
Reference
clock
13
14
XI
XO
4.332MHz
33pF
33pF
3
3
7-8
560p
VSS3
7
8
CMP
V
3
SS
8th Switched
capacitor filter
comparator
RCLK
16
QUAL
1
RDATA
Bi-phase
Differential
2
decoder
decoder
Measurement
circuit
BU1924/F/FS
9
10
T1
T2
1: V
1 and V
2 are separated within the IC.
DD
DD
2: Have V
2(digital power supply) of a sufficiently low impedance.
DD
3: Match the capacitor constants with the crystal manufacturer.
RDS/RBDS DECODER
BU1924F
Pins Description
Pin No.
Symbol
Pin name
1
QUAL
Demodulator quality
Good data: High, bad data : Low
2
RDATA
Demodulator data
Refer to output data timing
3
Vref
Reference voltage
1/2 V
(refer to input/output circuits)
D
D1
4
MUX
Input
Composite signal input (refer to input/output circuits)
5
V
D D1
Analog power supply 4.5V to 5.5V
6
V
S S1
7
V
GND
S S3
8
CMP
Comparator input
C-junction (refer to input/output circuits )
9
T2
Test input
Open or connected to ground
10
T1
11
V
D
D2
Digital power supply 4.5V to 5.5V
12
V
S
S2
13
XI
Connects to 4.332MHz oscillator
Crystal oscillator
(refer to input/output circuits)
14
XO
15
(N.C.)
16
RCLK
Demodulator clock
1187.5Hz clock (refer to the timing diagram)
Type A
Type B
10M
Type D
Type E
+
+
7-8
Functions
Input/Output type
Type C
Type E
Type D
Type D
Type B
Type A
Type C
Type C
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