Pscan Hdmi Board Circuit Diagram - Philips DVP7400S/93 Service Manual

Circuit Diagram and PWB Layout
PSCAN HDMI Board Circuit Diagram - Part 1
1 2
P-scan_DeInterlacer
A
B
3103
C
27M_CLK
22R #
7100
FLI2310
HSYNC
4102
#
1
VSYNC
HSYNC1_PORT1
4103 2
#
VSYNC1_PORT1
3
3104 FIELD_ID1_PORT1
4
27M_CLK
IN_CLK1_PORT1
5
22R
HSYNC2_PORT1
6
D VSYNC2_PORT1
7
FIELD_ID2_PORT1
8
VDD1
9
VSS1
# #
10
IN_CLK2_PORT1
11
B|Cb|D1_0
12
B|Cb|D1_1
13
B|Cb|D1_2
14
B|Cb|D1_3
15
B|Cb|D1_4
16
VDDcore1
17
VSScore1
18
B|Cb|D1_5
19
B|Cb|D1_6
20
E B|Cb|D1_7
YB(0) 21
R|Cr|CbCr_0
YB(1) 22
R|Cr|CbCr_1
YB(2) 23
R|Cr|CbCr_2
YB(3) 24
R|Cr|Cb|Cr_3
YB(4) 25
R|Cr|CbCr_4
YB(5) 26
R|Cr|CbCr_5
YB(6) 27
R|Cr|CbCr_6
YB(7) 28
R|Cr|CbCr_7
29
G|Y|Y_0
30
VDD2
31
* VSS2
+3V3_D 32
3105 10K G|Y|Y_1
33
G|Y|Y_2
34
F
G|Y|Y_3
* 35
3106 10K G|Y|Y_4
36
VDDcore2
37
VSScore2
38
G|Y|Y_5
39
G|Y|Y_6
40
G|Y|Y_7
41
IN_SEL
42
TEST
43
DEV_ADDR1
44
P1
DEV_ADDR0
3107 22R
SCL_3V3 45
P1
SCLK
3108 22R
SDA_3V3 46
P2
SDATA
3151 22R 47
RESET
RESET_N
* 3168 47K 48
+3V3_D
G VDD3
49
2153 100p
3109 VSS3
DATA(0) 22R
50
3110 22R SDRAM_DATA_0
DATA(1) 51
SDRAM_DATA_1
3111 22R
DATA(2) 52
SDRAM_DATA_2
+1V8_CORE
+3V3_D
H
* Option
# Refer Variant Table
I
V
DC vtg measured in STOP-MODE
1 2
Ref Des
2105 2106 2108 3100 3101
Variant
DVDR755
100n 100n 10u 16V 10R 150R
YDVS1500
NOT USED NOT USED NOT USED NOT USED NOT USED
NOT USED NOT USED NOT USED
YDVS2500 NOT USED NOT USED
YDVC950
NOT USED NOT USED NOT USED NOT USED NOT USED
3139 785 32310
3 4 5 6
DECOUPLING CAP FOR FLI2301 / FLI2310
+3V3_D
#
2108
#
100n
+3V3_DAC
2106 10u 16V
# #
# #
3100 3101 3102 2105
10R 150R 27R
100n
DAC
+1V8_DAC
100n
2151
*
3 4 5 6
3102 3171 3167 3170 3172 3191 3192 3193
75R
NOT USED NOT USED 1R0 1R0 10K 10K
27R
NOT USED
NOT USED 4k7 4k7 NOT USED NOT USED 10K 10K
10K NOT USED
NOT USED NOT USED NOT USED 0R 0R 10K
NOT USED NOT USED NOT USED
NOT USED 4k7 4k7 0R 0R
7 EN 34
7 8 9
+1V8_CORE
DECOUPLING CAP FOR FLI2301/ FLI2310
DECOUPLING CAP FOR FLI2301 / FLI2310
+1V8_PLL
+3V3_DAC
PLL DAC
F106 DAC_R
F107 DAC_G
F108
DAC_B
+1V8_PLL
# # #
PLL
DAC DAC DAC DAC
156 P1
CLK
OE
155 P2,P4 47R 3154 YA(9)
G|Y|Y_OUT_7
P2,P4 P1
154 47R 3155 YA(8) CSN
G|Y|Y_OUT_6
153 P2,P4 47R 3156
YA(7)
G|Y|Y_OUT_5
152 P2,P4 47R 3157 P1
YA(6) WEN
G|Y|Y_OUT_4
151 P2,P4 47R 3165 YA(5)
G|Y|Y_OUT_3
P2,P4 47R 3166 P1
150 YA(4) CASN
G|Y|Y_OUT_2
149 P2,P4 47R 3179
YA(3)
G|Y|Y_OUT_1
P1
148 P2,P4 47R 3180 RASN
YA(2)
G|Y|Y_OUT_0
147
VSS8
146
VDD8 +3V3_D
145 P2,P4 47R 3181
YA(1)
R|V|PR_OUT_7
144 P2,P4 47R 3182 YA(0)
R|V|PR_OUT_6
P1
143 BA0
R|V|PR_OUT_5
142
R|V|PR_OUT_4
141 P1
BA1
R|V|PR_OUT_3
140
R|V|PR_OUT_2
139
VSScore7 +1V8_CORE
138 P1
ADD(0)
VDDcore7
137 P2,P4 47R 3184
UVA(9)
R|V|PR_OUT_1
P1
136 P2,P4 47R 3185 UVA(8) ADD(1)
R|V|PR_OUT_0
P2,P4
135 47R 3186 UVA(7)
B|U|Pb_OUT_7
134 P2,P4 47R 3187 P1
UVA(6) ADD(2)
B|U|Pb_OUT_6
133 P2,P4 47R 3188
UVA(5)
B|U|Pb_OUT_5
P1
132 P2,P4 47R 3189 UVA(4) ADD(3)
B|U|Pb_OUT_4
P2,P4
131 47R 3196 UVA(3)
B|U|Pb_OUT_3
130 P2,P4 47R 3197 P1
UVA(2) ADD(4)
B|U|Pb_OUT_2
129
VSS7
P1
128 ADD(5)
+3V3_D
VDD7
P2,P4
127 47R 3198 UVA(1)
B|U|Pb_OUT_1
126 P2,P4 47R 3199 P1
UVA(0) ADD(6)
B|U|Pb_OUT_0
125 P2,P4 47R 3183
P_CLK
CLKOUT
P1
124 ADD(7)
VSScore6 2150
123
VDDcore6 +1V8_CORE
122 P1
ADD(8)
CTLOUT4 10p
121
*
CTLOUT3 3169 22R
P2,P4 RESET_SII P1
120 ADD(9)
CTLOUT2
P2,P4 P_VSYNC
119
CTLOUT1
118 P2,P4 P_HSYNC P1
ADD(10)
CTLOUT0
117
TEST_OUT1
116
TEST_OUT0
115 P1
TEST3
3177 22R
114
CLK
SDRAM_CLKIN
113
VSS6
112 P1
+3V3_D
VDD6 3178 22R
111 CLK P1
SDRAM_CLKOUT II0
110 SRAM_DQM
P1
SDRAM_DQM
109
CSN
SDRAM_CSN P1
108 BA0
SDRAM_BA0
P1
107 BA1
SDRAM_BA1
P1
106
CASN
SDRAM_CASN
P1
105 RASN
SDRAM_RASN
+3V3D_V
P1
WEN
#
AV3
7 8 9
7121 7122
3194 3195 4102 4103 7100
75R 75R
NOT USED NOT USED FLI2301 NOT USED NOT USED
NOT USED NOT USED NOT USED NOT USED FLI2310 BSN20
BSN20
NOT USED NOT USED NOT USED NOT USED FLI2310 NOT USED NOT USED
NOT USED NOT USED USED USED FLI2310 NOT USED NOT USED
10 11 12 13
5100 F101
PLL
7103
* 4105
LF18ABT
100n
5101
F100 F102
+3V3_D
* 2154
IN OUT
GND
DAC 2102
220n
5102 F103
AP1
AZ1
7101
MT48LC2M32B2TG
81 75 55 49 41 35 9 3 43 29
10p VDDQ VDD
*
2152
67 CKE
+3V3_MEM
CTRL
68 CLK
LOGIC
20 CS_
3160 22R
17 WE_
BANK0
3161 22R 18 CAS_
ROW-
ADDR
3164 22R 19 RAS_
LATCH &
DECODER
MODE REG
3162 22R 22 BA0
BANK0
3163 22R 23 BA1 MEMORY
ARRAY
(4,096x256x16)
25 A0
SENSE AMPLIFIERS
26 A1
27 A2
60 A3
61 A4
62 A5
ROW
DQM0...3
ADDR
63 A6
MUX
I/O GATING
64 A7
DQM DATA LOGIC
READ DATA LATCH
65 A8 BANK
WRITE DRIVERS
CTRL
66 A9
LOGIC
24 A10
COLUMN
14
+3V3D_V ADDR
21 COUNTER/
LATCH
30
57
69
#
#
70
73
1R0
COLUMN
# 3170
DEDCODER
#
VSSQ VSS
#
3172
6 12 32 38 46 52 78 84 44 58 72 86
1R0
Part 1 3139_243_30807_a2_sh130_sh1.pdf
10 11 12 13
14 2100 A14 3163 E11
2101 A5 3164 D11
2102 A13 3165 D9
2103 A14 3166 D9
2105 B6 3167 G10
+1V8_CORE
2106 A5 3168 G1
2107 B14 3169 F8
2108 A6 3170 H10
47u
2109 B5 3171 H10
2110 A7 3172 I10
2100
2111 A6 3177 G8
+1V8_DAC A
2112 A6 3178 G8
2113 B8 3179 D9
47u 2114 A5 3180 D9
2115 A5 3181 D9
2116 A6 3182 D9
2103
2117 B8 3183 F8
+1V8_PLL
2118 A5 3184 E9
2119 A6 3185 E9
47u
2120 B8 3186 E9
2121 B8 3187 E9
2122 A8 3188 E9
2107
2123 A8 3189 E9
2124 A8 3190 D2
2125 A8 3191 D2
B
2126 A9 3192 D1
2127 A9 3193 C8
2128 A9 3194 C8
2130 B12 3195 C8
2131 B12 3196 E9
2132 B12 3197 E9
2133 B13 3198 F9
2134 B10 3199 F9
2135 B10 4100 F1
2136 B9 4101 F1
+3V3_MEM
2137 B9 4102 D1
C
2138 A9 4103 D1
15 1
2139 B9 4105 A10
2140 B13 5100 A13
DQM0 16
SRAM_DQM
2141 B13 5101 A13
2142 C14 5102 A13
DQM1 71
2143 C13 7100 C3
DQM2 28
2144 C13 7101 C12
2145 C12 7103 A12
DQM3 59
2146 C12 7121 G11
DQ0 2 2147 C13 7122 H11
DATA(0)
2148 B10 F100 A12
DQ1 4
DATA(1) 2149 B10 F101 A13
D
2150 F9 F102 A13
DQ2 5
DATA(2)
2151 C6 F103 A13
DQ3 7 2152 C11 F106 B8
DATA(3)
2153 G2 F107 B8
DQ4 8
2154 A10 F108 B8
DATA(4)
2155 B13
DQ5 10
DATA(5)
3100 B4
DQ6 11 3101 B5
DATA(6)
3102 B5
DQ7 13
DATA(7) 3103 C2
3104 D1
DQ8 74
DATA(8)
E 3105 F1
DQ9 76 3106 F1
DATA(9)
3107 G1
DQ10 77
3108 G1
DATA(10)
3109 G1
DQ11 79
DATA(11)
3110 G1
DQ12 80 3111 G1
DATA(12)
3112 I3
DQ13 82
DATA(13) 3113 I3
3114 I3
DQ14 83
DATA(14)
3115 I4
DQ15 85 3116 I3
DATA(15)
F
3117 I3
DQ16 31
3118 I4
DATA(16)
3119 I3
DQ17 33
DATA(17)
3120 I4
DQ18 34 3121 I4
DATA(18)
3122 I4
DQ19 36
DATA(19) 3123 I4
3124 I4
DQ20 37
DATA(20)
3125 I4
DQ21 39 3126 I5
DATA(21)
3127 I4
DQ22 40
3128 I5
DATA(22)
G
3129 I4
DQ23 42
DATA(23)
3130 I5
DQ24 45 3131 I5
DATA(24)
3132 I5
DQ25 47
DATA(25) 3133 I5
3134 I5
DQ26 48
DATA(26)
3135 I5
DQ27 50 3136 I5
DATA(27)
3137 I5
DQ28 51
DATA(28) 3138 I5
3139 I5
DQ29 53
DATA(29)
H 3140 I7
3141 I6
DQ30 54
DATA(30)
3142 I6
DQ31 56
3143 I6
DATA(31)
3144 I6
3145 I6
3146 I6
3147 I7
3148 I6
3149 I6
3150 C7
3151 G1
I
3152 C4
3153 C5
3154 D9
3155 D9
3156 D9
3157 D9
3158 I7
3159 I7
3160 D11
3161 D11
2005-04-01 3162 E11
14