Circuit Diagram and PWB Layout
7.
Zoran Peak Design DVP5900 - HD Companion Chip
5
D
FS1
FS2
OPEN
OPEN
CLOSE
CLOSE
7610
V ID0
1
VID0
VIN[0]
V ID1
2
VID1
VIN[1]
V ID2
3
VID2
VIN[2]
C
V ID3
4
VID3
VIN[3]
V ID4
5
VID4
VIN[4]
V ID5
6
VID5
VIN[5]
V ID6
7
VID6
VIN[6]
V ID7
8
VID7
VIN[7]
9
VDDIP
10
VDDC
VCLKX2
11
VCLKX2
VCLKx2
12
GNDC
13
GNDP
H SYNC
14
HSYNC
HSYNC/I2C_CFG0
VS YNC
15
VSYNC
FIELD/I2C_CFG1
16
VDDP
FS3
17
FS3
GPIO[9]
18
GPIO[8]
3612
19
4385CS
GPIO[7]
4.7K
/AUDIO_RESET
20
/AUDIO_RESET
GPIO[6]
3613
4.7K
3615
4.7K
HDVCC33
HDVCC18
B
S PDIF
SPDIF
CCLK
CDTI
HD _CLK
HD_CLK
HD_DAT
HD_DAT
RESET-
RESET-
A
HDVCC18
HDVCC33
HDVCC18
HDVCC33
2616
2615
2614
2613
2612
2611
2610
2609
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
5
3139 785 31770
7
4
C272 & C179 should be nearby Pin48 & Pin54 of
2601
+
2620
0.1uF
+
0.1uF
2621
2602
47uF/16V
100uF/16V
3601
392 ohm/1%
3602
3604
3605
75R/1%
75R/1%
75R/1%
3606
430 ohm/1%
60
AVDDT1_8
59
AGNDT1_8
58
CSET
57
AGNDT33
TMDS_D2+
56
TXDP2
55
TMDS_D2-
TXDN2
54
AVDDT33
TMDS_D1+
53
ZR36721
TXDP1
TMDS_D1-
52
TXDN1
51
AGNDT33
TMDS_D0+
50
TXDP0
TMDS_D0-
49
TXDN0
48
AVDDT33
TMDS_CLK+
47
TXCP
TMDS_CLK-
46
TXCN
45
AGNDT33
44
GNDPLL
TDMSGND
43
REFCLK
42
VDDPLL
41
RESET-
3609
HOTPLUG_F
0R
HOTPLUG
3610
10K
7603
PSS8550
5606
DSPVCC33
FB220R
2
3
DSPVCC33
HD_AVDDT33
3625
2.7K
3624
1K
7604
1
BC848
3626
1K
Power for I77_AVDDT33
4
EN 17
3
I77
5607
FB220R
HD_VD DDAC
5601
FB220R
HD_AVDDT33
HD_AVDDT18
5602
FB220R
HD_VDDPLL
5603
FB220R
2619
2603
2605
2607
+
+
+
0.1uF
0.1uF
2604
0.1uF
2606
0.1uF
2608
100uF/16V
100uF/16V
100uF/16V
HDVCC33
DSPVCC18
TMDS:
Transition Minimized Differential Signaling
3611
75R
OSCOUT
3614
NM
N.C.
GCLKA
5608
5609
TMDS_D2+
3
1
3
TMDS_D2-
4
2
4
NM
NM
5610
5611
TMDS_D1+
3
1
3
TMDS_D1-
4
2
4
NM
NM
Adjust pin current
3619
B1117-ADJ
55 or 60uA
2.87K/1%
90uA
2.8K/1%
A+12V
3617
A+12V
3.3R/1W
+
HDMI 5V.(4.95~5.05V)
3
2
HDVCC33
HD_AVDDT33
HDVCC18
HDV CC33
HDVCC33
DSPVCC18
Please Note:
TDMSGND should be
connected to GND
at a single point.
TMDS_D2+
TMDS_D2-
TMDS_D1+
TMDS_D1-
TMDS_D0+
TMDS_D0-
TMDS_CLK+
DDC signal Capacitance:
TMDS_CLK-
<50pF
TMDS_CLK+
1
TMDS_CLK-
7605
2
2N7002
A+12V
1
A+12V
7606
2N7002
1
DDCCLK
DDCCLK
D DCDAT
DDCDAT
TMDS_D0+
3608
1.8K
1
HDMI5V
TMDS_D0-
3607
1.8K
2
HDMI5V
HOTPLUG
7611
GND
TDMSGND
3619
2.87K/1%
3618
1K/1%
DSPVCC33
HDMI5V
HDMI5V
+
2623
2622
47uF/16V
47uF/16V
PHILIPS_5900_V40_0805_pg6.eps 2005-08-04
2
1
D
C
1601
HD port
1
TDMS_D2+
2
TDMS_D2_SHIELD
3
TDMS_D2-
4
TDMS_D1+
5
TDMS_D1_SHIELD
6
TDMS_D1-
7
TDMS_D0+
8
TDMS_D0_SHIELD
9
TDMS_D0-
10
TDMS_CLK+
11
TDMS_CLK_SHIELD
12
TDMS_CLK-
13
CEC
14
NC
15
SCL
16
SDA
17
DDC/CEC_GND
18
+5V
19
HOTPLUG
HDMI_TYPE_A
B
TDMSGND
DSPVCC33
A
1