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Auto Configuration
Choosing Enabled (default) will automatically configure chipset
features using default settings. Choose Disable to customize setup.
DRAM Speed Selection
The DRAM timing is controlled by the DRAM Timing Registers.
The timings programmed into this register are dependent on the system
design. Slower rates may be required in certain system designs to support
loose layouts or slower memory.
60ns
50ns
MA Wait State
This item allows you to select MA Wait State. The settings are Fast
or Slow.
EDO RAS# To CAS# Delay
This sets the relative delay between the row and column address
strobes from DRAM (EDO). The settings are 2 or 3.
EDO RAS# Precharge Time
Defines the length of time for Row Address Strobe from DRAM
(EDO) is allowed to precharge. The settings are 3 or 4.
EDO DRAM Read Burst
This sets the timing for burst mode reads from DRAM(EDO). Burst
Read and write requests are generated by the CPU in four separate parts.
The lower the timing numbers, the faster the system will address memory.
x222
x333
DRAM Timing Type.
DRAM Timing Type.
Read DRAM (EDO) timings are 2-2-2
Read DRAM (EDO) timings are 3-3-3
3-14
®
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