Keithley 7012-S Instruction Manual page 10

Figure 4-9
Common-emitter
characteristics of
an
NPN
silicon Transistor
4-13
Fig:ure
4-10
Path
isolation resistance
4-13
Figure 4-11 Voltage attenuation
by
path
isolation resistance
4-13
Figure 4-12
Power
line
ground
loops 4-15
Figure
4-13
Eliminating
ground
loops
4-15
Figure 5-1 Path
resistance
testing....
5-3
Figure 5-2
Common-mode
offset
current
testing..
5-5
Figure 5-3
Differential offset
current testing
-
5-5
Figure 5-4 Contact
potential testing
5-6
Figure 5-5 Path
isolation testing
(guarded) 5-8
Figure 5-6
Differential isolation testing
5-10
Figure 5-7
Common-mode
isolation testing
5-10
Figure 5-8
Model
7012 block
diagram
5-12
Figure 5-9
Start
and
stop sequences
5-13
Figure 5-10 Transmit
and acknowledge
sequence 5-14
IV