Output Amplifier; Range Switch; Bias Voltages - HP 59501A Operating And Service Manual

(U30) provides a bipolar output range from -2.5V to +2.5V
(nominal). Variable resistor R26 allows for a zero output
adjustment in the bipolar mode. The U30 output is applied
to the output amplifier through range resistors R45, R49,
and/or R52.
4-38 Output Amplifier
4-39 The output amplifier is comprised of a range
amplifier stage (operational amplifier U31), voltage gain
stages (Q3, Q4), and complementary emitter follower stages
(Q10, Q11). The gain of the amplifier is determined by
the range digit programmed.
4-40 When high range is programmed, range resistors
R45 and R49 are shunted through range switch FET Q5
(see paragraph 4-44). The high range gain of the output
amplifier is equal to — (R2 + R56) ^ R52. In the high
range, the amplifier provides a 0 to +9.99V output (unipolar
mode) or a -10V to +9.98V output (bipolar mode).
4-41 When low range is programmed, the gain of the
amplifier is equal to - (R2 R56) (R45 + R49 -i- R52).
In the low range, the amplifier's unipolar or bipolar output
is one tenth of the corresponding high range output.
Variable resistor R49 allows a low range gain adjustment
while the front panel D/A FULL SCALE ADJUST control
(R2) allows setting the maximum rated 59501A output
(±5%) in the high and low ranges.
4-42 Transistor stages Q3 and Q4 provide a voltage gain
for the iow level output (±1V max.) of operational amplifier
U31. Stages Q10 (positive) and Q11 (negative) provide
the unipolar or bipolar output voltage between terminals
A1 and A2. Output current up to 10mA is available and
is automaticaliy limited to 17mA (nominal). When terminal
A1 is negative with respect to , load current will flow
through the Q11 stage. When terminal A1 is positive with
respect to , ioad current will flow through the Q10
stage.
4-43 Diodes CR9 and CR11 protect the output amplifier
if an external voltage exceeding 25V (nominal) is connected
between the A1 and A2 terminals. If an excessive negative
voltage is applied, CR9 will clamp the output to -25V
(nom.). If an excessive positive voltage is applied, CR11
will clamp the output to +25V (nom.).
4-44 Range Switch
4-45 The range switch allows the output amplifier to
produce a high range or a low range output. The range
switch circuit (Q5, Q6) receives the RANGE signal level
from range iatch U26-14. A LO signal level specifies high
range while a HI signal ievel specifies low range.
4-46 If a LO level is received, transistor Q6 is turned-
off causing F ET Q5 to conduct. The F ET is used as a
switch which has a very low on resistance and a very high
off resistance. While conducting, Q5 couples the output of
U30 to the input of U31 via range resistor R52 (R45 and
R49 are bypassed).
4-47 If a HI level is received, transistor Q6 is turned-on
causing Q5 to turn-off. For this condition, the output of
U30 is coupled to the input of U31 through range resistors
R45, R49, and R52.
4-48 The spike suppressor circuit (in conjunction with
range amplifier U31) suppresses voltage spikes that occur
when the range switch is turned on or off, Voltage limiting
diodes CR8 and CRIO (Schottky's) protect U31 from
excessive input voltages.
4-49 Turn-On/Tum-Off Control
4-50 The turn-on/turn-off control circuit is comprised
of shift register B (U25), transistor stages (Q1, Q2) and
FET's Q7-Q9. The purpose of this circuit is to prevent
transients at power turn-on and turn-off from affecting the
output. To accomplish this, the output is clamped at a
low level when power is turned on or off.
4-51 Before power is turned-on, range amplifier U31 is
shunted by FET Q8, the output of amplifier stage Q4 is
clamped at a iow level by FET Q7, and FET Q9 ciamps the
output of the Q10 and Q11 stages to ground. When power
is turned-on, the Vdd supply voltage (junction R27 and R28)
resets U25 (U25-13 goes LO), turning on Q1. With Ql turned-
on, FET's Q7, Q8, and Q9 continue to conduct to maintain
the initial conditions (low-levei output). Note that when power
is turned-on, there is a delay before the -1 5V supply voltage
is available, consequently, Q2 is turned off at initial power
turn-on. After the delay, Q2 turns-on removing the reset
condition at U25. When the first data word is loaded into
data storage 2, shift register B output (U25-13) goes Hi
(see paragraph 4-33d) turning off Q1. With Ql off, FET's
Q7, Q8, and Q9 cutoff allowing the output amplifier to
provide an output determined by the programmed data
word.
4-52 At turn-off, the —15V supply voltage decays faster
than the +15V and Vdd supply voltages. When the -15V
supply decays sufficiently, U25 is reset (U25-13 goes LO)
turning on Ql which causes FET's Q7-Q9 to conduct.
Thus, the output is clamped at a low level during the decay
of the 5V and Vdd supply voltages.
4-53 Bias Voltages
4-54 The bias voltages for the digital and analog circuits
4-6