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Chapter 4: Connecting the Emulator to a Target System
Plugging The Emulator Into A Target System
immediately double bus fault. Verify that the data captured by the analyzer is
what is expected.
If the data for the vectors is wrong, a trace should be set up to check for access
problems during the fetch of the initial vectors. If the data is completely incorrect,
suspect an address or strobe timing problem. If only a few bits are wrong or if the
data in the trace is correct, suspect a data timing problem.
If the tracelist contains many cycles, start from the end and work backwards to
understand what caused the double bus fault. If the trace was completed before the
processor stopped, modify the trace specification to "trigger on nothing" so that the
last bus cycles preceding the double bus fault will be captured.
Wait until the emulator status shows a double bus fault, and then halt the trace.
tg never
reset the target system
es
th
tl -23
h>tl
Line
addr,H
6833x Mnemonic
-----
------
----------------------------------
-23
000100
Illegal Instruction: $4AFC
-22
000102
NOP
-21
0003fe
$0010
-20
0003f8
$2700
-19
0003fa
$0000
-18
0003fc
$0100
-17
000010
$0011
-16
000012
$1111
-15
0003f6
$00D6
-14
0003f4
$0000
-13
0003f0
$0000
-12
0003f2
$0100
-11
0003ec
$0011
-10
0003ee
$1111
-9
0003e8
$0011
-8
0003ea
$1111
-7
0003e6
$C00C
-6
0003e2
$0000
-5
0003e4
$0100
-4
0003e0
$2700
-3
00000c
$0033
-2
00000e
$3333
-1
h>
70
data word wr (ds16)
data word wr (ds16)
data word wr (ds16)
data word wr (ds16)
data word rd (ds16)
data word rd (ds16)
data word wr (ds16)
data word wr (ds16)
data word wr (ds16)
data word wr (ds16)
data word wr (ds16)
data word wr (ds16)
data word wr (ds16)
data word wr (ds16)
data word wr (ds16)
data word wr (ds16)
data word wr (ds16)
data word wr (ds16)
data word rd (ds16)
data word rd (ds16)
<- illegal inst
<- illegal inst stack
<- odd vector
<- address error stack
<- odd vector
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