Sapphire Pure Element PE-AM2RS485M Manual page 40

40
Timing Mode (Auto)
In Auto mode, the system reads the electronic data sheet of the memory
modules as provided within the serial presence detect (SPD) ROM on each
module and adjusts the timings accordingly. Most overclockers will prefer the
Manual settings that allow manual configuration of the following parameters
Memory clock value or Limit
This tab allows the user to manually specify the memory clock frequency
independent of the system bus frequency
LDT & PCI Bus Control
LDT is the acronym for Lightning Data Transport, which was the original
name for the bus protocol now known as HyperTransport. HyperTransport
uses a highly scalable bus interface in full duplex mode, which means that
there is one dedicated bus for upstream and one for downstream data
transfer (to and from the CPU, respectively). Each bit uses a low voltage
differential signaling (LVDS) scheme, which means that there are two
complementary data lines with mirror-symmetric signals that are compared
against each other. Each HT signaling pair provides 2000 Mbit/sec data
bandwidth using a DDR protocol on a 1000 MHz clock rate. Therefore, a 16 bit
interface will support as much as 4 GB/sec data bandwidth. Since concurrent
upstream and downstream data transports are supported, the theoretical
maximum bandwidth is 8 MB/sec
The maximum HT interface width supported by current AMD processors is 16
bit wide in each direction, however, the interface is scalable and allows
selective disabling of eight of the 16 data lines in each direction. For optimal
performance, all 16 lanes in both upstream and downstream signal
pathways should be enabled.
The LDT or HT interface is specified for optimal signal characteristics when
running at 1000 MHz, that is, the trace layout is optimized for 1 GHz clock rate.
Any frequency above or below the nominal value will generate resonance to
a certain extend and signal reflexions known as ringing. Therefore, it is
advisable to keep the LDT or HT frequency as close as possible to 1000 MHz.
Since the actual Hypertransport frequency is derived from the external bus
frequency and the multiplier, this means that if the external clock is overclocked,
the ratio of the LDT bus multiplier needs to be lowered to bring the resulting
LDT frequency back to 1000 MHz
LDT Configuration
Upstream LDT Bus Width
Downstream LDT Bus Width
LDT Bus Frequency
PCIE Reset Delay
: Move Enter: Select
F5: Previous Values
PE-AM2RS485M PE-AM2RS485M
PE-AM2RS485M User's Manual PE-AM2RS485M PE-AM2RS485M
Phoenix - Award WorkstationBIOS CMOS Setup Utility
LDT & PCI Bus Control
+/-/PU/PD: Value
F6:Fail-Safe Defaults
[Enabled]
[16 bit]
[16 bit]
[Auto]
[Disabled]
F10: Save
F7: Optimized Defaults
Item Help
Menu Level
ESC: Exit F1: General Help