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THEORY
OF OPERATION
INSTRUCTION
MANUAL
Digital Multimeler
Models
172.173
e)
The Auto-Cal
feedback
and
storage
block
works
in
a manner
identical
to
that
of
the
Auto-Zero
feedback
and
storage
block,
with
the
exception
that
its
output
current
is
fed
to
the
emitter
of
QlO2B
instead
of
the
summing
junction
of
UIOI.
Although
the
Auto-Zero
and Auto-Cal
correction
operations
interact
to some degree,
a few
sequential
iterations
of
these
operations
suffice
to
establish
the
correct
values
of
the
two
correction
currents.
d.
Overall
A/D System
Operation.
1.
In the
preceeding
two
sections
the
structure
and
function
of
each
major
analog
circuit
block
has been
explained.
This
section
contains
a description
of
the
manner
in which
these
elements
are
combined
in a complete
A/D
conversion.
The description
is
based
on Figure
32,
an overall
A/D converter
timing
diagram
showing
one
complete
conversion.
2.
The
first
major
division
of
the
conversion
period
is
into
an error-correction
segment
(120
ms long)
and
a signal-measurement
segment
(200
ms long).
During
the
former,
the
input
multiplexer
supplies
known
reference
voltages
to
the
V/F
block,
and
(as
described
in
Section
c )
the
correction
currents
I
and
I
During
the
latter,
the
now error-corrected
V/F
converter
hatZthe
un tl %%n
are
established.
signal
voltage
applied
to
its
input,
and
its
output
pulses
are
counted
by the
digital
chip.
(As
the
next
conversion
period
begins,
the
chip
processes
the
resulting
pulse-count
and dis-
plays
the
result.)
3.
The
error-coirection
segment
of
the
conversion
cycle
is
further
divided
into
three
40-msec.
phases.
During
the
first
two of
these
phases,
the
buffer
amplifier
gain
is
held
constant
at
either
IX or
IOX (depending
on DMM range
and
function).
During
the
AZ1 phase,
the
input
multiplexer
supplies
the
buffer
with
a zero-reference
voltage,
and
the
Auto-Zero
feedback
loop
is
closed.
The
value
of
IAZ required
to
correct
any
system
zero-err-ors
is
established,
and
the
closure
of
the
AZCI
switch
(see
Figure
31)
causes
the
source-follower
gate
voltage
which
produces
this
current
to be stored
on the
corresponding
Auto-Zero
storage
capacitor.
4.
During
the
ACAL phase,
the
multiplexer
connects
the
buffer
input
to a full-scale
reference
voltage
(either
3.34
or
0.334
V, depending
on buffer
gain),
and a similar
process
results
in a scale-factor
correction
voltage
being
stored
in
the
Auto-Cal
storage
capacitor.
5.
Buffer
gain
during
the
AZ2 phase
is always
the
same as
it
is
during
the
signal-
measurement
phase;
it
may differ
from
its
value
during
AZI
and ACAL.
Because
of
the
(possibly)
changed
buffer
gain,
the
effective
system
offsets
may have
changed
so the
second
Auto-Zero
operation
is
required
to
prepare
the
V/F
converter
for
an error-
corrected
signal
measurement.
This
new value
of
the
Auto-Zero
correction
voltage
is
stored
on the
capacitor
controlled
by the
AZC2 switch
(Figure
31.).
5-a.
MODEL 1722 DIGITAL
INTERFACE.
a.
Overall
Block
Diagram.
As shown
in
Figure
33
Serial
data
from
the
DMM and
its
associated
clock
lines
are
first
isolated.
Bidirect\onal
data
line
SERDAT is
then
split.
Output
data
DOWNDAT goes
to
the
output
register
block
where
it
is
converted
to
parallel
form
and
then
to
the
output
buffers.
The clock
lines
go to
the
control
block
which
decides
where
the
data
is
going,
out
or
in,
and also
generates
the
flag.
i-22
AA
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