Advertisement
INSTRUCTION
MANUAL
-
Dlgital Multimeter
Models 172, 173
THEORY OF OPERATION
4.
Figure
30
is
a simplified
schematic
diagram
of
the
c
.~
,ircuitry
actually
employed
to
perform
the
V/F
conversion.
In addition
to some added
details
of
the
circuitry
already
discussed,
Figure
30
shows
three
major
circuit
elements
not
previously
mentioned.
a)
The
input
buffer
amplifier,
U202,
serves
two
functions.
First
it
provides
a
high
impedance
input
to
the
A/D converter.
Second,
it
provides
a selectable
voltage
gain
of
10,
giving
the
A/D converter
in
effect
two
voltage
ranges,
selected
by the
line
labeled
GIO (an output
from
the
LSI
chip).
b)
The
transconductance
amplifier,
consisting
of
op amp UlOl
and
its
associated
MOS FET (QlO4)
and
resistors,
converts
the
voltage
which
appears
at
the
output
of
buffer
amplifier
LIZ02 into
a proportional
current,
Ix,
which
is
used
to charge
the
integrating
capacitor.
c)
The
reference
diode
and
the
resistor
connected
from
it
to
the
summing
junction
of
op amp UIOI
provide
a fixed
current
component
of
I
in addition
to
the
variable
component
I
(which
is
proportional
to
the
input
voltsge).
This
fixed
offset
current,
labeled
I
allows
the
overall
A/D
converter
to handle
both
positive
and
negative
input
vol?iges.
With
this
arrangement,
the
output
pulse
frequency
is one
half
of
its
maximum
possible
value
when
the
input
voltage
to
the
entire
converter
is
zero.
This
transposi.~tion
is
accounted
for
in
the
digital
subsystem
(LSI
chip)
by
subtracting
a fixed
number
from
the
accumulated
count
before
displaying
it.
d)
The
remaining
circuitry
in
Figure
30 is
functionally
equivalent
(with
some added
details)
to
the
basic
charge-balance
loop
shown
in
Figure
28.
The digital
output
signals
QR and
CLK are
used
by the
digital
subsystem,
in effect,
to
reconstitute
the
pulse
train
discussed
in connection
with
Figure
28.
C.
Auto-Zero
and
Auto-Calibrate
Circuitry.
1 .
The
charge
balance
system
shown
in
Figure
30.
is
inherently
highly
linear,
but
both
its
zero
and
full-scale
calibration
(scale
factor)
are
susceptible
to drift
with
time
and
temperature,
due
to a variety
of
effects.
Through
the
use of
a pair
of
related
circuit
functions,
referred
to
as Auto-Zero
and Auto-Calibrate,
these
intrinsic
errors
can
be cancelled,
resulting
in a system
whose
scale
factor
is
essentially
as stable
as the
voltage
of
a reference
zener
diode
and whose
zero
stability
is
limited
principally
by thermo-electric
offsets.
The
techniques
used
to
achieve
this
performance
are
described
in
this
section.
2.
It
can be shown
that
all
zero-error
sources
in
the
charge
balance
system
(such
as offset
voltage
drift
of
amplifiers
U202 and UIOI,
input
current
drift
of
amp-
lifier
UIOI,
etc.)
can
be represented
as a total
effective
error
current
at
the
summing
junction
of
amplifier
UlOl.
In a similar
way,
all
gain
errors
are
equiva-
lent
to
an error
current
at
the
emitter
of
the
reference
current
output
transistor,
Ql02B.
It
is
thus
possible
to correct
for
all
such
errors
by
introducing
an
approprrate
correction
current
at
each
of
these
two
locations
in
the
circuit.
The
function
of
the
Auto-Cal
and Auto-Zero
circuitry,
then,
is
to
discover
the
proper
values
of
these
two
currents
and
to
supply
them during
the
measurement
of
the
input
signal.
3.
The method
used
to "discover
" the
proper
value
of
the
correction
signals
is
as
follows:
Consider
first
the
Auto-Zero
operation.
In an error-free
system,
a zero-
volt
input
would
cause
the
charge-balance
loop
to deliver
reference-current
pulses
fo
the
integrator
at
exactly
l/2
the
clock
frequency.
In
the
Auto-Zero
mode,
the
buffer
input
is
supplied
with
zero
volts,
and
the
current
switch
is
digitally
forced
to deliver
reference-current
pulses
at
precisely
l/2
the
clock
frequency.
In
a real
system
with
finite
offset
errors,
the
current
being
delivered
to the
integrat-
Advertisement
