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In fixed mode (not locking to external source) one example of the application PLL jitter
performance on the xcore.ai multichannel audio board is shown below. Divided versions
of these clock frequencies will have similar jitter levels.
Desired Frequency
Actual Frequency
Frequency Error
Baseband Jitter
Frequency accuracy of 0ppm is possible for most clock frequencies but they are likely to
have higher jitter levels. The frequency accuracies in this example (<11ppm) are better
than would be expected of typical crystal oscillators so would only be an issue in systems
requiring synchronicity from multiple devices on a common 24MHz clock reference which
is quite rare.
Clock jitter of 7ps in the 100Hz - 40kHz baseband shows the ability to produce very high
quality DAC/ADC performance in the 0-20kHz audio band (jitter artefacts should be below
the noise floor for the majority of converters).
Of course a fixed audio master clock is only suitable for certain applications: Asynchronous
mode USB audio or standalone analog audio processing. For most other applications
(Synchronous or Adaptive mode USB audio, ext S/PDIF, ADAT or Word clock in sync), the
local master clock will need to be able to lock to an external clock rate. The Cirrus Logic
CS2100 makes this easy as it can generate a low jitter master clock output which is a
multiple of a low frequency input reference. The input reference can then come from the
clock we need to sync to e.g. word clock in, a signal that toggles every S/PDIF frame or
the USB start of frame for Synchronous mode USB.
The xcore.ai application PLL can also work in locking to external clock sources but it
requires a software PLL to be implemented which will use some processing power. Work
on this solution is ongoing.
The Skyworks Si5351A-B-GT device was included on the board as a fixed very low jitter
clock source to use for comparison in audio quality measurements. It has the potential to
be used in locking to external sources using a software PLL and this approach is being
investigated.
The selected master clock is buffered and distributed to the DAC circuitry, the ADC circuitry
and the digital output circuitry.
Audio interface clocks LRCK and BCLK are used in both I2S and TDM modes. These
clocks are outputs when the xcore is I2S/TDM master and inputs when xcore is I2S/TDM
slave. As outputs these clocks are divided down versions of the audio master clock. As
inputs these clocks must be generated by a source synchronous to the global audio
master clock.
14
xcore.ai Multichannel Audio Board 1v1 Hardware Manual
49.152MHz (1024x48kHz)
45.157895MHz
-11.2ppm
100Hz - 40kHz
7ps
100Hz - 1MHz
67ps
100Hz corner
215ps
45.1584MHz
(1024x44.1kHz)
49.151786MHz
-4.4ppm
7ps
70ps
118ps
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