Audio Clocking; Control Signal; Master Clock Source - XMOS XK-AUDIO-316-MC-AB Hardware Manual

11 Audio clocking

A flexible clocking scheme is provided to allow for experimentation with different clocking
architectures.
Figure 16:
Clocking
circuit
The audio master clock can be generated from one of three possible sources: the xcore.ai
secondary (application) PLL, a Cirrus Logic CS2100 Fractional-N clock multiplier, or a
Skyworks Si5351A-B-GT CMOS clock generator.
The master clock source is chosen by driving two control signals as shown below:

Control Signal

EXT_PLL_SEL
0
1
X
Each of the sources have potential benefits, some of which are discussed below:
The Cirrus CS2100 simplifies generating a master clock locked to an external clock
(such as S/PDIF in or word clock in).
It multiplies up the PLL_SYNC signal which is generated by the xcore.ai device based
on the desired external source (so S/PDIF in frame signal or word clock in).
The Si5351A-B-GT offers very low jitter performance at a relatively lower cost than the
CS2100. Locking to an external source is more difficult.
The xcore.ai application PLL is obviously the lowest cost and significantly lowest power
solution, however its jitter performance can not match the Si5351A which may be
important in demanding applications. Locking to an external clock is possible but
involves more complicated firmware and more MIPS.
13
xcore.ai Multichannel Audio Board 1v1 Hardware Manual

Master Clock Source

MCLK_DIR
0 Cirrus CS2100
0 Skyworks SI5351A-B-GT
1 xcore.ai secondary (application) PLL